Use the non-legacy drm_bus_flag _SAMPLE_ member.
No functional change.
Note:
DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE = DRM_BUS_FLAG_PIXDATA_NEGEDGE
Signed-off-by: Sam Ravnborg
Cc: Laurent Pinchart
Cc: Robert Chiras
Cc: Thierry Reding
Cc: Sam Ravnborg
---
On Tue, Jun 30, 2020 at 10:21 AM Anshuman Gupta
wrote:
>
> On 2020-06-23 at 21:29:05 +0530, Sean Paul wrote:
> Hi Sean,
> I am new to DP MST stuff, I am looking to DP MST spec DP v1.2a.
> I have looked the entire series, i will take up this opportunity to review
> the series from HDCP over DP MST
tree: git://people.freedesktop.org/~airlied/linux.git not-butter
head: f9de02ab2d4b7fc8d05e5fff0d5b4d8e474bbba5
commit: 9ef551714e1c0e9a800143eb927c68b6eadb87cb [2/12] flesh out mgrs a bit
config: i386-randconfig-m021-20200630 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-13) 9.3.0
On Mon, Jun 29, 2020 at 09:18:47PM +0200, Sam Ravnborg wrote:
> On Mon, Jun 29, 2020 at 11:57:37AM -0600, Rob Herring wrote:
> > On Mon, Jun 22, 2020 at 10:57 AM Daniel Thompson
> > wrote:
> > >
> > > On Fri, Jun 19, 2020 at 11:53:41PM +0200, Sam Ravnborg wrote:
> > > > > diff --git
> > > > >
Hi, Enric:
Enric Balletbo i Serra 於 2020年6月30日 週二 下午10:34寫道：
>
> Hi Sam, Chun-Kuan,
>
> On 20/6/20 23:33, Sam Ravnborg wrote:
> > Hi Enric
> >
> > On Mon, Jun 15, 2020 at 10:31:01PM +0200, Enric Balletbo i Serra wrote:
> >> (This resend is to fix some trivial conflicts due the merge window)
> >>
On 30.06.2020 10:59, Grygorii Strashko wrote:
> Hi
>
> On 29/06/2020 14:28, Andrzej Hajda wrote:
>> Hi Grygorii,
>>
>> (...)
>>
/*
* deferred_devs_show() - Show the devices in the deferred probe
pending list.
*/
@@ -221,7 +241,8 @@ static int
On Mon, Jun 29, 2020 at 01:22:39PM +0200, Andrzej Hajda wrote:
> During probe every time driver gets resource it should usually check for
> error printk some message if it is not -EPROBE_DEFER and return the error.
> This pattern is simple but requires adding few lines after any resource
>
tree: git://people.freedesktop.org/~airlied/linux.git not-butter
head: f9de02ab2d4b7fc8d05e5fff0d5b4d8e474bbba5
commit: 5212462bfe5c8cb3f783accd4afd40413c45ac57 [6/12] i915: hacks the planet
config: i386-allyesconfig (attached as .config)
compiler: gcc-9 (Debian 9.3.0-13) 9.3.0
reproduce (this
On Tue, Jun 30, 2020 at 05:41:32PM +0300, Laurent Pinchart wrote:
> Hi Ville,
>
> On Tue, Jun 30, 2020 at 05:39:02PM +0300, Ville Syrjälä wrote:
> > On Tue, Jun 30, 2020 at 10:19:23AM -0400, Alex Deucher wrote:
> > > On Tue, Jun 30, 2020 at 10:15 AM Ville Syrjälä wrote:
> > > >
> > > > On Tue,
tree: git://people.freedesktop.org/~airlied/linux.git not-butter
head: f9de02ab2d4b7fc8d05e5fff0d5b4d8e474bbba5
commit: aa9156566812da129f0ea379878ae97710347e76 [1/12] TTM JDI
config: i386-randconfig-m021-20200630 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-13) 9.3.0
If you fix
Hi Ville,
On Tue, Jun 30, 2020 at 05:39:02PM +0300, Ville Syrjälä wrote:
> On Tue, Jun 30, 2020 at 10:19:23AM -0400, Alex Deucher wrote:
> > On Tue, Jun 30, 2020 at 10:15 AM Ville Syrjälä wrote:
> > >
> > > On Tue, Jun 30, 2020 at 04:33:37PM +1000, Dave Airlie wrote:
> > > > Hey Laurent,
> > > >
On Tue, Jun 30, 2020 at 10:19:23AM -0400, Alex Deucher wrote:
> On Tue, Jun 30, 2020 at 10:15 AM Ville Syrjälä
> wrote:
> >
> > On Tue, Jun 30, 2020 at 04:33:37PM +1000, Dave Airlie wrote:
> > > Hey Laurent,
> > >
> > > I merged drm-misc-next and noticed this, I'm not sure if it's
> > >
tree: git://people.freedesktop.org/~airlied/linux.git not-butter
head: f9de02ab2d4b7fc8d05e5fff0d5b4d8e474bbba5
commit: 9ef551714e1c0e9a800143eb927c68b6eadb87cb [2/12] flesh out mgrs a bit
config: i386-allyesconfig (attached as .config)
compiler: gcc-9 (Debian 9.3.0-13) 9.3.0
reproduce (this
On 2020-06-23 at 21:29:05 +0530, Sean Paul wrote:
Hi Sean,
I am new to DP MST stuff, I am looking to DP MST spec DP v1.2a.
I have looked the entire series, i will take up this opportunity to review
the series from HDCP over DP MST POV.
I think theoretically this series should work or Gen12 as
On Tue, Jun 30, 2020 at 10:15 AM Ville Syrjälä
wrote:
>
> On Tue, Jun 30, 2020 at 04:33:37PM +1000, Dave Airlie wrote:
> > Hey Laurent,
> >
> > I merged drm-misc-next and noticed this, I'm not sure if it's
> > collateral damage from something else changing or I've just missed it
> > previously.
On Tue, Jun 30, 2020 at 04:33:37PM +1000, Dave Airlie wrote:
> Hey Laurent,
>
> I merged drm-misc-next and noticed this, I'm not sure if it's
> collateral damage from something else changing or I've just missed it
> previously. 32-bit arm build.
>
>
>
Hi Laurent.
On Tue, Jun 30, 2020 at 02:33:16AM +0300, Laurent Pinchart wrote:
> Hello,
>
> This small patch series is the second version of what has been
> previously submitted as "[PATCH] drm: panel: simple: Drop drive/sample
> bus flags for LVDS panels". It fixes incorrect bus format and
On Sat, 20 Jun 2020, Hans de Goede wrote:
> Hi All,
>
> Here is v3 of my patch series converting the i915 driver's code for
> controlling the panel's backlight with an external PWM controller to
> use the atomic PWM API. See below for the changelog.
>
> Initially the plan was for this series to
Hi Paul.
On Tue, Jun 30, 2020 at 01:52:09AM +0200, Paul Cercueil wrote:
> Add support for the Image Processing Unit (IPU) found in all Ingenic
> SoCs.
>
> The IPU can upscale and downscale a source frame of arbitrary size
> ranging from 4x4 to 4096x4096 on newer SoCs, with bicubic filtering
> on
Hi Paul.
On Tue, Jun 30, 2020 at 01:52:08AM +0200, Paul Cercueil wrote:
> All Ingenic SoCs starting from the JZ4725B support OSD mode.
>
> In this mode, two separate planes can be used. They can have different
> positions and sizes, and one can be overlayed on top of the other.
>
>
On SDM845 DSI needs to express a perforamnce state
requirement on a power domain depending on the clock rates.
Use OPP table from DT to register with OPP framework and use
dev_pm_opp_set_rate() to set the clk/perf state.
Signed-off-by: Rajendra Nayak
---
drivers/gpu/drm/msm/dsi/dsi.h | 2
These patches add DVFS support for DPU and DSI. Where posted
earlier as part of a series with multiple different drivers [1]
I have split them into specific driver changes in order to avoid
confusion on dependencies. Also added the corresponding device tree
changes for sdm845 and sc7180 platforms.
Add the OPP tables for DSI and MDP based on the perf state/clk
requirements, and add the power-domains property to specify the
scalable power domain.
Signed-off-by: Rajendra Nayak
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 49
1 file changed, 49
Add the OPP tables for DSI and MDP based on the perf state/clk
requirements, and add the power-domains property to specify the
scalable power domain.
Signed-off-by: Rajendra Nayak
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 59
1 file changed, 59
On some qualcomm platforms DPU needs to express a performance state
requirement on a power domain depending on the clock rates.
Use OPP table from DT to register with OPP framework and use
dev_pm_opp_set_rate() to set the clk/perf state.
Signed-off-by: Rajendra Nayak
Reviewed-by: Rob Clark
On Tue, Jun 30, 2020 at 01:52:07AM +0200, Paul Cercueil wrote:
> Move the register definitions to ingenic-drm.h, to keep
> ingenic-drm-drv.c tidy.
>
> Signed-off-by: Paul Cercueil
Acked-by: Sam Ravnborg
> ---
>
> Notes:
> v2: Fix SPDX license tag
>
>
Hi Paul.
On Tue, Jun 30, 2020 at 01:52:06AM +0200, Paul Cercueil wrote:
> The address of the DMA descriptor never changes. It can therefore be set
> in the probe function.
>
> Signed-off-by: Paul Cercueil
> ---
>
> Notes:
> v2: No change
>
> drivers/gpu/drm/ingenic/ingenic-drm-drv.c | 5
On Sat, Jun 27, 2020 at 12:43 PM Vladimir Oltean wrote:
>
> Hi Nick,
>
> On Mon, 22 Jun 2020 at 19:50, Nick Desaulniers
> wrote:
> >
>
> > > I really don't get what's the problem here. The listing of
> > > ld9040_prepare at the given commit and with the given .config is:
> >
> > I wrote a tool
On Tue, Jun 30, 2020 at 01:52:05AM +0200, Paul Cercueil wrote:
> plane->index is NOT the index of the color plane in a YUV frame.
> Actually, a YUV frame is represented by a single drm_plane, even though
> it contains three Y, U, V planes.
>
> Cc: sta...@vger.kernel.org # v5.3
> Fixes:
On Tue, 16 Jun 2020, Colin Ian King wrote:
> On 16/06/2020 12:54, Dan Carpenter wrote:
>> On Tue, Jun 16, 2020 at 12:42:21PM +0100, Colin King wrote:
>>> From: Colin Ian King
>>>
>>> Currently there is no null check for a failed memory allocation
>>> on the dsb object and without this a null
On 6/29/20 1:59 AM, Dmitry Osipenko wrote:
28.06.2020 14:16, Mikko Perttunen пишет:
On 6/26/20 7:35 PM, Dmitry Osipenko wrote:
26.06.2020 10:34, Thierry Reding пишет:
On Fri, Jun 26, 2020 at 01:47:46AM +0300, Dmitry Osipenko wrote:
23.06.2020 15:09, Mikko Perttunen пишет:
###
Use recently introduced common wrappers operating directly on the struct
sg_table objects and scatterlist page iterators to make the code a bit
more compact, robust, easier to follow and copy/paste safe.
No functional change, because the code already properly did all the
scaterlist related calls.
On 6/29/20 3:00 AM, Dmitry Osipenko wrote:
28.06.2020 13:28, Mikko Perttunen пишет:
On 6/28/20 1:32 AM, Dmitry Osipenko wrote:
23.06.2020 15:09, Mikko Perttunen пишет:
/* Command is an opcode gather from a GEM handle */
#define DRM_TEGRA_SUBMIT_COMMAND_GATHER 0
/* Command is an
On 6/29/20 10:42 PM, Dmitry Osipenko wrote:
Secondly, I suppose neither GPU, nor DLA could wait on a host1x sync
point, correct? Or are they integrated with Host1x HW?
They can access syncpoints directly. (That's what I alluded to in the
"Introduction to the hardware" section :) all those
On Tue, Jun 30, 2020 at 01:52:04AM +0200, Paul Cercueil wrote:
> If you pass a string that is not terminated with a carriage return to
> dev_err(), it will eventually be printed with a carriage return, but
> not right away, since the kernel will wait for a pr_cont().
>
> Signed-off-by: Paul
On Tue, Jun 30, 2020 at 01:52:03AM +0200, Paul Cercueil wrote:
> Full rename without any modification, except to the Makefile.
>
> Renaming ingenic-drm.c to ingenic-drm-drv.c allow to decouple the module
> name from the source file name in the Makefile. This will be useful
> later when more
On Tue, Jun 30, 2020 at 01:52:02AM +0200, Paul Cercueil wrote:
> Add documentation of the Device Tree bindings for the Image Processing
> Unit (IPU) found in most Ingenic SoCs.
>
> Signed-off-by: Paul Cercueil
Do not know the IPU but looks correct.
Acked-by: Sam Ravnborg
> ---
>
> Notes:
>
On 21.06.2020 06:00, Dmitry Osipenko wrote:
> В Fri, 19 Jun 2020 12:36:31 +0200
> Marek Szyprowski пишет:
>
>> The Documentation/DMA-API-HOWTO.txt states that the dma_map_sg()
>> function returns the number of the created entries in the DMA address
>> space. However the subsequent calls to the
>>
On Tue, Jun 30, 2020 at 11:32 AM Andrzej Hajda wrote:
> On 29.06.2020 18:36, Andy Shevchenko wrote:
> > On Mon, Jun 29, 2020 at 2:22 PM Andrzej Hajda wrote:
> >> /sys/kernel/debug/devices_deferred property contains list of deferred
> >> devices.
> >> This list does not contain reason why the
On Tue, 16 Jun 2020, Colin King wrote:
> From: Colin Ian King
>
> There are a couple of spelling mistakes in kernel parameter help text,
> namely "helpfull" and "paramters". Fix them.
>
> Signed-off-by: Colin Ian King
Pushed, thanks for the patch.
BR,
Jani.
> ---
>
Hi,
On 6/30/20 11:06 AM, Daniel Vetter wrote:
On Mon, Jun 29, 2020 at 11:39 AM Hans de Goede wrote:
Hi,
On 6/25/20 2:00 PM, Thomas Zimmermann wrote:
This patchset adds support for simple-framebuffer platform devices and
a handover mechanism for native drivers to take-over control of the
On Thu, Jun 25, 2020 at 02:00:10PM +0200, Thomas Zimmermann wrote:
> Platform devices might operate on firmware framebuffers, such as VESA or
> EFI. Before a native driver for the graphics hardware can take over the
> device, it has to remove any platform driver that operates on the firmware
>
On Fri, Jun 26, 2020 at 04:59:45PM +0300, Dmitry Osipenko wrote:
> 26.06.2020 16:38, Daniel Vetter пишет:
> > On Fri, Jun 26, 2020 at 01:40:40PM +0200, Thierry Reding wrote:
> >> On Fri, Jun 26, 2020 at 01:06:58PM +0200, Karol Herbst wrote:
> >>> On Tue, Jun 23, 2020 at 3:03 PM Mikko Perttunen
On Mon, Jun 29, 2020 at 11:39 AM Hans de Goede wrote:
>
> Hi,
>
> On 6/25/20 2:00 PM, Thomas Zimmermann wrote:
> > This patchset adds support for simple-framebuffer platform devices and
> > a handover mechanism for native drivers to take-over control of the
> > hardware.
> >
> > The new driver,
On Mon, Jun 29, 2020 at 08:13:51PM -0600, Rob Herring wrote:
> On Mon, Jun 29, 2020 at 10:04 AM Greg KH wrote:
> >
> > On Mon, Jun 29, 2020 at 11:22:30AM +0200, Daniel Vetter wrote:
> > > On Thu, Jun 25, 2020 at 02:00:11PM +0200, Thomas Zimmermann wrote:
> > > > We register the simplekms device
Hi All,
On 19.06.2020 12:36, Marek Szyprowski wrote:
> During the Exynos DRM GEM rework and fixing the issues in the.
> drm_prime_sg_to_page_addr_arrays() function [1] I've noticed that most
> drivers in DRM framework incorrectly use nents and orig_nents entries of
> the struct sg_table.
>
> In
The Documentation/DMA-API-HOWTO.txt states that the dma_map_sg() function
returns the number of the created entries in the DMA address space.
However the subsequent calls to the dma_sync_sg_for_{device,cpu}() and
dma_unmap_sg must be called with the original number of the entries
passed to the
On 29.06.2020 18:36, Andy Shevchenko wrote:
> On Mon, Jun 29, 2020 at 2:22 PM Andrzej Hajda wrote:
>> /sys/kernel/debug/devices_deferred property contains list of deferred
>> devices.
>> This list does not contain reason why the driver deferred probe, the patch
>> improves it.
>> The natural
It doesn't hurt to add the bridge in the global bridge list also for
platform specific dw-hdmi drivers which are based on the component
framework. This can be achieved by moving the drm_bridge_add() function
call from dw_hdmi_probe() to __dw_hdmi_probe(). A counterpart movement
for
Add documentation of the Device Tree bindings for the Image Processing
Unit (IPU) found in most Ingenic SoCs.
Signed-off-by: Paul Cercueil
---
Notes:
v2: Add missing 'const' in items list
.../bindings/display/ingenic,ipu.yaml | 65 +++
1 file changed, 65
Initialize hardware clock-gating registers on A640 and A650 GPUs.
I put the hwcg tables in adreno_device.c, but maybe it makes more
sense to keep them in a6xx_gpu.c? (this would allow switching a5xx
to use the gpulist too.. it isn't possible to include both a6xx.xml.h
and a5xx.xml.h in
Hi,
This is v3 of the seqlock patch series:
[PATCH v1 00/25] seqlock: Extend seqcount API with associated locks
https://lore.kernel.org/lkml/20200519214547.352050-1-a.darw...@linutronix.de
[PATCH v2 00/18]
https://lore.kernel.org/lkml/20200608005729.1874024-1-a.darw...@linutronix.de
plane->index is NOT the index of the color plane in a YUV frame.
Actually, a YUV frame is represented by a single drm_plane, even though
it contains three Y, U, V planes.
Cc: sta...@vger.kernel.org # v5.3
Fixes: 90b86fcc47b4 ("DRM: Add KMS driver for the Ingenic JZ47xx SoCs")
Signed-off-by: Paul
Initialize hardware clock-gating registers on A640 and A650 GPUs.
At least for A650, this solves some performance issues.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a6xx.xml.h | 8 ++
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 11 ++-
A650 has a separate RSCC region, so dump RSCC registers separately, reading
them from the RSCC base. Without this change a GPU hang will cause a system
reset if CONFIG_DEV_COREDUMP is enabled.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 5 +
Hi Alexander,
thanks for trying to fix this, yet I have some doubts.
On Mon, Jun 29, 2020 at 10:31:21PM +0200, Alexander A. Klimov wrote:
> Rationale:
> https://lore.kernel.org/linux-doc/20200626110706.7b5d4...@lwn.net/
I think we need some text here. Clicking on a link to understand what a
Laurent Pinchart wrote on
Tue, 30 Jun 2020 02:33:18 +0300:
> The Satoz SAT050AT40H12R2 panel is an LVDS panel, the
> MEDIA_BUS_FMT_RGB888_1X24 bus format is thus incorrect. Set it to the
> correct value MEDIA_BUS_FMT_RGB888_1X7X4_SPWG.
>
> Signed-off-by: Laurent Pinchart
> ---
>
29.06.2020 13:27, Mikko Perttunen пишет:
...
3. Sync points should be properly refcounted. Job's sync points
shouldn't be re-used while job is alive.
4. The job's sync point can't be re-used after job's submission (UAPI
constraint!). Userspace must free sync point and
Commit 3c3b177a9369 ("reservation: add support for read-only access
using rcu") introduced a sequence counter to manage updates to
reservations. Back then, the reservation object initializer
reservation_object_init() was always inlined.
Having the sequence counter initialization inlined meant
From: Sharat Masetty
The last level system cache can be partitioned to 32 different
slices of which GPU has two slices preallocated. One slice is
used for caching GPU buffers and the other slice is used for
caching the GPU SMMU pagetables. This talks to the core system
cache driver to acquire
Am 29.06.20 um 23:10 schrieb Wolfram Sang:
Hi Alexander,
thanks for trying to fix this, yet I have some doubts.
On Mon, Jun 29, 2020 at 10:31:21PM +0200, Alexander A. Klimov wrote:
Rationale:
https://lore.kernel.org/linux-doc/20200626110706.7b5d4...@lwn.net/
I think we need some text
All Ingenic SoCs starting from the JZ4725B support OSD mode.
In this mode, two separate planes can be used. They can have different
positions and sizes, and one can be overlayed on top of the other.
Signed-off-by: Paul Cercueil
---
Notes:
v2: Use fallthrough; instead of /* fall-through */
Move the register definitions to ingenic-drm.h, to keep
ingenic-drm-drv.c tidy.
Signed-off-by: Paul Cercueil
---
Notes:
v2: Fix SPDX license tag
drivers/gpu/drm/ingenic/ingenic-drm-drv.c | 116 +---
drivers/gpu/drm/ingenic/ingenic-drm.h | 126 ++
2
The standard binding for DSI requires, that the channel number
of the panel is encoded in DT. This adds the channel number in
all OMAP3-5 boards, in preparation for using common infrastructure.
Signed-off-by: Sebastian Reichel
---
arch/arm/boot/dts/motorola-mapphone-common.dtsi | 3 ++-
It's unnecessary to cleanup the i2c adapter and the ddc pointer in
the bailout path of __dw_hdmi_probe(), since the adapter is not
added and the ddc pointer is not set.
Fixes: a23d6265f033 (drm: bridge: dw-hdmi: Extract PHY interrupt setup to a
function)
Cc: Andrzej Hajda
Cc: Neil Armstrong
29.06.2020 13:27, Mikko Perttunen пишет:
...
4. The job's sync point can't be re-used after job's submission (UAPI
constraint!). Userspace must free sync point and allocate a new one for
the next job submission. And now we:
- Know that job's sync point is always in a
From: Sharat Masetty
The register read-modify-write construct is generic enough
that it can be used by other subsystems as needed, create
a more generic rmw() function and have the gpu_rmw() use
this new function.
Signed-off-by: Sharat Masetty
Reviewed-by: Jordan Crouse
Signed-off-by: Sai
On 2020-06-25 06:37, Stephen Boyd wrote:
Quoting Harigovindan P (2020-02-17 00:58:42)
diff --git a/arch/arm64/boot/dts/qcom/sc7180-idp.dts
b/arch/arm64/boot/dts/qcom/sc7180-idp.dts
index 388f50ad4fde..349db8fe78a5 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-idp.dts
+++
Neil,
yaml is the v3 version, there was no change , so i had not created v4 for yaml
[PATCH v3 2/2] display/drm/bridge: TC358775 DSI/LVDS driver
On Mon, Jun 29, 2020 at 2:08 PM Neil Armstrong wrote:
>
> Hi,
>
> On 21/06/2020 17:38, Vinay Simha BN wrote:
> > Signed-off-by: Vinay Simha BN
> >
>
From: Jordan Crouse
Add a new implementation hook to allow the implementation specific code
to tweek the context bank configuration just before it gets written.
The first user will be the Adreno GPU implementation to turn on
SCTLR.HUPCF to ensure that a page fault doesn't terminating pending
Hi Laurent,
[...]
> >
> > +static const struct display_timing satoz_sat050at40h12r2_timing = {
> > + .pixelclock = {3330, 3330, 5000},
> > + .hactive = {800, 800, 800},
> > + .hfront_porch = {16, 210, 354},
> > + .hback_porch = {46, 46, 46},
> > + .hsync_len = {1, 1, 40},
Add Droid 4 specific compatible value in addition to the
generic one, so that we have the ability to add panel
specific quirks in the future.
Signed-off-by: Sebastian Reichel
---
arch/arm/boot/dts/motorola-mapphone-common.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
Add iommu domain attribute for using system cache aka last level
cache by client drivers like GPU to set right attributes for caching
the hardware pagetables into the system cache.
Signed-off-by: Sai Prakash Ranjan
---
drivers/iommu/arm-smmu.c | 17 +
drivers/iommu/arm-smmu.h |
Subject: panel-dsi-cm: update bindings
The cleanup series for omapdrm's DSI code got too big. Reviewing
this is not fun and the same goes for keeping track of the change
requests. Let's do the cleanup in smaller steps instead. This is
the first batch, which updates the binding (txt -> yaml) and
A sequence counter write side critical section must be protected by some
form of locking to serialize writers. If the serialization primitive is
not disabling preemption implicitly, preemption has to be explicitly
disabled before entering the sequence counter write side critical
section.
The
Convert panel-dsi-cm bindings to YAML and add
missing properties while at it.
Signed-off-by: Sebastian Reichel
---
.../bindings/display/panel/panel-dsi-cm.txt | 29 -
.../bindings/display/panel/panel-dsi-cm.yaml | 100 ++
2 files changed, 100 insertions(+), 29
Some hardware variants contain a system cache or the last level
cache(llc). This cache is typically a large block which is shared
by multiple clients on the SOC. GPU uses the system cache to cache
both the GPU data buffers(like textures) as well the SMMU pagetables.
This helps with improved render
If you pass a string that is not terminated with a carriage return to
dev_err(), it will eventually be printed with a carriage return, but
not right away, since the kernel will wait for a pr_cont().
Signed-off-by: Paul Cercueil
---
Notes:
v2: New patch
On 6/27/20 4:18 PM, Greg Kroah-Hartman wrote:
> On Wed, May 20, 2020 at 03:39:31PM +0200, Erwan Le Ray wrote:
>> Add support of generic DT binding for annoucing RTS/CTS lines. The initial
>> binding 'st,hw-flow-control' is not needed anymore since generic binding
>> is available, but is kept for
Support multiple panels or bridges connected to the same DPI output of
the SoC. This setup can be found for instance on the GCW Zero, where the
same DPI output interfaces the internal 320x240 TFT panel, and the ITE
IT6610 HDMI chip.
Signed-off-by: Paul Cercueil
---
Notes:
v2: No change
Use of_match_node() to match qcom implementation instead
of multiple of_device_compatible() calls for each qcom
implementation.
Signed-off-by: Sai Prakash Ranjan
---
drivers/iommu/arm-smmu-impl.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git
Convert the ingenic,lcd.txt to a new ingenic,lcd.yaml file.
In the process, the new ingenic,jz4780-lcd compatible string has been
added.
Reviewed-by: Rob Herring
Acked-by: Sam Ravnborg
Signed-off-by: Paul Cercueil
---
Notes:
v2: Add info about IPU at port@8
The address of the DMA descriptor never changes. It can therefore be set
in the probe function.
Signed-off-by: Paul Cercueil
---
Notes:
v2: No change
drivers/gpu/drm/ingenic/ingenic-drm-drv.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git
Hi Laurent,
Good catch. It's actually the connector type which is wrong. The
connector_type should be DRM_MODE_CONNECTOR_DPI. If you would include
this in your patch series, you can have my acked-by.
Regards,
Pascal
On 2020-06-28 09:28, Laurent Pinchart wrote:
Hi Pascal,
On Fri, Mar 20,
This will allow supporting different hwcg tables for a6xx.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 129 ++---
drivers/gpu/drm/msm/adreno/adreno_device.c | 111 ++
drivers/gpu/drm/msm/adreno/adreno_gpu.h| 7 ++
3 files
Hi!
On Fri, Jun 05, 2020 at 04:44:51PM +0800, Jian-Hong Pan wrote:
> Maxime Ripard 於 2020年6月2日 週二 下午7:04寫道：
> >
> > Hi,
> >
> > On Mon, Jun 01, 2020 at 03:58:26PM +0800, Jian-Hong Pan wrote:
> > > Maxime Ripard 於 2020年5月28日 週四 下午3:30寫道：
> > > >
> > > > Hi Daniel,
> > > >
> > > > On Wed, May 27,
Add a quirk IO_PGTABLE_QUIRK_SYS_CACHE to override the
attributes set in TCR for the page table walker when
using system cache.
Signed-off-by: Sai Prakash Ranjan
---
drivers/iommu/io-pgtable-arm.c | 7 ++-
include/linux/io-pgtable.h | 4
2 files changed, 10 insertions(+), 1
Rationale:
https://lore.kernel.org/linux-doc/20200626110706.7b5d4...@lwn.net/
Signed-off-by: Alexander A. Klimov
---
@Jon I thought about what I said and *no*, unfortunately I *can't* automate
the detection of such as easy as the HTTPSifying. As you maybe see below
cleaning up is even
29.06.2020 13:27, Mikko Perttunen пишет:
...
>> We don't need a dedicated sync point FD for all kinds of jobs, don't we?
>> For example, I don't see why a sync point FD may be needed in a case of
>> Opentegra jobs.
>
> I think it's cleaner if we have just one way to allocate syncpoints, and
>
Full rename without any modification, except to the Makefile.
Renaming ingenic-drm.c to ingenic-drm-drv.c allow to decouple the module
name from the source file name in the Makefile. This will be useful
later when more source files are added.
Signed-off-by: Paul Cercueil
---
Notes:
v2: New
Add support for the Image Processing Unit (IPU) found in all Ingenic
SoCs.
The IPU can upscale and downscale a source frame of arbitrary size
ranging from 4x4 to 4096x4096 on newer SoCs, with bicubic filtering
on newer SoCs, bilinear filtering on older SoCs. Nearest-neighbour can
also be obtained
Add nodes for IDP display. The display is Visionox RM69299.
Signed-off-by: Harigovindan P
---
Changes in v2:
- Adding dependency patchwork series
- Removing suspend configuration
- Adding blank before space curly brace
Changes in v3:
- Updating status for mdp and
There are few places in arm-smmu-impl where there are
extra blank lines, remove them and while at it fix the
checkpatch warning for space required before the open
parenthesis.
Signed-off-by: Sai Prakash Ranjan
---
drivers/iommu/arm-smmu-impl.c | 6 +-
1 file changed, 1 insertion(+), 5
Add information about panel orientation, so that the
system boots into a properly rotated shell.
Signed-off-by: Sebastian Reichel
---
arch/arm/boot/dts/motorola-mapphone-common.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/motorola-mapphone-common.dtsi
Hi,
On 29/06/2020 10:47, Vinay Simha B N wrote:
> Neil,
>
> yaml is the v3 version, there was no change , so i had not created v4 for yaml
> [PATCH v3 2/2] display/drm/bridge: TC358775 DSI/LVDS driver
>
OK, please resend the whole patchset even with unchanged patches, you can
explain
which
Hey Laurent,
I merged drm-misc-next and noticed this, I'm not sure if it's
collateral damage from something else changing or I've just missed it
previously. 32-bit arm build.
/home/airlied/devel/kernel/dim/src/drivers/gpu/drm/omapdrm/omap_connector.c:
In function ‘omap_connector_mode_valid’:
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