idr_init() uses base 0 which is an invalid identifier. The new function
idr_init_base allows IDR to set the ID lookup from base 1. This avoids
all lookups that otherwise starts from 0 since 0 is always unused.
References: commit 6ce711f27500 ("idr: Make 1-based IDRs more efficient")
Add OPP and SoC core voltage scaling support to the GR3D driver.
This is required for enabling system-wide DVFS on Tegra SoCs.
Tested-by: Peter Geis
Tested-by: Nicolas Chauvet
Signed-off-by: Dmitry Osipenko
---
drivers/gpu/drm/tegra/gr3d.c | 136 +++
1 file
Increase the scaled image's theorical width/height until we find a
configuration that has valid scaling coefficients, up to 102% of the
screen's resolution. This makes sure that we can scale from almost
every resolution possible at the cost of a very small distorsion.
The CRTC_W / CRTC_H are not
On Wed, 04 Nov 2020 17:01:40 +
Simon Ser wrote:
> User-space doesn't need to keep track of blobs that might be in use by
> the kernel. User-space can just destroy blobs as soon as they don't need
> them anymore.
>
> Signed-off-by: Simon Ser
> Signed-off-by: Daniel Stone
> Reviewed-by:
On Thu, Nov 5, 2020 at 9:00 AM Christian König wrote:
>
> Am 04.11.20 um 17:50 schrieb Daniel Vetter:
> > Random observation while trying to review Christian's patch series to
> > stop looking at struct page for dma-buf imports.
> >
> > This was originally added in
> >
> > commit
On Wed, Nov 04, 2020 at 10:44:56AM -0800, John Hubbard wrote:
> On 11/4/20 10:17 AM, Jason Gunthorpe wrote:
> > On Wed, Nov 04, 2020 at 04:41:19PM +, Christoph Hellwig wrote:
> > > On Wed, Nov 04, 2020 at 04:37:58PM +, Christoph Hellwig wrote:
> > > > On Wed, Nov 04, 2020 at 05:26:58PM
Am 04.11.20 um 17:50 schrieb Daniel Vetter:
Random observation while trying to review Christian's patch series to
stop looking at struct page for dma-buf imports.
This was originally added in
commit 58aa6622d32af7d2c08d45085f44c54554a16ed7
Author: Thomas Hellstrom
Date: Fri Jan 3 11:47:23
Document new DVFS OPP table and voltage regulator properties of the
video decoder engine.
Signed-off-by: Dmitry Osipenko
---
.../devicetree/bindings/media/nvidia,tegra-vde.txt | 12
1 file changed, 12 insertions(+)
diff --git
We're going to modularize Tegra EMC drivers and some of the EMC-clock
driver symbols need to be exported, let's export them.
Acked-by: Thierry Reding
Signed-off-by: Dmitry Osipenko
---
drivers/clk/tegra/clk-tegra20-emc.c | 3 +++
1 file changed, 3 insertions(+)
diff --git
The latency allowness is calculated based on buffering capabilities of
memory clients. Add FIFO sizes to the Tegra30 memory clients.
Signed-off-by: Dmitry Osipenko
---
drivers/memory/tegra/tegra30.c | 66 ++
1 file changed, 66 insertions(+)
diff --git
Add interconnect properties to the Memory Controller, External Memory
Controller and the Display Controller nodes in order to describe hardware
interconnection.
Signed-off-by: Dmitry Osipenko
---
arch/arm/boot/dts/tegra30.dtsi | 27 ++-
1 file changed, 26 insertions(+),
Add common SoC-agnostic ICC framework which turns Tegra Memory Controller
into a memory interconnection provider. This allows us to use interconnect
API for tuning of memory configurations.
Tested-by: Peter Geis
Tested-by: Nicolas Chauvet
Signed-off-by: Dmitry Osipenko
---
Add OPP and SoC core voltage scaling support to the GR2D driver.
This is required for enabling system-wide DVFS on Tegra SoCs.
Tested-by: Peter Geis
Tested-by: Nicolas Chauvet
Signed-off-by: Dmitry Osipenko
---
drivers/gpu/drm/tegra/gr2d.c | 136 +++
1 file
Add devfreq support to the Tegra20 EMC driver. Memory utilization
statistics will be periodically polled from the memory controller and
appropriate minimum clock rate will be selected by the devfreq governor.
Signed-off-by: Dmitry Osipenko
---
drivers/memory/tegra/Kconfig | 2 +
Memory controller is interconnected with memory clients and with the
External Memory Controller. Document new interconnect property which
turns memory controller into interconnect provider.
Signed-off-by: Dmitry Osipenko
---
.../bindings/memory-controllers/nvidia,tegra124-emc.yaml | 1 +
The device-tree compatibles are swapped in the code, correct them.
Tested-by: Peter Geis
Tested-by: Nicolas Chauvet
Signed-off-by: Dmitry Osipenko
---
drivers/gpu/drm/tegra/gr2d.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/tegra/gr2d.c
External memory controller is interconnected with memory controller and
with external memory. Document new interconnect property which turns
External Memory Controller into interconnect provider.
Acked-by: Rob Herring
Signed-off-by: Dmitry Osipenko
---
Document new DVFS OPP table and voltage regulator properties of the
Host1x bus and devices sitting on the bus.
Signed-off-by: Dmitry Osipenko
---
.../display/tegra/nvidia,tegra20-host1x.txt | 56 +++
1 file changed, 56 insertions(+)
diff --git
Add nvidia,memory-controller to the Tegra20 External Memory Controller
node. This allows to perform a direct lookup of the Memory Controller
instead of walking up the whole tree. This puts Tegra20 device-tree on
par with Tegra30+.
Signed-off-by: Dmitry Osipenko
---
Now Internal and External memory controllers are memory interconnection
providers. This allows us to use interconnect API for tuning of memory
configuration. EMC driver now supports OPPs and DVFS.
Tested-by: Nicolas Chauvet
Signed-off-by: Dmitry Osipenko
---
drivers/memory/tegra/Kconfig
External memory controller is interconnected with memory controller and
with external memory. Document new interconnect property which turns
External Memory Controller into interconnect provider.
Reviewed-by: Rob Herring
Signed-off-by: Dmitry Osipenko
---
Add EMC OPP DVFS/DFS tables and interconnect paths that will be used for
dynamic memory bandwidth scaling based on memory utilization statistics.
Update board device-trees with optional EMC core supply and remove
unsupported OPPs.
Note that ACTMON watches all memory interconnect paths, but we use
Previously we were using count-weight of the T124 for T30 in order to
get EMC clock rate that was reasonable for T30. In fact the count-weight
should be x2 times smaller on T30, but then devfreq was producing a bit
too low EMC clock rate for ISO memory clients, like display controller
for example.
Add modularization support to the Tegra20 EMC driver, which now can be
compiled as a loadable kernel module.
Acked-by: Thierry Reding
Signed-off-by: Dmitry Osipenko
---
drivers/memory/tegra/Kconfig | 2 +-
drivers/memory/tegra/tegra20-emc.c | 17 -
2 files changed, 13
Document EMC DFS OPP table and interconnect paths that will be used
for scaling of system's memory bandwidth based on memory utilization
statistics. Previously ACTMON was supposed to drive EMC clock rate
directly, but now it should do it using interconnect framework in order
to support shared
Sync driver state using the Tegra SoC device state syncing API, telling
to regulators voltage coupler that EMC state is ready for DVFS. This is
required for enabling system-wide DVFS on Tegra30.
Tested-by: Peter Geis
Signed-off-by: Dmitry Osipenko
---
drivers/memory/tegra/tegra30-emc.c | 8
External Memory Controller is interconnected with memory controller and
with external memory. Document new interconnect property which turns EMC
into interconnect provider.
Acked-by: Rob Herring
Signed-off-by: Dmitry Osipenko
---
.../bindings/memory-controllers/nvidia,tegra20-emc.txt
The platform_get_irq() prints error message telling that interrupt is
missing, hence there is no need to duplicated that message in the drivers.
Signed-off-by: Dmitry Osipenko
---
drivers/memory/tegra/mc.c | 4 +---
drivers/memory/tegra/tegra20-emc.c | 1 -
Each memory client has unique hardware ID, add these IDs.
Reviewed-by: Rob Herring
Signed-off-by: Dmitry Osipenko
---
include/dt-bindings/memory/tegra124-mc.h | 68
1 file changed, 68 insertions(+)
diff --git a/include/dt-bindings/memory/tegra124-mc.h
Add modularization support to the Tegra124 EMC driver, which now can be
compiled as a loadable kernel module.
Note that EMC clock must be registered at clk-init time, otherwise PLLM
will be disabled as unused clock at boot time if EMC driver is compiled
as a module. Hence add a prepare/complete
Use devm_platform_ioremap_resource() helper which makes code a bit
cleaner.
Acked-by: Thierry Reding
Signed-off-by: Dmitry Osipenko
---
drivers/memory/tegra/tegra124-emc.c | 4 +---
drivers/memory/tegra/tegra20-emc.c | 4 +---
2 files changed, 2 insertions(+), 6 deletions(-)
diff --git
This patch moves ACTMON driver away from generating OPP table by itself,
transitioning it to use the table which comes from device-tree. This
change breaks compatibility with older device-trees in order to bring
support for the interconnect framework to the driver. This is a mandatory
change which
Multiple Tegra drivers need to retrieve Memory Controller and there is
duplication of the retrieval code among the drivers.
Add new devm_tegra_memory_controller_get() helper to remove the code's
duplication and to fix put_device() which was missed in the duplicated
code. Make EMC drivers to use
Each memory client has unique hardware ID, add these IDs.
Acked-by: Rob Herring
Signed-off-by: Dmitry Osipenko
---
include/dt-bindings/memory/tegra30-mc.h | 67 +
1 file changed, 67 insertions(+)
diff --git a/include/dt-bindings/memory/tegra30-mc.h
The tegra_read_ram_code() is used by EMC drivers and we're going to make
these driver modular, hence this function needs to be exported.
Acked-by: Thierry Reding
Signed-off-by: Dmitry Osipenko
---
drivers/soc/tegra/fuse/tegra-apbmisc.c | 2 ++
1 file changed, 2 insertions(+)
diff --git
It's useful to know the total number of underflow events and currently
the debug stats are getting reset each time CRTC is being disabled. Let's
account the overall number of events that doesn't get a reset.
Tested-by: Peter Geis
Tested-by: Nicolas Chauvet
Signed-off-by: Dmitry Osipenko
---
Document new OPP table and NVIDIA Tegra-specific voltage regulator
properties.
Signed-off-by: Dmitry Osipenko
---
Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt | 4
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt
Most of Host1x devices have at least one memory client. These clients
are directly connected to the memory controller. The new interconnect
properties represent the memory client's connection to the memory
controller.
Reviewed-by: Rob Herring
Signed-off-by: Dmitry Osipenko
---
Document new OPP table and voltage regulator properties which are needed
for supporting dynamic voltage-frequency scaling of the memory controller.
Some boards may have a fixed core voltage regulator, hence it's optional
because frequency scaling still may be desired.
Reviewed-by: Rob Herring
EMC driver will become mandatory after turning it into interconnect
provider because interconnect users, like display controller driver, will
fail to probe using newer device-trees that have interconnect properties.
Thus make EMC driver to probe even if timings are missing in device-tree.
Add EMC OPP DVFS/DFS tables and interconnect paths that will be used for
dynamic memory bandwidth scaling based on memory utilization statistics.
Remove unsupported EMC OPPs from board device-trees.
Note that ACTMON watches all memory interconnect paths, but we use a
single CPU-READ interconnect
Introduce sync state API that will be used by Tegra device drivers. This
new API is primarily needed for syncing state of SoC devices that are left
ON after bootloader or permanently enabled. All these devices belong to a
shared CORE voltage domain, and thus, we needed to bring all the devices
Add OPP tables for Tegra20 SoC devices.
Signed-off-by: Dmitry Osipenko
---
.../arm/boot/dts/tegra20-peripherals-opp.dtsi | 386 ++
arch/arm/boot/dts/tegra20.dtsi| 14 +
2 files changed, 400 insertions(+)
diff --git
There is superfluous zero in the registers base address and registers
size should be twice bigger.
Acked-by: Rob Herring
Acked-by: Thierry Reding
Signed-off-by: Dmitry Osipenko
---
.../bindings/memory-controllers/nvidia,tegra20-emc.txt | 2 +-
1 file changed, 1 insertion(+), 1
This series brings initial support for memory interconnect to Tegra20,
Tegra30 and Tegra124 SoCs.
For the starter only display controllers and devfreq devices are getting
interconnect API support, others could be supported later on. The display
controllers have the biggest demand for interconnect
Enable runtime PM before registering the fbdev emulation and disable it
afterward, otherwise register access to the LTDC IP during the fbdev
emulation registration might hang the system.
The problem happens because RPM is activated at the end of ltdc_load(),
but the fbdev emulation registration
The SoC core voltage can't be changed without taking into account the
clock rate of External Memory Controller. Document OPP table that will
be used for dynamic voltage frequency scaling, taking into account EMC
voltage requirement. Document optional core voltage regulator, which is
optional
Each memory client has unique hardware ID, add these IDs.
Acked-by: Rob Herring
Signed-off-by: Dmitry Osipenko
---
include/dt-bindings/memory/tegra20-mc.h | 53 +
1 file changed, 53 insertions(+)
diff --git a/include/dt-bindings/memory/tegra20-mc.h
Introduce core voltage scaling for NVIDIA Tegra20/30 SoCs, which reduces
power consumption and heating of the Tegra chips. Tegra SoC has multiple
hardware units which belong to a core power domain of the SoC and share
the core voltage. The voltage must be selected in accordance to a minimum
On Wed, Nov 04, 2020 at 10:15:49AM +, Robin Murphy wrote:
> On 2020-11-04 08:14, Maxime Ripard wrote:
> > Hi Christoph,
> >
> > On Tue, Nov 03, 2020 at 10:55:38AM +0100, Christoph Hellwig wrote:
> > > Linux 5.10-rc1 switched from having a single dma offset in struct device
> > > to a set of
Add initial OPP and SoC CORE voltage scaling support to the Tegra UDC
driver. This is required for enabling system-wide DVFS on older Tegra
SoCs.
Tested-by: Peter Geis
Signed-off-by: Dmitry Osipenko
---
drivers/usb/chipidea/Kconfig | 1 +
drivers/usb/chipidea/ci_hdrc_tegra.c | 79
Document new DVFS OPP table and voltage regulator properties of the
Tegra EHCI controller.
Signed-off-by: Dmitry Osipenko
---
Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git
Remove tegra20-devfreq in order to replace it with a EMC_STAT based
devfreq driver. Previously we were going to use MC_STAT based
tegra20-devfreq driver because EMC_STAT wasn't working properly, but
now that problem is resolved. This resolves complications imposed by
the removed driver since it
Add voltage supplies to DVFS-capable devices in order to enable
system-wide voltage scaling.
Signed-off-by: Dmitry Osipenko
---
.../tegra30-asus-nexus7-grouper-common.dtsi | 23 +++
1 file changed, 23 insertions(+)
diff --git
Memory controller is interconnected with memory clients and with the
External Memory Controller. Document new interconnect property which
turns memory controller into interconnect provider.
Acked-by: Rob Herring
Signed-off-by: Dmitry Osipenko
---
Fix voltage coupler lockup which happens when voltage-spread is out
of range due to a bug in the code. The max-spread requirement shall be
accounted when CPU regulator doesn't have consumers. This problem is
observed on Tegra30 Ouya game console once system-wide DVFS is enabled
in a device-tree.
Hi,
On (20/11/05 07:52), Gerd Hoffmann wrote:
> > - *ents = kmalloc_array(*nents, sizeof(struct virtio_gpu_mem_entry),
> > - GFP_KERNEL);
> > + *ents = kvmalloc_array(*nents,
> > + sizeof(struct virtio_gpu_mem_entry),
> > +
We observed that some of virtio_gpu_object_shmem_init() allocations
can be rather costly - order 6 - which can be difficult to fulfill
under memory pressure conditions. Switch to kvmalloc_array() in
virtio_gpu_object_shmem_init() and let the kernel vmalloc the entries
array.
Signed-off-by: Sergey
Add OPP and SoC core voltage scaling support to the Tegra SDHCI driver.
This is required for enabling system-wide DVFS on older Tegra SoCs.
Tested-by: Peter Geis
Tested-by: Nicolas Chauvet
Signed-off-by: Dmitry Osipenko
---
drivers/mmc/host/Kconfig | 1 +
drivers/mmc/host/sdhci-tegra.c
Tegra20 External Memory Controller talks to DRAM chips and it needs to be
reprogrammed when memory frequency changes. Tegra Memory Controller sits
behind EMC and these controllers are tightly coupled. This patch adds the
new phandle property which allows to properly express connection of EMC
and
Add voltage supplies to DVFS-capable devices in order to enable
system-wide voltage scaling and allow CORE/RTC regulators to go lower.
Signed-off-by: Dmitry Osipenko
---
.../boot/dts/tegra20-acer-a500-picasso.dts| 30 +--
1 file changed, 28 insertions(+), 2 deletions(-)
Add OPP tables for Tegra30 SoC devices.
Signed-off-by: Dmitry Osipenko
---
.../arm/boot/dts/tegra30-peripherals-opp.dtsi | 415 ++
arch/arm/boot/dts/tegra30.dtsi| 13 +
2 files changed, 428 insertions(+)
diff --git
Quoting Kuogee Hsieh (2020-11-03 12:49:02)
> Some dongles require link training done at irq_hpd request instead
> of plugin request. This patch promote irq_hpd handler to handle link
> training and setup hpd_state correctly.
>
> Fixes: fdaf9a5e3c15 (drm/msm/dp: fixes wrong connection state
On Thu, Nov 05, 2020 at 02:43:57AM +0300, Dmitry Osipenko wrote:
> Introduce core voltage scaling for NVIDIA Tegra20/30 SoCs, which reduces
> power consumption and heating of the Tegra chips. Tegra SoC has multiple
> hardware units which belong to a core power domain of the SoC and share
> the
On Wed, Nov 04, 2020 at 02:06:34PM -0800, Jianxin Xiong wrote:
> + umem = ib_umem_dmabuf_get(>ib_dev, offset, length, fd,
> access_flags,
> + _ib_dmabuf_attach_ops);
> + if (IS_ERR(umem)) {
> + mlx5_ib_dbg(dev, "umem get failed (%ld)\n",
Add initial OPP and SoC core voltage scaling support to the Host1x driver.
This is required for enabling system-wide DVFS on older Tegra SoCs.
Tested-by: Peter Geis
Tested-by: Nicolas Chauvet
Signed-off-by: Dmitry Osipenko
---
drivers/gpu/host1x/Kconfig | 1 +
drivers/gpu/host1x/dev.c | 87
Add OPP and SoC core voltage scaling support to the Tegra PWM driver.
This is required for enabling system-wide DVFS on older Tegra SoCs.
Tested-by: Peter Geis
Tested-by: Nicolas Chauvet
Signed-off-by: Dmitry Osipenko
---
drivers/pwm/Kconfig | 1 +
drivers/pwm/pwm-tegra.c | 84
Add OPP and SoC core voltage scaling support to the HDMI driver.
This is required for enabling system-wide DVFS on older Tegra SoCs.
Signed-off-by: Dmitry Osipenko
---
drivers/gpu/drm/tegra/hdmi.c | 63 +++-
1 file changed, 62 insertions(+), 1 deletion(-)
diff
Document new DVFS OPP table and voltage regulator properties of the
PWM controller.
Signed-off-by: Dmitry Osipenko
---
.../devicetree/bindings/pwm/nvidia,tegra20-pwm.txt | 13 +
1 file changed, 13 insertions(+)
diff --git
Now Internal and External memory controllers are memory interconnection
providers. This allows us to use interconnect API for tuning of memory
configuration. EMC driver now supports OPPs and DVFS. MC driver now
supports tuning of memory arbitration latency, which needs to be done
for ISO memory
Drivers that use tegra_sku_info and have COMPILE_TEST are failing to be
build due to the missing stub for tegra_sku_info, thus add the missing
stub.
Signed-off-by: Dmitry Osipenko
---
include/soc/tegra/fuse.h | 4
1 file changed, 4 insertions(+)
diff --git a/include/soc/tegra/fuse.h
Display controller (DC) performs isochronous memory transfers, and thus,
has a requirement for a minimum memory bandwidth that shall be fulfilled,
otherwise framebuffer data can't be fetched fast enough and this results
in a DC's data-FIFO underflow that follows by a visual corruption.
The Memory
Fix the size of Tegra20 EMC registers, which should be twice bigger.
Acked-by: Krzysztof Kozlowski
Signed-off-by: Dmitry Osipenko
---
arch/arm/boot/dts/tegra20.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/tegra20.dtsi
idr_init() uses base 0 which is an invalid identifier. The new function
idr_init_base allows IDR to set the ID lookup from base 1. This avoids
all lookups that otherwise starts from 0 since 0 is always unused.
References: commit 6ce711f27500 ("idr: Make 1-based IDRs more efficient")
Add voltage supplies to DVFS-capable devices in order to enable
system-wide voltage scaling.
Signed-off-by: Dmitry Osipenko
---
arch/arm/boot/dts/tegra30-cardhu-a04.dts | 44
1 file changed, 44 insertions(+)
diff --git a/arch/arm/boot/dts/tegra30-cardhu-a04.dts
On Wed, Nov 04, 2020 at 10:44:56AM -0800, John Hubbard wrote:
> On 11/4/20 10:17 AM, Jason Gunthorpe wrote:
> > On Wed, Nov 04, 2020 at 04:41:19PM +, Christoph Hellwig wrote:
> > > On Wed, Nov 04, 2020 at 04:37:58PM +, Christoph Hellwig wrote:
> > > > On Wed, Nov 04, 2020 at 05:26:58PM
Sync driver state using the Tegra SoC device state syncing API, telling
to regulators voltage coupler that EMC state is ready for DVFS. This is
required for enabling system-wide DVFS on Tegra20.
Tested-by: Nicolas Chauvet
Signed-off-by: Dmitry Osipenko
---
drivers/memory/tegra/tegra20-emc.c |
Now Internal and External Memory Controllers are memory interconnection
providers. This allows us to use interconnect API for tuning of memory
configuration. EMC driver now supports OPPs and DVFS.
Signed-off-by: Dmitry Osipenko
---
drivers/memory/tegra/Kconfig | 3 +-
Add interconnect properties to the Memory Controller, External Memory
Controller and the Display Controller nodes in order to describe hardware
interconnection.
Signed-off-by: Dmitry Osipenko
---
arch/arm/boot/dts/tegra20.dtsi | 26 +-
1 file changed, 25 insertions(+), 1
Add initial OPP and SoC core voltage scaling support to the video
decoder driver. This is required for enabling system-wide DVFS on
older Tegra SoCs.
Tested-by: Peter Geis
Tested-by: Nicolas Chauvet
Signed-off-by: Dmitry Osipenko
---
drivers/staging/media/tegra-vde/Kconfig | 1 +
Document new DVFS OPP table and voltage regulator properties of the
SDHCI controller.
Signed-off-by: Dmitry Osipenko
---
.../devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt | 12
1 file changed, 12 insertions(+)
diff --git
Add voltage supplies to DVFS-capable devices in order to enable
system-wide voltage scaling and allow CORE/RTC regulators to go lower.
Tested-by: Nicolas Chauvet
Signed-off-by: Dmitry Osipenko
---
arch/arm/boot/dts/tegra20-paz00.dts | 40 -
1 file changed, 33
Add interconnect properties to the Memory Controller, External Memory
Controller and the Display Controller nodes in order to describe hardware
interconnection.
Signed-off-by: Dmitry Osipenko
---
arch/arm/boot/dts/tegra124.dtsi | 25 +
1 file changed, 25 insertions(+)
Add option which allows regulator_check_consumers() to skip accounting of
a disabled consumer regulators.
This new option is needed for the NVIDIA Tegra voltage couplers in order
to properly calculate a lowest possible voltage for the CORE regulator.
The requirements of a disabled consumer
EMC driver will become mandatory after turning it into interconnect
provider because interconnect users, like display controller driver, will
fail to probe using newer device-trees that have interconnect properties.
Thus make EMC driver to probe even if timings are missing in device-tree.
Add missing PTC memory client latency allowness entry to the Tegra MC
drivers.
This prevents erroneous clearing of MC_INTSTATUS 0x0 register during
of the LA programming in tegra_mc_setup_latency_allowance() due to the
missing entry. Note that this patch doesn't fix any known problems.
Memory controller is interconnected with memory clients and with the
External Memory Controller. Document new interconnect property which
turns memory controller into interconnect provider.
Acked-by: Rob Herring
Signed-off-by: Dmitry Osipenko
---
Add voltage supplies to DVFS-capable devices in order to enable
system-wide voltage scaling and allow CORE/RTC regulators to go lower.
Signed-off-by: Dmitry Osipenko
---
arch/arm/boot/dts/tegra20-ventana.dts | 65 +++
1 file changed, 56 insertions(+), 9 deletions(-)
Downscale of the CORE voltage isn't allowed because some hardware units,
which are supplied by the CORE regulator, usually left ON at a boot time.
The new sync state API resolves this problem for us. All drivers of the
devices that are known to be ON at a boot time now should sync theirs
state.
Document new OPP table and voltage regulator properties which are needed
for supporting dynamic voltage-frequency scaling of the memory controller.
Some boards may have a fixed core voltage regulator, hence it's optional
because frequency scaling still may be desired.
Reviewed-by: Rob Herring
On Sun, Nov 01, 2020 at 11:50:39PM +0100, Daniel Vetter wrote:
> It's not device drivers, but everyone else. At least my understanding
> is that VM_IO | VM_PFNMAP means "even if it happens to be backed by a
> struct page, do not treat it like normal memory". And gup/pup_fast
> happily break that.
On Wed, Nov 04, 2020 at 04:41:19PM +, Christoph Hellwig wrote:
> On Wed, Nov 04, 2020 at 04:37:58PM +, Christoph Hellwig wrote:
> > On Wed, Nov 04, 2020 at 05:26:58PM +0100, Daniel Vetter wrote:
> > > What we're discussing is whether gup_fast and pup_fast also obey this,
> > > or fall over
Add EMC OPP DVFS table that will be used for dynamic scaling of memory
frequency/voltage. Update board device-trees with optional EMC core supply
and remove unsupported OPPs.
Signed-off-by: Dmitry Osipenko
---
.../boot/dts/tegra20-acer-a500-picasso.dts| 7 ++
idr_init() uses base 0 which is an invalid identifier. The new function
idr_init_base allows IDR to set the ID lookup from base 1. This avoids
all lookups that otherwise starts from 0 since 0 is always unused.
References: commit 6ce711f27500 ("idr: Make 1-based IDRs more efficient")
Add OPP and SoC core voltage scaling support to the display controller
driver. This is required for enabling system-wide DVFS on older Tegra
SoCs.
Tested-by: Peter Geis
Tested-by: Nicolas Chauvet
Signed-off-by: Dmitry Osipenko
---
drivers/gpu/drm/tegra/Kconfig | 1 +
Add modularization support to the Tegra30 EMC driver, which now can be
compiled as a loadable kernel module.
Signed-off-by: Dmitry Osipenko
---
drivers/memory/tegra/Kconfig | 2 +-
drivers/memory/tegra/mc.c | 3 +++
drivers/memory/tegra/tegra30-emc.c | 17 -
3
Add initial OPP and SoC core voltage scaling support to the Tegra EHCI
driver. This is required for enabling system-wide DVFS on older Tegra
SoCs.
Tested-by: Peter Geis
Tested-by: Nicolas Chauvet
Signed-off-by: Dmitry Osipenko
---
drivers/usb/host/Kconfig | 1 +
On Thu, Nov 05, 2020 at 10:56:53AM +0200, Pekka Paalanen wrote:
> On Wed, 04 Nov 2020 17:01:40 +
> Simon Ser wrote:
>
> > User-space doesn't need to keep track of blobs that might be in use by
> > the kernel. User-space can just destroy blobs as soon as they don't need
> > them anymore.
> >
On Wed, Nov 04, 2020 at 05:01:40PM +, Simon Ser wrote:
> User-space doesn't need to keep track of blobs that might be in use by
> the kernel. User-space can just destroy blobs as soon as they don't need
> them anymore.
>
> Signed-off-by: Simon Ser
> Signed-off-by: Daniel Stone
>
On Wed, Nov 04, 2020 at 04:53:38PM +0530, Deepak R Varma wrote:
> idr_init() uses base 0 which is an invalid identifier. The new function
> idr_init_base allows IDR to set the ID lookup from base 1. This avoids
> all lookups that otherwise starts from 0 since 0 is always unused.
>
> References:
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