Re: [PATCH] amd/display/dc:remove repeating expression
On 6/14/23 10:49 AM, Wang Ming wrote: Identify issues that arise by using the tests/doubletest.cocci semantic patch.Need to remove duplicate expression in if statement. Signed-off-by: Wang Ming Reviewed-by: Ammar Faizi -- Ammar Faizi
Re: [2/2] drm: Remove struct drm_driver.gem_prime_mmap
Hi
Am 14.06.23 um 04:06 schrieb Sui Jingfeng:
On 2023/6/14 01:27, Sui Jingfeng wrote:
Wow, so many drivers get nuked!
On 2023/6/13 22:51, Thomas Zimmermann wrote:
All drivers initialize this field with drm_gem_prime_mmap(). Call
the function directly and remove the field. Simplifies the code and
resolves a long-standing TODO item.
Signed-off-by: Thomas Zimmermann
Reviewed-by: Alex Deucher
I have tested this patch briefly with drm/amdgpu(RX560), Running
glmark2, the rendered scene looks OK.
But single driver is self-sharing. I think I should test this more
with multiple video card.
No need to test; it's equivalent to removing a wrapper.
Yes, only msm hardware might be affected.
But new DRM (un-upstreamed) drivers cannot be compiled anymore with this
patch applied.
This makes them all out-of-date or going to be outdated; this is
embarrassing!
What do you mean by embarrassing? Simply rebase your driver onto the
change and that's it. This happens regularly for out-of-tree drivers.
But if such a driver would land before this patchset, I'd have to update
the patchset instead.
Best regards
Thomas
---
Documentation/gpu/todo.rst | 9 -
drivers/accel/ivpu/ivpu_drv.c | 1 -
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 1 -
drivers/gpu/drm/drm_fbdev_dma.c | 6 +-
drivers/gpu/drm/drm_prime.c | 14 ++
drivers/gpu/drm/etnaviv/etnaviv_drv.c | 1 -
drivers/gpu/drm/exynos/exynos_drm_drv.c | 1 -
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c | 1 -
drivers/gpu/drm/lima/lima_drv.c | 1 -
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 1 -
drivers/gpu/drm/msm/msm_drv.c | 1 -
drivers/gpu/drm/msm/msm_drv.h | 1 -
drivers/gpu/drm/msm/msm_gem_prime.c | 5 -
drivers/gpu/drm/nouveau/nouveau_drm.c | 1 -
drivers/gpu/drm/panfrost/panfrost_drv.c | 1 -
drivers/gpu/drm/pl111/pl111_drv.c | 1 -
drivers/gpu/drm/radeon/radeon_drv.c | 1 -
drivers/gpu/drm/renesas/rcar-du/rcar_du_drv.c | 1 -
drivers/gpu/drm/rockchip/rockchip_drm_drv.c | 1 -
drivers/gpu/drm/v3d/v3d_drv.c | 1 -
drivers/gpu/drm/virtio/virtgpu_drv.c | 1 -
drivers/gpu/drm/xen/xen_drm_front.c | 1 -
include/drm/drm_drv.h | 14 --
include/drm/drm_gem_dma_helper.h | 6 ++
include/drm/drm_gem_shmem_helper.h | 1 -
include/drm/drm_gem_vram_helper.h | 1 -
26 files changed, 5 insertions(+), 69 deletions(-)
diff --git a/Documentation/gpu/todo.rst b/Documentation/gpu/todo.rst
index 68bdafa0284f5..ca1efad8c89c3 100644
--- a/Documentation/gpu/todo.rst
+++ b/Documentation/gpu/todo.rst
@@ -319,15 +319,6 @@ Contact: Daniel Vetter, Noralf Tronnes
Level: Advanced
-struct drm_gem_object_funcs
-
-GEM objects can now have a function table instead of having the
callbacks on the
-DRM driver struct. This is now the preferred way. Callbacks in
drivers have been
-converted, except for struct drm_driver.gem_prime_mmap.
-
-Level: Intermediate
-
connector register/unregister fixes
---
diff --git a/drivers/accel/ivpu/ivpu_drv.c
b/drivers/accel/ivpu/ivpu_drv.c
index 2df7643b843d5..9f2b9fdcc5498 100644
--- a/drivers/accel/ivpu/ivpu_drv.c
+++ b/drivers/accel/ivpu/ivpu_drv.c
@@ -376,7 +376,6 @@ static const struct drm_driver driver = {
.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
.gem_prime_import = ivpu_gem_prime_import,
- .gem_prime_mmap = drm_gem_prime_mmap,
.ioctls = ivpu_drm_ioctls,
.num_ioctls = ARRAY_SIZE(ivpu_drm_ioctls),
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index c9a41c997c6c7..7681f79f462eb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -2809,7 +2809,6 @@ static const struct drm_driver
amdgpu_kms_driver = {
.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
.gem_prime_import = amdgpu_gem_prime_import,
- .gem_prime_mmap = drm_gem_prime_mmap,
.name = DRIVER_NAME,
.desc = DRIVER_DESC,
diff --git a/drivers/gpu/drm/drm_fbdev_dma.c
b/drivers/gpu/drm/drm_fbdev_dma.c
index d86773fa8ab00..8217f1ddc0075 100644
--- a/drivers/gpu/drm/drm_fbdev_dma.c
+++ b/drivers/gpu/drm/drm_fbdev_dma.c
@@ -54,12 +54,8 @@ static void drm_fbdev_dma_fb_destroy(struct
fb_info *info)
static int drm_fbdev_dma_fb_mmap(struct fb_info *info, struct
vm_area_struct *vma)
{
struct drm_fb_helper *fb_helper = info->par;
- struct drm_device *dev = fb_helper->dev;
-
- if (drm_WARN_ON_ONCE(dev,
Re: [PATCH] drm/fbdev-generic: Remove a redundant assignment clause
Hi
Am 14.06.23 um 03:30 schrieb Sui Jingfeng:
The assignment "dst = map;" in the drm_fbdev_generic_damage_blit() function
is redundant because it has already been copied when the call to
drm_client_buffer_vmap() is finished. Therefore, this patch saves a useless
copy. No functional change.
Isn't that what we discussed here?
https://lore.kernel.org/dri-devel/20230325074636.136833-1-15330273...@189.cn/
Best regards
Thomas
Signed-off-by: Sui Jingfeng
---
drivers/gpu/drm/drm_fbdev_generic.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/drm_fbdev_generic.c
b/drivers/gpu/drm/drm_fbdev_generic.c
index 98ae703848a0..aa6924e3a58c 100644
--- a/drivers/gpu/drm/drm_fbdev_generic.c
+++ b/drivers/gpu/drm/drm_fbdev_generic.c
@@ -182,7 +182,7 @@ static int drm_fbdev_generic_damage_blit(struct
drm_fb_helper *fb_helper,
struct drm_clip_rect *clip)
{
struct drm_client_buffer *buffer = fb_helper->buffer;
- struct iosys_map map, dst;
+ struct iosys_map map;
int ret;
/*
@@ -202,8 +202,7 @@ static int drm_fbdev_generic_damage_blit(struct
drm_fb_helper *fb_helper,
if (ret)
goto out;
- dst = map;
- drm_fbdev_generic_damage_blit_real(fb_helper, clip, );
+ drm_fbdev_generic_damage_blit_real(fb_helper, clip, );
drm_client_buffer_vunmap(buffer);
--
Thomas Zimmermann
Graphics Driver Developer
SUSE Software Solutions Germany GmbH
Frankenstrasse 146, 90461 Nuernberg, Germany
GF: Ivo Totev, Andrew Myers, Andrew McDonald, Boudien Moerman
HRB 36809 (AG Nuernberg)
OpenPGP_signature
Description: OpenPGP digital signature
Re: [PATCH v4 5/8] drm/mediatek: hdmi: add v2 support
Re: [PATCH] udmabuf: revert 'Add support for mapping hugepages (v4)'
On Tue, 13 Jun 2023, David Hildenbrand wrote: > On 13.06.23 10:26, Kasireddy, Vivek wrote: > >> On 12.06.23 09:10, Kasireddy, Vivek wrote: > >>> Sorry for the late reply; I just got back from vacation. > >>> If it is unsafe to directly use the subpages of a hugetlb page, then > >>> reverting > >>> this patch seems like the only option for addressing this issue > >>> immediately. > >>> So, this patch is > >>> Acked-by: Vivek Kasireddy > >>> > >>> As far as the use-case is concerned, there are two main users of the > >> udmabuf > >>> driver: Qemu and CrosVM VMMs. However, it appears Qemu is the only > >> one > >>> that uses hugetlb pages (when hugetlb=on is set) as the backing store for > >>> Guest (Linux, Android and Windows) system memory. The main goal is to > >>> share the pages associated with the Guest allocated framebuffer (FB) with > >>> the Host GPU driver and other components in a zero-copy way. To that > >> end, > >>> the guest GPU driver (virtio-gpu) allocates 4k size pages (associated with > >>> the FB) and pins them before sharing the (guest) physical (or dma) > >> addresses > >>> (and lengths) with Qemu. Qemu then translates the addresses into file > >>> offsets and shares these offsets with udmabuf. > >> > >> Is my understanding correct, that we can effectively long-term pin > >> (worse than mlock) 64 MiB per UDMABUF_CREATE, allowing eventually !root > > The 64 MiB limit is the theoretical upper bound that we have not seen hit in > > practice. Typically, for a 1920x1080 resolution (commonly used in Guests), > > the size of the FB is ~8 MB (1920x1080x4). And, most modern Graphics > > compositors flip between two FBs. > > > > Okay, but users with privileges to open that file can just create as many as > they want? I think I'll have to play with it. > > >> users > >> > >> ll /dev/udmabuf > >> crw-rw 1 root kvm 10, 125 12. Jun 08:12 /dev/udmabuf > >> > >> to bypass there effective MEMLOCK limit, fragmenting physical memory and > >> breaking swap? > > Right, it does not look like the mlock limits are honored. > > > > That should be added. Agreed. > > >> > >> Regarding the udmabuf_vm_fault(), I assume we're mapping pages we > >> obtained from the memfd ourselves into a special VMA (mmap() of the > > mmap operation is really needed only if any component on the Host needs > > CPU access to the buffer. But in most scenarios, we try to ensure direct GPU > > access (h/w acceleration via gl) to these pages. > > > >> udmabuf). I'm not sure how well shmem pages are prepared for getting > >> mapped by someone else into an arbitrary VMA (page->index?). > > Most drm/gpu drivers use shmem pages as the backing store for FBs and > > other buffers and also provide mmap capability. What concerns do you see > > with this approach? > > Are these mmaping the pages the way udmabuf maps these pages (IOW, on-demand > fault where we core-mm will adjust the mapcount etc)? > > Skimming over at shmem_read_mapping_page() users, I assume most of them use a > VM_PFNMAP mapping (or don't mmap them at all), where we won't be messing with > the struct page at all. > > (That might even allow you to mmap hugetlb sub-pages, because the struct page > -- and mapcount -- will be ignored completely and not touched.) You're well ahead of me: I didn't reach an understanding of whether or not mapcount would get manipulated here - though if Junxiao's original patch did fix the immediate hugetlb symptoms, presumably it is (and without much point, since udmabuf holds on to that extra reference which pins each page for the duration). > > > > >> > >> ... also, just imagine someone doing FALLOC_FL_PUNCH_HOLE / ftruncate() > >> on the memfd. What's mapped into the memfd no longer corresponds to > >> what's pinned / mapped into the VMA. > > IIUC, making use of the DMA_BUF_IOCTL_SYNC ioctl would help with any > > coherency issues: > > https://www.kernel.org/doc/html/v6.2/driver-api/dma-buf.html#c.dma_buf_sync > > > > Would it as of now? udmabuf_create() pulls the shmem pages out of the memfd, > not sure how DMA_BUF_IOCTL_SYNC would help to update that whenever the pages > inside the memfd would change (e.g., FALLOC_FL_PUNCH_HOLE + realloc). > > But that's most probably simply "not supported". Yes, the pages which udmabuf is holding would be the originals: they will then be detached from the hole-punched file, and subsequent faults or writes to that backing file (through shmem, rather than through udmabuf) can fill in the holes with new, different pages. So long as that's well understood, then it's not necessarily a disaster. I see udmabuf asks for SEAL_SHRINK (I guess to keep away from SIGBUS), but refuses SEAL_WRITE - so hole-punching remains permitted. > > >> > >> > >> Was linux-mm (and especially shmem maintainers, ccing Hugh) involved in > >> the upstreaming of udmabuf? Thanks for the Cc, David. No, I wasn't involved at all; but I probably would not have understood their needs much better then than now. I don't
[PATCH v9 6/9] drm/etnaviv: Add driver support for the PCI devices
From: Sui Jingfeng
This patch adds PCI driver support on top of what we already have. Take
the GC1000 in LS7A1000/LS2K1000 as the first instance of the PCI device
driver. There is only one GPU core for the GC1000 in the LS7A1000 and
LS2K1000. Therefore, component frameworks can be avoided.
Cc: Lucas Stach
Cc: Christian Gmeiner
Cc: Philipp Zabel
Cc: Bjorn Helgaas
Cc: Daniel Vetter
Signed-off-by: Sui Jingfeng
---
drivers/gpu/drm/etnaviv/Kconfig | 10 +++
drivers/gpu/drm/etnaviv/Makefile | 2 +
drivers/gpu/drm/etnaviv/etnaviv_drv.c | 13 +++-
drivers/gpu/drm/etnaviv/etnaviv_drv.h | 3 +
drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 8 +--
drivers/gpu/drm/etnaviv/etnaviv_gpu.h | 6 ++
drivers/gpu/drm/etnaviv/etnaviv_pci_drv.c | 75 +++
drivers/gpu/drm/etnaviv/etnaviv_pci_drv.h | 18 ++
8 files changed, 128 insertions(+), 7 deletions(-)
create mode 100644 drivers/gpu/drm/etnaviv/etnaviv_pci_drv.c
create mode 100644 drivers/gpu/drm/etnaviv/etnaviv_pci_drv.h
diff --git a/drivers/gpu/drm/etnaviv/Kconfig b/drivers/gpu/drm/etnaviv/Kconfig
index faa7fc68b009..1b5b162efb61 100644
--- a/drivers/gpu/drm/etnaviv/Kconfig
+++ b/drivers/gpu/drm/etnaviv/Kconfig
@@ -15,6 +15,16 @@ config DRM_ETNAVIV
help
DRM driver for Vivante GPUs.
+config DRM_ETNAVIV_PCI_DRIVER
+ bool "enable ETNAVIV PCI driver support"
+ depends on DRM_ETNAVIV
+ depends on PCI
+ default y
+ help
+ Compile in support for PCI GPUs of Vivante.
+ For example, the GC1000 in LS7A1000 and LS2K1000.
+ Say Y if you have such a hardware.
+
config DRM_ETNAVIV_THERMAL
bool "enable ETNAVIV thermal throttling"
depends on DRM_ETNAVIV
diff --git a/drivers/gpu/drm/etnaviv/Makefile b/drivers/gpu/drm/etnaviv/Makefile
index 46e5ffad69a6..6829e1ebf2db 100644
--- a/drivers/gpu/drm/etnaviv/Makefile
+++ b/drivers/gpu/drm/etnaviv/Makefile
@@ -16,4 +16,6 @@ etnaviv-y := \
etnaviv_perfmon.o \
etnaviv_sched.o
+etnaviv-$(CONFIG_DRM_ETNAVIV_PCI_DRIVER) += etnaviv_pci_drv.o
+
obj-$(CONFIG_DRM_ETNAVIV) += etnaviv.o
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_drv.c
b/drivers/gpu/drm/etnaviv/etnaviv_drv.c
index 93ca240cd4c0..0a365e96d371 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_drv.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_drv.c
@@ -21,6 +21,7 @@
#include "etnaviv_gpu.h"
#include "etnaviv_gem.h"
#include "etnaviv_mmu.h"
+#include "etnaviv_pci_drv.h"
#include "etnaviv_perfmon.h"
/*
@@ -538,7 +539,7 @@ static const struct drm_driver etnaviv_drm_driver = {
static struct etnaviv_drm_private *etna_private_ptr;
-static int etnaviv_drm_bind(struct device *dev, bool component)
+int etnaviv_drm_bind(struct device *dev, bool component)
{
struct etnaviv_drm_private *priv;
struct drm_device *drm;
@@ -588,7 +589,7 @@ static int etnaviv_drm_bind(struct device *dev, bool
component)
return ret;
}
-static void etnaviv_drm_unbind(struct device *dev, bool component)
+void etnaviv_drm_unbind(struct device *dev, bool component)
{
struct etnaviv_drm_private *priv = etna_private_ptr;
struct drm_device *drm = priv->drm;
@@ -746,6 +747,10 @@ static int __init etnaviv_init(void)
if (ret != 0)
goto unregister_gpu_driver;
+ ret = etnaviv_register_pci_driver();
+ if (ret != 0)
+ goto unregister_platform_driver;
+
/*
* If the DT contains at least one available GPU device, instantiate
* the DRM platform device.
@@ -763,7 +768,7 @@ static int __init etnaviv_init(void)
break;
}
- return 0;
+ return ret;
unregister_platform_driver:
platform_driver_unregister(_platform_driver);
@@ -778,6 +783,8 @@ static void __exit etnaviv_exit(void)
etnaviv_destroy_platform_device(_platform_device);
platform_driver_unregister(_platform_driver);
platform_driver_unregister(_gpu_driver);
+
+ etnaviv_unregister_pci_driver();
}
module_exit(etnaviv_exit);
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_drv.h
b/drivers/gpu/drm/etnaviv/etnaviv_drv.h
index e58f82e698de..9cd72948cfad 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_drv.h
+++ b/drivers/gpu/drm/etnaviv/etnaviv_drv.h
@@ -83,6 +83,9 @@ bool etnaviv_cmd_validate_one(struct etnaviv_gpu *gpu,
u32 *stream, unsigned int size,
struct drm_etnaviv_gem_submit_reloc *relocs, unsigned int reloc_size);
+int etnaviv_drm_bind(struct device *dev, bool component);
+void etnaviv_drm_unbind(struct device *dev, bool component);
+
#ifdef CONFIG_DEBUG_FS
void etnaviv_gem_describe_objects(struct etnaviv_drm_private *priv,
struct seq_file *m);
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
index 059be8c89c5a..d6a21e97feb1 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
@@ -1866,8 +1866,8 @@
[PATCH v9 9/9] drm/etnaviv: Clean up etnaviv_pdev_probe() function
From: Sui Jingfeng
Add a dedicate function to do the DMA configuration to the virtual master.
Also replace the >dev with dev.
Signed-off-by: Sui Jingfeng
---
drivers/gpu/drm/etnaviv/etnaviv_drv.c | 65 +++
1 file changed, 36 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_drv.c
b/drivers/gpu/drm/etnaviv/etnaviv_drv.c
index 0ee7f641cee3..df4c21a17d9d 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_drv.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_drv.c
@@ -54,6 +54,40 @@ static bool etnaviv_is_dma_coherent(struct device *dev)
return coherent;
}
+static int etnaviv_of_dma_configure(struct device *dev)
+{
+ struct device_node *first_node;
+
+ /*
+* PTA and MTLB can have 40 bit base addresses, but
+* unfortunately, an entry in the MTLB can only point to a
+* 32 bit base address of a STLB. Moreover, to initialize the
+* MMU we need a command buffer with a 32 bit address because
+* without an MMU there is only an indentity mapping between
+* the internal 32 bit addresses and the bus addresses.
+*
+* To make things easy, we set the dma_coherent_mask to 32
+* bit to make sure we are allocating the command buffers and
+* TLBs in the lower 4 GiB address space.
+*/
+ if (dma_set_mask(dev, DMA_BIT_MASK(40)) ||
+ dma_set_coherent_mask(dev, DMA_BIT_MASK(32))) {
+ dev_err(dev, "No suitable DMA available\n");
+ return -ENODEV;
+ }
+
+ /*
+* Apply the same DMA configuration to the virtual etnaviv
+* device as the GPU we found. This assumes that all Vivante
+* GPUs in the system share the same DMA constraints.
+*/
+ first_node = etnaviv_of_first_available_node();
+ if (first_node)
+ of_dma_configure(dev, first_node, true);
+
+ return 0;
+}
+
/*
* etnaviv private data construction and destructions:
*/
@@ -663,7 +697,6 @@ static const struct component_master_ops etnaviv_master_ops
= {
static int etnaviv_pdev_probe(struct platform_device *pdev)
{
struct device *dev = >dev;
- struct device_node *first_node = NULL;
struct component_match *match = NULL;
if (!dev->platform_data) {
@@ -673,10 +706,7 @@ static int etnaviv_pdev_probe(struct platform_device *pdev)
if (!of_device_is_available(core_node))
continue;
- if (!first_node)
- first_node = core_node;
-
- drm_of_component_match_add(>dev, ,
+ drm_of_component_match_add(dev, ,
component_compare_of,
core_node);
}
} else {
@@ -687,31 +717,8 @@ static int etnaviv_pdev_probe(struct platform_device *pdev)
component_match_add(dev, ,
component_compare_dev_name, names[i]);
}
- /*
-* PTA and MTLB can have 40 bit base addresses, but
-* unfortunately, an entry in the MTLB can only point to a
-* 32 bit base address of a STLB. Moreover, to initialize the
-* MMU we need a command buffer with a 32 bit address because
-* without an MMU there is only an indentity mapping between
-* the internal 32 bit addresses and the bus addresses.
-*
-* To make things easy, we set the dma_coherent_mask to 32
-* bit to make sure we are allocating the command buffers and
-* TLBs in the lower 4 GiB address space.
-*/
- if (dma_set_mask(>dev, DMA_BIT_MASK(40)) ||
- dma_set_coherent_mask(>dev, DMA_BIT_MASK(32))) {
- dev_dbg(>dev, "No suitable DMA available\n");
+ if (etnaviv_of_dma_configure(dev))
return -ENODEV;
- }
-
- /*
-* Apply the same DMA configuration to the virtual etnaviv
-* device as the GPU we found. This assumes that all Vivante
-* GPUs in the system share the same DMA constraints.
-*/
- if (first_node)
- of_dma_configure(>dev, first_node, true);
return component_master_add_with_match(dev, _master_ops, match);
}
--
2.25.1
[PATCH v9 5/9] drm/etnaviv: Allow bypass component framework
From: Sui Jingfeng
Adding additional code path to allow bypass component frameworks, A
platform with a single GPU core could probably try the non-component
code path. This patch is for code sharing, no functional change.
Cc: Lucas Stach
Cc: Christian Gmeiner
Cc: Philipp Zabel
Cc: Bjorn Helgaas
Cc: Daniel Vetter
Signed-off-by: Sui Jingfeng
---
drivers/gpu/drm/etnaviv/etnaviv_drv.c | 47 ++-
drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 83 +--
drivers/gpu/drm/etnaviv/etnaviv_gpu.h | 3 +
3 files changed, 91 insertions(+), 42 deletions(-)
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_drv.c
b/drivers/gpu/drm/etnaviv/etnaviv_drv.c
index 6a048be02857..93ca240cd4c0 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_drv.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_drv.c
@@ -536,10 +536,9 @@ static const struct drm_driver etnaviv_drm_driver = {
.minor = 3,
};
-/*
- * Platform driver:
- */
-static int etnaviv_bind(struct device *dev)
+static struct etnaviv_drm_private *etna_private_ptr;
+
+static int etnaviv_drm_bind(struct device *dev, bool component)
{
struct etnaviv_drm_private *priv;
struct drm_device *drm;
@@ -556,12 +555,15 @@ static int etnaviv_bind(struct device *dev)
}
drm->dev_private = priv;
+ etna_private_ptr = priv;
dma_set_max_seg_size(dev, SZ_2G);
- dev_set_drvdata(dev, drm);
+ if (component)
+ ret = component_bind_all(dev, drm);
+ else
+ ret = etnaviv_gpu_bind(dev, NULL, drm);
- ret = component_bind_all(dev, drm);
if (ret < 0)
goto out_free_priv;
@@ -574,7 +576,10 @@ static int etnaviv_bind(struct device *dev)
return 0;
out_unbind:
- component_unbind_all(dev, drm);
+ if (component)
+ component_unbind_all(dev, drm);
+ else
+ etnaviv_gpu_unbind(dev, NULL, drm);
out_free_priv:
etnaviv_free_private(priv);
out_put:
@@ -583,14 +588,17 @@ static int etnaviv_bind(struct device *dev)
return ret;
}
-static void etnaviv_unbind(struct device *dev)
+static void etnaviv_drm_unbind(struct device *dev, bool component)
{
- struct drm_device *drm = dev_get_drvdata(dev);
- struct etnaviv_drm_private *priv = drm->dev_private;
+ struct etnaviv_drm_private *priv = etna_private_ptr;
+ struct drm_device *drm = priv->drm;
drm_dev_unregister(drm);
- component_unbind_all(dev, drm);
+ if (component)
+ component_unbind_all(dev, drm);
+ else
+ etnaviv_gpu_unbind(dev, NULL, drm);
etnaviv_free_private(priv);
@@ -599,9 +607,22 @@ static void etnaviv_unbind(struct device *dev)
drm_dev_put(drm);
}
+/*
+ * Platform driver:
+ */
+static int etnaviv_master_bind(struct device *dev)
+{
+ return etnaviv_drm_bind(dev, true);
+}
+
+static void etnaviv_master_unbind(struct device *dev)
+{
+ return etnaviv_drm_unbind(dev, true);
+}
+
static const struct component_master_ops etnaviv_master_ops = {
- .bind = etnaviv_bind,
- .unbind = etnaviv_unbind,
+ .bind = etnaviv_master_bind,
+ .unbind = etnaviv_master_unbind,
};
static int etnaviv_pdev_probe(struct platform_device *pdev)
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
index 5e88fa95dac2..059be8c89c5a 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
@@ -1737,8 +1737,7 @@ static const struct thermal_cooling_device_ops
cooling_ops = {
.set_cur_state = etnaviv_gpu_cooling_set_cur_state,
};
-static int etnaviv_gpu_bind(struct device *dev, struct device *master,
- void *data)
+int etnaviv_gpu_bind(struct device *dev, struct device *master, void *data)
{
struct drm_device *drm = data;
struct etnaviv_drm_private *priv = drm->dev_private;
@@ -1769,7 +1768,6 @@ static int etnaviv_gpu_bind(struct device *dev, struct
device *master,
if (ret < 0)
goto out_sched;
-
gpu->drm = drm;
gpu->fence_context = dma_fence_context_alloc(1);
xa_init_flags(>user_fences, XA_FLAGS_ALLOC);
@@ -1798,8 +1796,7 @@ static int etnaviv_gpu_bind(struct device *dev, struct
device *master,
return ret;
}
-static void etnaviv_gpu_unbind(struct device *dev, struct device *master,
- void *data)
+void etnaviv_gpu_unbind(struct device *dev, struct device *master, void *data)
{
struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
@@ -1867,9 +1864,11 @@ static int etnaviv_gpu_register_irq(struct etnaviv_gpu
*gpu, int irq)
return 0;
}
-static int etnaviv_gpu_platform_probe(struct platform_device *pdev)
+/* platform independent */
+
+static int etnaviv_gpu_driver_create(struct device *dev, void __iomem *mmio,
+int irq, bool component, bool has_clk)
{
- struct device *dev = >dev;
[PATCH v9 8/9] drm/etnaviv: Add a dedicated function to create the virtual master
From: Sui Jingfeng
After introducing the etnaviv_of_first_available_node() helper, the
creation of the virtual master platform device can also be simplified.
So, switch to etnaviv_create_virtual_master() function.
Cc: Lucas Stach
Cc: Christian Gmeiner
Cc: Philipp Zabel
Cc: Bjorn Helgaas
Cc: Daniel Vetter
Signed-off-by: Sui Jingfeng
---
drivers/gpu/drm/etnaviv/etnaviv_drv.c | 43 ---
1 file changed, 26 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_drv.c
b/drivers/gpu/drm/etnaviv/etnaviv_drv.c
index 1c9386e5a1b0..0ee7f641cee3 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_drv.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_drv.c
@@ -766,10 +766,32 @@ static void etnaviv_destroy_platform_device(struct
platform_device **ppdev)
*ppdev = NULL;
}
+static int etnaviv_create_virtual_master(void)
+{
+ struct platform_device **master = _platform_device;
+ struct device_node *np;
+
+ /*
+* If the DT contains at least one available GPU device, instantiate
+* the DRM platform device.
+*/
+ np = etnaviv_of_first_available_node();
+ if (np) {
+ int ret;
+
+ of_node_put(np);
+
+ ret = etnaviv_create_platform_device("etnaviv", master);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
static int __init etnaviv_init(void)
{
int ret;
- struct device_node *np;
etnaviv_validate_init();
@@ -785,22 +807,9 @@ static int __init etnaviv_init(void)
if (ret != 0)
goto unregister_platform_driver;
- /*
-* If the DT contains at least one available GPU device, instantiate
-* the DRM platform device.
-*/
- for_each_compatible_node(np, NULL, "vivante,gc") {
- if (!of_device_is_available(np))
- continue;
- of_node_put(np);
-
- ret = etnaviv_create_platform_device("etnaviv",
-_platform_device);
- if (ret)
- goto unregister_platform_driver;
-
- break;
- }
+ ret = etnaviv_create_virtual_master();
+ if (ret)
+ goto unregister_platform_driver;
return ret;
--
2.25.1
[PATCH v9 3/9] drm/etnaviv: Add dedicated functions to create and destroy platform device
From: Sui Jingfeng
Also rename the virtual master platform device as etnaviv_platform_device,
for better reflection that it is a platform device, not a DRM device.
Another benefit is that we no longer need to call of_node_put() for three
different cases, Instead, we only need to call it once.
Cc: Lucas Stach
Cc: Christian Gmeiner
Cc: Philipp Zabel
Cc: Bjorn Helgaas
Cc: Daniel Vetter
Signed-off-by: Sui Jingfeng
---
drivers/gpu/drm/etnaviv/etnaviv_drv.c | 56 +++
1 file changed, 39 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_drv.c
b/drivers/gpu/drm/etnaviv/etnaviv_drv.c
index 31a7f59ccb49..cec005035d0e 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_drv.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_drv.c
@@ -656,12 +656,44 @@ static struct platform_driver etnaviv_platform_driver = {
},
};
-static struct platform_device *etnaviv_drm;
+static struct platform_device *etnaviv_platform_device;
-static int __init etnaviv_init(void)
+static int etnaviv_create_platform_device(const char *name,
+ struct platform_device **ppdev)
{
struct platform_device *pdev;
int ret;
+
+ pdev = platform_device_alloc(name, PLATFORM_DEVID_NONE);
+ if (!pdev)
+ return -ENOMEM;
+
+ ret = platform_device_add(pdev);
+ if (ret) {
+ platform_device_put(pdev);
+ return ret;
+ }
+
+ *ppdev = pdev;
+
+ return 0;
+}
+
+static void etnaviv_destroy_platform_device(struct platform_device **ppdev)
+{
+ struct platform_device *pdev = *ppdev;
+
+ if (!pdev)
+ return;
+
+ platform_device_unregister(pdev);
+
+ *ppdev = NULL;
+}
+
+static int __init etnaviv_init(void)
+{
+ int ret;
struct device_node *np;
etnaviv_validate_init();
@@ -681,23 +713,13 @@ static int __init etnaviv_init(void)
for_each_compatible_node(np, NULL, "vivante,gc") {
if (!of_device_is_available(np))
continue;
+ of_node_put(np);
- pdev = platform_device_alloc("etnaviv", PLATFORM_DEVID_NONE);
- if (!pdev) {
- ret = -ENOMEM;
- of_node_put(np);
- goto unregister_platform_driver;
- }
-
- ret = platform_device_add(pdev);
- if (ret) {
- platform_device_put(pdev);
- of_node_put(np);
+ ret = etnaviv_create_platform_device("etnaviv",
+_platform_device);
+ if (ret)
goto unregister_platform_driver;
- }
- etnaviv_drm = pdev;
- of_node_put(np);
break;
}
@@ -713,7 +735,7 @@ module_init(etnaviv_init);
static void __exit etnaviv_exit(void)
{
- platform_device_unregister(etnaviv_drm);
+ etnaviv_destroy_platform_device(_platform_device);
platform_driver_unregister(_platform_driver);
platform_driver_unregister(_gpu_driver);
}
--
2.25.1
[PATCH v9 4/9] drm/etnaviv: Add helpers for private data construction and destruction
From: Sui Jingfeng
struct etnaviv_drm_private contains a lot of common resources that are
shared by all GPUs. This patch introduces two dedicated functions, which
is for the construction and destruction of instances of this structure.
The idea is to avoid leaking its members outside. The error handling code
can also be simplified.
Cc: Lucas Stach
Cc: Christian Gmeiner
Cc: Philipp Zabel
Cc: Bjorn Helgaas
Cc: Daniel Vetter
Signed-off-by: Sui Jingfeng
---
drivers/gpu/drm/etnaviv/etnaviv_drv.c | 73 +--
drivers/gpu/drm/etnaviv/etnaviv_drv.h | 1 +
2 files changed, 47 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_drv.c
b/drivers/gpu/drm/etnaviv/etnaviv_drv.c
index cec005035d0e..6a048be02857 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_drv.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_drv.c
@@ -24,9 +24,47 @@
#include "etnaviv_perfmon.h"
/*
- * DRM operations:
+ * etnaviv private data construction and destructions:
*/
+static struct etnaviv_drm_private *
+etnaviv_alloc_private(struct device *dev, struct drm_device *drm)
+{
+ struct etnaviv_drm_private *priv;
+
+ priv = kzalloc(sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return ERR_PTR(-ENOMEM);
+
+ priv->drm = drm;
+
+ xa_init_flags(>active_contexts, XA_FLAGS_ALLOC);
+
+ mutex_init(>gem_lock);
+ INIT_LIST_HEAD(>gem_list);
+ priv->num_gpus = 0;
+ priv->shm_gfp_mask = GFP_HIGHUSER | __GFP_RETRY_MAYFAIL | __GFP_NOWARN;
+ priv->cmdbuf_suballoc = etnaviv_cmdbuf_suballoc_new(dev);
+ if (IS_ERR(priv->cmdbuf_suballoc)) {
+ kfree(priv);
+ dev_err(dev, "Failed to create cmdbuf suballocator\n");
+ return ERR_PTR(-ENOMEM);
+ }
+
+ return priv;
+}
+
+static void etnaviv_free_private(struct etnaviv_drm_private *priv)
+{
+ if (!priv)
+ return;
+
+ etnaviv_cmdbuf_suballoc_destroy(priv->cmdbuf_suballoc);
+
+ xa_destroy(>active_contexts);
+
+ kfree(priv);
+}
static void load_gpu(struct drm_device *dev)
{
@@ -511,35 +549,21 @@ static int etnaviv_bind(struct device *dev)
if (IS_ERR(drm))
return PTR_ERR(drm);
- priv = kzalloc(sizeof(*priv), GFP_KERNEL);
- if (!priv) {
- dev_err(dev, "failed to allocate private data\n");
- ret = -ENOMEM;
+ priv = etnaviv_alloc_private(dev, drm);
+ if (IS_ERR(priv)) {
+ ret = PTR_ERR(priv);
goto out_put;
}
+
drm->dev_private = priv;
dma_set_max_seg_size(dev, SZ_2G);
- xa_init_flags(>active_contexts, XA_FLAGS_ALLOC);
-
- mutex_init(>gem_lock);
- INIT_LIST_HEAD(>gem_list);
- priv->num_gpus = 0;
- priv->shm_gfp_mask = GFP_HIGHUSER | __GFP_RETRY_MAYFAIL | __GFP_NOWARN;
-
- priv->cmdbuf_suballoc = etnaviv_cmdbuf_suballoc_new(drm->dev);
- if (IS_ERR(priv->cmdbuf_suballoc)) {
- dev_err(drm->dev, "Failed to create cmdbuf suballocator\n");
- ret = PTR_ERR(priv->cmdbuf_suballoc);
- goto out_free_priv;
- }
-
dev_set_drvdata(dev, drm);
ret = component_bind_all(dev, drm);
if (ret < 0)
- goto out_destroy_suballoc;
+ goto out_free_priv;
load_gpu(drm);
@@ -551,10 +575,8 @@ static int etnaviv_bind(struct device *dev)
out_unbind:
component_unbind_all(dev, drm);
-out_destroy_suballoc:
- etnaviv_cmdbuf_suballoc_destroy(priv->cmdbuf_suballoc);
out_free_priv:
- kfree(priv);
+ etnaviv_free_private(priv);
out_put:
drm_dev_put(drm);
@@ -570,12 +592,9 @@ static void etnaviv_unbind(struct device *dev)
component_unbind_all(dev, drm);
- etnaviv_cmdbuf_suballoc_destroy(priv->cmdbuf_suballoc);
-
- xa_destroy(>active_contexts);
+ etnaviv_free_private(priv);
drm->dev_private = NULL;
- kfree(priv);
drm_dev_put(drm);
}
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_drv.h
b/drivers/gpu/drm/etnaviv/etnaviv_drv.h
index b3eb1662e90c..e58f82e698de 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_drv.h
+++ b/drivers/gpu/drm/etnaviv/etnaviv_drv.h
@@ -35,6 +35,7 @@ struct etnaviv_file_private {
};
struct etnaviv_drm_private {
+ struct drm_device *drm;
int num_gpus;
struct etnaviv_gpu *gpu[ETNA_MAX_PIPES];
gfp_t shm_gfp_mask;
--
2.25.1
[PATCH v9 2/9] drm/etnaviv: Add a dedicated function to get various clocks
From: Sui Jingfeng
Because it is also platform-dependent, there are environments where don't
have CLK subsystem support, for example, discreted PCI GPUs. So don't rage
quit if there is no CLK subsystem support.
For the GPU in LS7A1000 and LS2K1000, the working frequency of the GPU is
tuned by configuring the PLL registers.
Cc: Lucas Stach
Cc: Christian Gmeiner
Cc: Philipp Zabel
Cc: Bjorn Helgaas
Cc: Daniel Vetter
Signed-off-by: Sui Jingfeng
---
drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 53 ---
1 file changed, 32 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
index a03e81337d8f..5e88fa95dac2 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
@@ -1565,6 +1565,35 @@ static irqreturn_t irq_handler(int irq, void *data)
return ret;
}
+static int etnaviv_gpu_clk_get(struct etnaviv_gpu *gpu)
+{
+ struct device *dev = gpu->dev;
+
+ gpu->clk_reg = devm_clk_get_optional(dev, "reg");
+ DBG("clk_reg: %p", gpu->clk_reg);
+ if (IS_ERR(gpu->clk_reg))
+ return PTR_ERR(gpu->clk_reg);
+
+ gpu->clk_bus = devm_clk_get_optional(dev, "bus");
+ DBG("clk_bus: %p", gpu->clk_bus);
+ if (IS_ERR(gpu->clk_bus))
+ return PTR_ERR(gpu->clk_bus);
+
+ gpu->clk_core = devm_clk_get(dev, "core");
+ DBG("clk_core: %p", gpu->clk_core);
+ if (IS_ERR(gpu->clk_core))
+ return PTR_ERR(gpu->clk_core);
+ gpu->base_rate_core = clk_get_rate(gpu->clk_core);
+
+ gpu->clk_shader = devm_clk_get_optional(dev, "shader");
+ DBG("clk_shader: %p", gpu->clk_shader);
+ if (IS_ERR(gpu->clk_shader))
+ return PTR_ERR(gpu->clk_shader);
+ gpu->base_rate_shader = clk_get_rate(gpu->clk_shader);
+
+ return 0;
+}
+
static int etnaviv_gpu_clk_enable(struct etnaviv_gpu *gpu)
{
int ret;
@@ -1863,27 +1892,9 @@ static int etnaviv_gpu_platform_probe(struct
platform_device *pdev)
return err;
/* Get Clocks: */
- gpu->clk_reg = devm_clk_get_optional(>dev, "reg");
- DBG("clk_reg: %p", gpu->clk_reg);
- if (IS_ERR(gpu->clk_reg))
- return PTR_ERR(gpu->clk_reg);
-
- gpu->clk_bus = devm_clk_get_optional(>dev, "bus");
- DBG("clk_bus: %p", gpu->clk_bus);
- if (IS_ERR(gpu->clk_bus))
- return PTR_ERR(gpu->clk_bus);
-
- gpu->clk_core = devm_clk_get(>dev, "core");
- DBG("clk_core: %p", gpu->clk_core);
- if (IS_ERR(gpu->clk_core))
- return PTR_ERR(gpu->clk_core);
- gpu->base_rate_core = clk_get_rate(gpu->clk_core);
-
- gpu->clk_shader = devm_clk_get_optional(>dev, "shader");
- DBG("clk_shader: %p", gpu->clk_shader);
- if (IS_ERR(gpu->clk_shader))
- return PTR_ERR(gpu->clk_shader);
- gpu->base_rate_shader = clk_get_rate(gpu->clk_shader);
+ err = etnaviv_gpu_clk_get(gpu);
+ if (err)
+ return err;
/* TODO: figure out max mapped size */
dev_set_drvdata(dev, gpu);
--
2.25.1
[PATCH v9 7/9] drm/etnaviv: Add support for the dma coherent device
From: Sui Jingfeng
Loongson CPUs maintain cache coherency by hardware, which means that the
data in the CPU cache is identical to the data in main system memory. As
for the peripheral device, most of Loongson chips chose to define the
peripherals as DMA coherent by default, device drivers do not need to
maintain the coherency between a processor and an I/O device manually.
There are exceptions, for LS2K1000 SoC, part of peripheral device can be
configured as DMA non-coherent. But there is no released version of such
firmware exist in the market. Peripherals of older LS2K1000 is also DMA
non-coherent, but they are nearly outdated. So, those are trivial cases.
Nevertheless, kernel space still need to do the probe work, because vivante
GPU IP has been integrated into various platform. Hence, this patch add
runtime detection code to probe if a specific GPU is DMA coherent, If the
answer is yes, we are going to utilize such features. On Loongson platform,
When a buffer is accessed by both the GPU and the CPU, the driver should
prefer ETNA_BO_CACHED over ETNA_BO_WC.
This patch also add a new parameter: etnaviv_param_gpu_coherent, which
allow userspace to know if such a feature is available. Because
write-combined BO is still preferred in some case, especially where don't
need CPU read, for example, uploading shader bin.
Cc: Lucas Stach
Cc: Christian Gmeiner
Cc: Philipp Zabel
Cc: Bjorn Helgaas
Cc: Daniel Vetter
Signed-off-by: Sui Jingfeng
---
drivers/gpu/drm/etnaviv/etnaviv_drv.c | 34 +
drivers/gpu/drm/etnaviv/etnaviv_drv.h | 6
drivers/gpu/drm/etnaviv/etnaviv_gem.c | 22 ++---
drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c | 7 -
drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 4 +++
include/uapi/drm/etnaviv_drm.h | 1 +
6 files changed, 69 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_drv.c
b/drivers/gpu/drm/etnaviv/etnaviv_drv.c
index 0a365e96d371..1c9386e5a1b0 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_drv.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_drv.c
@@ -5,7 +5,9 @@
#include
#include
+#include
#include
+#include
#include
#include
@@ -24,6 +26,34 @@
#include "etnaviv_pci_drv.h"
#include "etnaviv_perfmon.h"
+static struct device_node *etnaviv_of_first_available_node(void)
+{
+ struct device_node *core_node;
+
+ for_each_compatible_node(core_node, NULL, "vivante,gc") {
+ if (of_device_is_available(core_node))
+ return core_node;
+ }
+
+ return NULL;
+}
+
+static bool etnaviv_is_dma_coherent(struct device *dev)
+{
+ struct device_node *np;
+ bool coherent;
+
+ np = etnaviv_of_first_available_node();
+ if (np) {
+ coherent = of_dma_is_coherent(np);
+ of_node_put(np);
+ } else {
+ coherent = dev_is_dma_coherent(dev);
+ }
+
+ return coherent;
+}
+
/*
* etnaviv private data construction and destructions:
*/
@@ -52,6 +82,10 @@ etnaviv_alloc_private(struct device *dev, struct drm_device
*drm)
return ERR_PTR(-ENOMEM);
}
+ priv->dma_coherent = etnaviv_is_dma_coherent(dev);
+
+ drm_info(drm, "%s is dma coherent\n", dev_name(dev));
+
return priv;
}
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_drv.h
b/drivers/gpu/drm/etnaviv/etnaviv_drv.h
index 9cd72948cfad..644e5712c050 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_drv.h
+++ b/drivers/gpu/drm/etnaviv/etnaviv_drv.h
@@ -46,6 +46,12 @@ struct etnaviv_drm_private {
struct xarray active_contexts;
u32 next_context_id;
+ /*
+* If true, the GPU is capable of snooping cpu cache. Here, it
+* also means that cache coherency is enforced by the hardware.
+*/
+ bool dma_coherent;
+
/* list of GEM objects: */
struct mutex gem_lock;
struct list_head gem_list;
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gem.c
b/drivers/gpu/drm/etnaviv/etnaviv_gem.c
index b5f73502e3dd..39bdc3774f2d 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_gem.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_gem.c
@@ -343,6 +343,7 @@ void *etnaviv_gem_vmap(struct drm_gem_object *obj)
static void *etnaviv_gem_vmap_impl(struct etnaviv_gem_object *obj)
{
struct page **pages;
+ pgprot_t prot;
lockdep_assert_held(>lock);
@@ -350,8 +351,19 @@ static void *etnaviv_gem_vmap_impl(struct
etnaviv_gem_object *obj)
if (IS_ERR(pages))
return NULL;
- return vmap(pages, obj->base.size >> PAGE_SHIFT,
- VM_MAP, pgprot_writecombine(PAGE_KERNEL));
+ switch (obj->flags) {
+ case ETNA_BO_CACHED:
+ prot = PAGE_KERNEL;
+ break;
+ case ETNA_BO_UNCACHED:
+ prot = pgprot_noncached(PAGE_KERNEL);
+ break;
+ case ETNA_BO_WC:
+ default:
+ prot =
[PATCH v9 0/9] drm/etnaviv: Add pci device driver support
From: Sui Jingfeng There is a Vivante GC1000 (v5037) in LS2K1000 and LS7A1000, this GPU is a PCI device, and it has 2D and 3D cores in the same core. This series is trying to add PCI device driver support to etnaviv. v6: * Fix build issue on system without CONFIG_PCI enabled v7: * Add a separate patch for the platform driver rearrangement (Bjorn) * Switch to runtime check if the GPU is dma coherent or not (Lucas) * Add ETNAVIV_PARAM_GPU_COHERENT to allow userspace to query (Lucas) * Remove etnaviv_gpu.no_clk member (Lucas) * Various Typos and coding style fixed (Bjorn) v8: * Fix typos and remove unnecessary header included (Bjorn). * Add a dedicated function to create the virtual master platform device. v9: * Use PCI_VDEVICE() macro (Bjorn) * Add trivial stubs for trivial stubs for the PCI driver (Bjorn) * Remove a redundant dev_err() usage (Bjorn) * Clean up etnaviv_pdev_probe() also. Sui Jingfeng (9): drm/etnaviv: Add a dedicated function to register an irq handler drm/etnaviv: Add a dedicated function to get various clocks drm/etnaviv: Add dedicated functions to create and destroy platform device drm/etnaviv: Add helpers for private data construction and destruction drm/etnaviv: Allow bypass component framework drm/etnaviv: Add driver support for the PCI devices drm/etnaviv: Add support for the dma coherent device drm/etnaviv: Add a dedicated function to create the virtual master drm/etnaviv: Clean up etnaviv_pdev_probe() function drivers/gpu/drm/etnaviv/Kconfig | 10 + drivers/gpu/drm/etnaviv/Makefile| 2 + drivers/gpu/drm/etnaviv/etnaviv_drv.c | 315 ++-- drivers/gpu/drm/etnaviv/etnaviv_drv.h | 10 + drivers/gpu/drm/etnaviv/etnaviv_gem.c | 22 +- drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c | 7 +- drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 166 +++ drivers/gpu/drm/etnaviv/etnaviv_gpu.h | 9 + drivers/gpu/drm/etnaviv/etnaviv_pci_drv.c | 75 + drivers/gpu/drm/etnaviv/etnaviv_pci_drv.h | 18 ++ include/uapi/drm/etnaviv_drm.h | 1 + 11 files changed, 476 insertions(+), 159 deletions(-) create mode 100644 drivers/gpu/drm/etnaviv/etnaviv_pci_drv.c create mode 100644 drivers/gpu/drm/etnaviv/etnaviv_pci_drv.h -- 2.25.1
[PATCH v9 1/9] drm/etnaviv: Add a dedicated function to register an irq handler
From: Sui Jingfeng
Because getting IRQ from a device is platform-dependent, PCI devices have
different methods for getting an IRQ. This patch is a preparation patch to
extend the driver for the PCI device support.
Cc: Lucas Stach
Cc: Christian Gmeiner
Cc: Philipp Zabel
Cc: Bjorn Helgaas
Cc: Daniel Vetter
Signed-off-by: Sui Jingfeng
---
drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 32 +++
1 file changed, 23 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
index de8c9894967c..a03e81337d8f 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
@@ -1817,6 +1817,27 @@ static const struct of_device_id etnaviv_gpu_match[] = {
};
MODULE_DEVICE_TABLE(of, etnaviv_gpu_match);
+static int etnaviv_gpu_register_irq(struct etnaviv_gpu *gpu, int irq)
+{
+ struct device *dev = gpu->dev;
+ int err;
+
+ if (irq < 0)
+ return irq;
+
+ err = devm_request_irq(dev, irq, irq_handler, 0, dev_name(dev), gpu);
+ if (err) {
+ dev_err(dev, "failed to request irq %u: %d\n", irq, err);
+ return err;
+ }
+
+ gpu->irq = irq;
+
+ dev_info(dev, "irq(%d) handler registered\n", irq);
+
+ return 0;
+}
+
static int etnaviv_gpu_platform_probe(struct platform_device *pdev)
{
struct device *dev = >dev;
@@ -1837,16 +1858,9 @@ static int etnaviv_gpu_platform_probe(struct
platform_device *pdev)
return PTR_ERR(gpu->mmio);
/* Get Interrupt: */
- gpu->irq = platform_get_irq(pdev, 0);
- if (gpu->irq < 0)
- return gpu->irq;
-
- err = devm_request_irq(>dev, gpu->irq, irq_handler, 0,
- dev_name(gpu->dev), gpu);
- if (err) {
- dev_err(dev, "failed to request IRQ%u: %d\n", gpu->irq, err);
+ err = etnaviv_gpu_register_irq(gpu, platform_get_irq(pdev, 0));
+ if (err)
return err;
- }
/* Get Clocks: */
gpu->clk_reg = devm_clk_get_optional(>dev, "reg");
--
2.25.1
Re: [PATCH] drm/i915/guc/slpc: Apply min softlimit correctly
On Fri, 09 Jun 2023 15:02:52 -0700, Vinay Belgaumkar wrote:
>
Hi Vinay,
> We were skipping when min_softlimit was equal to RPn. We need to apply
> it rergardless as efficient frequency will push the SLPC min to RPe.
regardless
> This will break scenarios where user sets a min softlimit < RPe before
> reset and then performs a GT reset.
Can you explain the reason for the patch clearly in terms of variables in
the code, what variable has what value and what is the bug. I am not
following from the above description.
Thanks.
--
Ashutosh
>
> Fixes: 95ccf312a1e4 ("drm/i915/guc/slpc: Allow SLPC to use efficient
> frequency")
>
> Signed-off-by: Vinay Belgaumkar
> ---
> drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
> index 01b75529311c..ee9f83af7cf6 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
> @@ -606,7 +606,7 @@ static int slpc_set_softlimits(struct intel_guc_slpc
> *slpc)
> if (unlikely(ret))
> return ret;
> slpc_to_gt(slpc)->defaults.min_freq = slpc->min_freq_softlimit;
> - } else if (slpc->min_freq_softlimit != slpc->min_freq) {
> + } else {
> return intel_guc_slpc_set_min_freq(slpc,
> slpc->min_freq_softlimit);
> }
> --
> 2.38.1
>
Re: [2/2] drm: Remove struct drm_driver.gem_prime_mmap
On 2023/6/14 01:27, Sui Jingfeng wrote:
Wow, so many drivers get nuked!
On 2023/6/13 22:51, Thomas Zimmermann wrote:
All drivers initialize this field with drm_gem_prime_mmap(). Call
the function directly and remove the field. Simplifies the code and
resolves a long-standing TODO item.
Signed-off-by: Thomas Zimmermann
Reviewed-by: Alex Deucher
I have tested this patch briefly with drm/amdgpu(RX560), Running
glmark2, the rendered scene looks OK.
But single driver is self-sharing. I think I should test this more
with multiple video card.
No need to test; it's equivalent to removing a wrapper.
But new DRM (un-upstreamed) drivers cannot be compiled anymore with this
patch applied.
This makes them all out-of-date or going to be outdated; this is
embarrassing!
---
Documentation/gpu/todo.rst | 9 -
drivers/accel/ivpu/ivpu_drv.c | 1 -
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 1 -
drivers/gpu/drm/drm_fbdev_dma.c | 6 +-
drivers/gpu/drm/drm_prime.c | 14 ++
drivers/gpu/drm/etnaviv/etnaviv_drv.c | 1 -
drivers/gpu/drm/exynos/exynos_drm_drv.c | 1 -
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c | 1 -
drivers/gpu/drm/lima/lima_drv.c | 1 -
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 1 -
drivers/gpu/drm/msm/msm_drv.c | 1 -
drivers/gpu/drm/msm/msm_drv.h | 1 -
drivers/gpu/drm/msm/msm_gem_prime.c | 5 -
drivers/gpu/drm/nouveau/nouveau_drm.c | 1 -
drivers/gpu/drm/panfrost/panfrost_drv.c | 1 -
drivers/gpu/drm/pl111/pl111_drv.c | 1 -
drivers/gpu/drm/radeon/radeon_drv.c | 1 -
drivers/gpu/drm/renesas/rcar-du/rcar_du_drv.c | 1 -
drivers/gpu/drm/rockchip/rockchip_drm_drv.c | 1 -
drivers/gpu/drm/v3d/v3d_drv.c | 1 -
drivers/gpu/drm/virtio/virtgpu_drv.c | 1 -
drivers/gpu/drm/xen/xen_drm_front.c | 1 -
include/drm/drm_drv.h | 14 --
include/drm/drm_gem_dma_helper.h | 6 ++
include/drm/drm_gem_shmem_helper.h | 1 -
include/drm/drm_gem_vram_helper.h | 1 -
26 files changed, 5 insertions(+), 69 deletions(-)
diff --git a/Documentation/gpu/todo.rst b/Documentation/gpu/todo.rst
index 68bdafa0284f5..ca1efad8c89c3 100644
--- a/Documentation/gpu/todo.rst
+++ b/Documentation/gpu/todo.rst
@@ -319,15 +319,6 @@ Contact: Daniel Vetter, Noralf Tronnes
Level: Advanced
-struct drm_gem_object_funcs
-
-GEM objects can now have a function table instead of having the
callbacks on the
-DRM driver struct. This is now the preferred way. Callbacks in
drivers have been
-converted, except for struct drm_driver.gem_prime_mmap.
-
-Level: Intermediate
-
connector register/unregister fixes
---
diff --git a/drivers/accel/ivpu/ivpu_drv.c
b/drivers/accel/ivpu/ivpu_drv.c
index 2df7643b843d5..9f2b9fdcc5498 100644
--- a/drivers/accel/ivpu/ivpu_drv.c
+++ b/drivers/accel/ivpu/ivpu_drv.c
@@ -376,7 +376,6 @@ static const struct drm_driver driver = {
.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
.gem_prime_import = ivpu_gem_prime_import,
- .gem_prime_mmap = drm_gem_prime_mmap,
.ioctls = ivpu_drm_ioctls,
.num_ioctls = ARRAY_SIZE(ivpu_drm_ioctls),
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index c9a41c997c6c7..7681f79f462eb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -2809,7 +2809,6 @@ static const struct drm_driver
amdgpu_kms_driver = {
.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
.gem_prime_import = amdgpu_gem_prime_import,
- .gem_prime_mmap = drm_gem_prime_mmap,
.name = DRIVER_NAME,
.desc = DRIVER_DESC,
diff --git a/drivers/gpu/drm/drm_fbdev_dma.c
b/drivers/gpu/drm/drm_fbdev_dma.c
index d86773fa8ab00..8217f1ddc0075 100644
--- a/drivers/gpu/drm/drm_fbdev_dma.c
+++ b/drivers/gpu/drm/drm_fbdev_dma.c
@@ -54,12 +54,8 @@ static void drm_fbdev_dma_fb_destroy(struct
fb_info *info)
static int drm_fbdev_dma_fb_mmap(struct fb_info *info, struct
vm_area_struct *vma)
{
struct drm_fb_helper *fb_helper = info->par;
- struct drm_device *dev = fb_helper->dev;
-
- if (drm_WARN_ON_ONCE(dev, !fb_helper->dev->driver->gem_prime_mmap))
- return -ENODEV;
- return
fb_helper->dev->driver->gem_prime_mmap(fb_helper->buffer->gem, vma);
+ return drm_gem_prime_mmap(fb_helper->buffer->gem, vma);
}
static const struct fb_ops drm_fbdev_dma_fb_ops = {
diff --git a/drivers/gpu/drm/drm_prime.c b/drivers/gpu/drm/drm_prime.c
index
[PATCH] drm/amdkfd: Switch over to memdup_user()
Use memdup_user() rather than duplicating its implementation. This is a little bit restricted to reduce false positives. ./drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c:2813:13-20: WARNING opportunity for memdup_user. Reported-by: Abaci Robot Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=5523 Signed-off-by: Jiapeng Chong --- drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 9 +++-- 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index d6b15493fffd..637962d4083c 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c @@ -2810,12 +2810,9 @@ static uint32_t *get_queue_ids(uint32_t num_queues, uint32_t *usr_queue_id_array if (!usr_queue_id_array) return NULL; - queue_ids = kzalloc(array_size, GFP_KERNEL); - if (!queue_ids) - return ERR_PTR(-ENOMEM); - - if (copy_from_user(queue_ids, usr_queue_id_array, array_size)) - return ERR_PTR(-EFAULT); + queue_ids = memdup_user(usr_queue_id_array, array_size); + if (IS_ERR(queue_ids)) + return PTR_ERR(queue_ids); return queue_ids; } -- 2.20.1.7.g153144c
[PATCH 3/3] drm/msm/dsi: Enable DATABUS_WIDEN for DSI command mode
DSI 6G v2.5.x+ supports a data-bus widen mode that allows DSI to send
48 bits of compressed data per pclk instead of 24.
For all chipsets that support this mode, enable it whenever DSC is
enabled as recommend by the hardware programming guide.
Only enable this for command mode as we are currently unable to validate
it for video mode.
Signed-off-by: Jessica Zhang
---
Note: The dsi.xml.h changes were generated using the headergen2 script in
envytools [1], but the changes to the copyright and rules-ng-ng source file
paths were dropped.
[1] https://github.com/freedreno/envytools/
drivers/gpu/drm/msm/dsi/dsi.xml.h | 1 +
drivers/gpu/drm/msm/dsi/dsi_host.c | 19 ++-
2 files changed, 19 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi.xml.h
b/drivers/gpu/drm/msm/dsi/dsi.xml.h
index a4a154601114..2a7d980e12c3 100644
--- a/drivers/gpu/drm/msm/dsi/dsi.xml.h
+++ b/drivers/gpu/drm/msm/dsi/dsi.xml.h
@@ -664,6 +664,7 @@ static inline uint32_t
DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP(enum dsi_rgb_swap v
return ((val) << DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP__SHIFT) &
DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP__MASK;
}
#define DSI_CMD_MODE_MDP_CTRL2_BURST_MODE 0x0001
+#define DSI_CMD_MODE_MDP_CTRL2_DATABUS_WIDEN 0x0010
#define REG_DSI_CMD_MODE_MDP_STREAM2_CTRL 0x01b8
#define DSI_CMD_MODE_MDP_STREAM2_CTRL_DATA_TYPE__MASK 0x003f
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
b/drivers/gpu/drm/msm/dsi/dsi_host.c
index 5d7b4409e4e9..1da5238e7105 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -927,6 +927,9 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host,
bool is_bonded_dsi)
u32 hdisplay = mode->hdisplay;
u32 wc;
int ret;
+ bool widebus_supported = msm_host->cfg_hnd->major ==
MSM_DSI_VER_MAJOR_6G &&
+ msm_host->cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V2_5_0;
+
DBG("");
@@ -973,8 +976,15 @@ static void dsi_timing_setup(struct msm_dsi_host
*msm_host, bool is_bonded_dsi)
*
* hdisplay will be divided by 3 here to account for the fact
* that DPU sends 3 bytes per pclk cycle to DSI.
+*
+* If widebus is supported, set DATABUS_WIDEN register and
divide hdisplay by 6
+* instead of 3
*/
- hdisplay =
DIV_ROUND_UP(msm_dsc_get_bytes_per_line(msm_host->dsc), 3);
+ if (!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) &&
widebus_supported)
+ hdisplay =
DIV_ROUND_UP(msm_dsc_get_bytes_per_line(msm_host->dsc), 6);
+ else
+ hdisplay =
DIV_ROUND_UP(msm_dsc_get_bytes_per_line(msm_host->dsc), 3);
+
h_total += hdisplay;
ha_end = ha_start + hdisplay;
}
@@ -1027,6 +1037,13 @@ static void dsi_timing_setup(struct msm_dsi_host
*msm_host, bool is_bonded_dsi)
dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_TOTAL,
DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL(hdisplay) |
DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL(mode->vdisplay));
+
+ if (msm_host->dsc && widebus_supported) {
+ u32 mdp_ctrl2 = dsi_read(msm_host,
REG_DSI_CMD_MODE_MDP_CTRL2);
+
+ mdp_ctrl2 |= DSI_CMD_MODE_MDP_CTRL2_DATABUS_WIDEN;
+ dsi_write(msm_host, REG_DSI_CMD_MODE_MDP_CTRL2,
mdp_ctrl2);
+ }
}
}
--
2.40.1
[PATCH 2/3] drm/msm/dpu: Set DATABUS_WIDEN on command mode encoders
Add a DPU INTF op to set the DATABUS_WIDEN register to enable the
databus-widen mode datapath.
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 3 +++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 12
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 3 +++
3 files changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
index b856c6286c85..124ba96bebda 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
@@ -70,6 +70,9 @@ static void _dpu_encoder_phys_cmd_update_intf_cfg(
if (intf_cfg.dsc != 0 && phys_enc->hw_intf->ops.enable_compression)
phys_enc->hw_intf->ops.enable_compression(phys_enc->hw_intf);
+
+ if (phys_enc->hw_intf->ops.enable_widebus)
+ phys_enc->hw_intf->ops.enable_widebus(phys_enc->hw_intf);
}
static void dpu_encoder_phys_cmd_pp_tx_done_irq(void *arg, int irq_idx)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
index 5b0f6627e29b..03ba3a1c7a46 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
@@ -513,6 +513,15 @@ static void dpu_hw_intf_disable_autorefresh(struct
dpu_hw_intf *intf,
}
+static void dpu_hw_intf_enable_widebus(struct dpu_hw_intf *ctx)
+{
+ u32 intf_cfg2 = DPU_REG_READ(>hw, INTF_CONFIG2);
+
+ intf_cfg2 |= INTF_CFG2_DATABUS_WIDEN;
+
+ DPU_REG_WRITE(>hw, INTF_CONFIG2, intf_cfg2);
+}
+
static void dpu_hw_intf_enable_compression(struct dpu_hw_intf *ctx)
{
u32 intf_cfg2 = DPU_REG_READ(>hw, INTF_CONFIG2);
@@ -545,6 +554,9 @@ static void _setup_intf_ops(struct dpu_hw_intf_ops *ops,
if (cap & BIT(DPU_INTF_DATA_COMPRESS))
ops->enable_compression = dpu_hw_intf_enable_compression;
+
+ if (cap & BIT(DPU_INTF_DATABUS_WIDEN))
+ ops->enable_widebus = dpu_hw_intf_enable_widebus;
}
struct dpu_hw_intf *dpu_hw_intf_init(const struct dpu_intf_cfg *cfg,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
index 99e21c4137f9..64a17b99d3d1 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
@@ -71,6 +71,7 @@ struct intf_status {
* Return: 0 on success, -ETIMEDOUT on timeout
* @vsync_sel: Select vsync signal for tear-effect
configuration
* @enable_compression: Enable data compression
+ * @enable_widebus: Enable widebus
*/
struct dpu_hw_intf_ops {
void (*setup_timing_gen)(struct dpu_hw_intf *intf,
@@ -109,6 +110,8 @@ struct dpu_hw_intf_ops {
void (*disable_autorefresh)(struct dpu_hw_intf *intf, uint32_t
encoder_id, u16 vdisplay);
void (*enable_compression)(struct dpu_hw_intf *intf);
+
+ void (*enable_widebus)(struct dpu_hw_intf *intf);
};
struct dpu_hw_intf {
--
2.40.1
[PATCH 1/3] drm/msm/dpu: Add DPU_INTF_DATABUS_WIDEN feature flag for DPU >= 5.0
DPU 5.x+ supports a databus widen mode that allows more data to be sent
per pclk. Enable this feature flag on all relevant chipsets.
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 ++-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 ++
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 36ba3f58dcdf..0be7bf0bfc41 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -103,7 +103,8 @@
(BIT(DPU_INTF_INPUT_CTRL) | \
BIT(DPU_INTF_TE) | \
BIT(DPU_INTF_STATUS_SUPPORTED) | \
-BIT(DPU_DATA_HCTL_EN))
+BIT(DPU_DATA_HCTL_EN) | \
+BIT(DPU_INTF_DATABUS_WIDEN))
#define INTF_SC7280_MASK (INTF_SC7180_MASK | BIT(DPU_INTF_DATA_COMPRESS))
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index b860784ade72..b9939e00f5e0 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -182,6 +182,7 @@ enum {
* than video timing
* @DPU_INTF_STATUS_SUPPORTED INTF block has INTF_STATUS register
* @DPU_INTF_DATA_COMPRESS INTF block has DATA_COMPRESS register
+ * @DPU_INTF_DATABUS_WIDEN INTF block has DATABUS_WIDEN register
* @DPU_INTF_MAX
*/
enum {
@@ -190,6 +191,7 @@ enum {
DPU_DATA_HCTL_EN,
DPU_INTF_STATUS_SUPPORTED,
DPU_INTF_DATA_COMPRESS,
+ DPU_INTF_DATABUS_WIDEN,
DPU_INTF_MAX
};
--
2.40.1
[PATCH 0/3] Add support for databus widen mode
DPU 5.x+ and DSI 6G 2.5.x+ support a databus-widen mode that allows for more compressed data to be transferred per pclk. This series adds support for enabling this feature for both DPU and DSI by doing the following: 1. Add a DPU_INTF_DATABUS_WIDEN feature flag 2. Add a DPU INTF op to set the DATABUS_WIDEN register 3. Set the DATABUS_WIDEN register and do the proper hdisplay calculations in DSI when applicable Note: This series will only enable the databus-widen mode for command mode as we are currently unable to validate it on video mode. Depends on: "Add DSC v1.2 Support for DSI" [1] [1] https://patchwork.freedesktop.org/series/117219/ Signed-off-by: Jessica Zhang --- Jessica Zhang (3): drm/msm/dpu: Add DPU_INTF_DATABUS_WIDEN feature flag for DPU >= 5.0 drm/msm/dpu: Set DATABUS_WIDEN on command mode encoders drm/msm/dsi: Enable DATABUS_WIDEN for DSI command mode drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 3 +++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 ++- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 12 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 3 +++ drivers/gpu/drm/msm/dsi/dsi.xml.h| 1 + drivers/gpu/drm/msm/dsi/dsi_host.c | 19 ++- 7 files changed, 41 insertions(+), 2 deletions(-) --- base-commit: 1981c2c0c05f5d7fe4d4552d4f352cb46840e51e change-id: 20230525-add-widebus-support-f785546ee751 Best regards, -- Jessica Zhang
[PATCH] drm/fbdev-generic: Remove a redundant assignment clause
The assignment "dst = map;" in the drm_fbdev_generic_damage_blit() function
is redundant because it has already been copied when the call to
drm_client_buffer_vmap() is finished. Therefore, this patch saves a useless
copy. No functional change.
Signed-off-by: Sui Jingfeng
---
drivers/gpu/drm/drm_fbdev_generic.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/drm_fbdev_generic.c
b/drivers/gpu/drm/drm_fbdev_generic.c
index 98ae703848a0..aa6924e3a58c 100644
--- a/drivers/gpu/drm/drm_fbdev_generic.c
+++ b/drivers/gpu/drm/drm_fbdev_generic.c
@@ -182,7 +182,7 @@ static int drm_fbdev_generic_damage_blit(struct
drm_fb_helper *fb_helper,
struct drm_clip_rect *clip)
{
struct drm_client_buffer *buffer = fb_helper->buffer;
- struct iosys_map map, dst;
+ struct iosys_map map;
int ret;
/*
@@ -202,8 +202,7 @@ static int drm_fbdev_generic_damage_blit(struct
drm_fb_helper *fb_helper,
if (ret)
goto out;
- dst = map;
- drm_fbdev_generic_damage_blit_real(fb_helper, clip, );
+ drm_fbdev_generic_damage_blit_real(fb_helper, clip, );
drm_client_buffer_vunmap(buffer);
--
2.25.1
Re: [PATCH drm-next v4 14/14] drm/nouveau: debugfs: implement DRM GPU VA debugfs
* Danilo Krummrich [230606 18:32]:
> Provide the driver indirection iterating over all DRM GPU VA spaces to
> enable the common 'gpuvas' debugfs file for dumping DRM GPU VA spaces.
>
> Signed-off-by: Danilo Krummrich
> ---
> drivers/gpu/drm/nouveau/nouveau_debugfs.c | 39 +++
> 1 file changed, 39 insertions(+)
>
> diff --git a/drivers/gpu/drm/nouveau/nouveau_debugfs.c
> b/drivers/gpu/drm/nouveau/nouveau_debugfs.c
> index 99d022a91afc..053f703f2f68 100644
> --- a/drivers/gpu/drm/nouveau/nouveau_debugfs.c
> +++ b/drivers/gpu/drm/nouveau/nouveau_debugfs.c
> @@ -203,6 +203,44 @@ nouveau_debugfs_pstate_open(struct inode *inode, struct
> file *file)
> return single_open(file, nouveau_debugfs_pstate_get, inode->i_private);
> }
>
> +static void
> +nouveau_debugfs_gpuva_regions(struct seq_file *m, struct nouveau_uvmm *uvmm)
> +{
> + MA_STATE(mas, >region_mt, 0, 0);
> + struct nouveau_uvma_region *reg;
> +
> + seq_puts (m, " VA regions | start | range |
> end\n");
> + seq_puts (m,
> "\n");
rcu_read_lock();
> + mas_for_each(, reg, ULONG_MAX)
> + seq_printf(m, " | 0x%016llx | 0x%016llx |
> 0x%016llx\n",
> +reg->va.addr, reg->va.range, reg->va.addr +
> reg->va.range);
rcu_read_unlock();
> +}
> +
> +static int
> +nouveau_debugfs_gpuva(struct seq_file *m, void *data)
> +{
> + struct drm_info_node *node = (struct drm_info_node *) m->private;
> + struct nouveau_drm *drm = nouveau_drm(node->minor->dev);
> + struct nouveau_cli *cli;
> +
> + mutex_lock(>clients_lock);
> + list_for_each_entry(cli, >clients, head) {
> + struct nouveau_uvmm *uvmm = nouveau_cli_uvmm(cli);
> +
> + if (!uvmm)
> + continue;
> +
> + nouveau_uvmm_lock(uvmm);
> + drm_debugfs_gpuva_info(m, >umgr);
> + seq_puts(m, "\n");
> + nouveau_debugfs_gpuva_regions(m, uvmm);
> + nouveau_uvmm_unlock(uvmm);
> + }
> + mutex_unlock(>clients_lock);
> +
> + return 0;
> +}
> +
> static const struct file_operations nouveau_pstate_fops = {
> .owner = THIS_MODULE,
> .open = nouveau_debugfs_pstate_open,
> @@ -214,6 +252,7 @@ static const struct file_operations nouveau_pstate_fops =
> {
> static struct drm_info_list nouveau_debugfs_list[] = {
> { "vbios.rom", nouveau_debugfs_vbios_image, 0, NULL },
> { "strap_peek", nouveau_debugfs_strap_peek, 0, NULL },
> + DRM_DEBUGFS_GPUVA_INFO(nouveau_debugfs_gpuva, NULL),
> };
> #define NOUVEAU_DEBUGFS_ENTRIES ARRAY_SIZE(nouveau_debugfs_list)
>
> --
> 2.40.1
>
Re: [PATCH drm-next v4 03/14] drm: manager to keep track of GPUs VA mappings
* Danilo Krummrich [230606 18:32]: > Add infrastructure to keep track of GPU virtual address (VA) mappings > with a decicated VA space manager implementation. > > New UAPIs, motivated by Vulkan sparse memory bindings graphics drivers > start implementing, allow userspace applications to request multiple and > arbitrary GPU VA mappings of buffer objects. The DRM GPU VA manager is > intended to serve the following purposes in this context. > > 1) Provide infrastructure to track GPU VA allocations and mappings, >making use of the maple_tree. > > 2) Generically connect GPU VA mappings to their backing buffers, in >particular DRM GEM objects. > > 3) Provide a common implementation to perform more complex mapping >operations on the GPU VA space. In particular splitting and merging >of GPU VA mappings, e.g. for intersecting mapping requests or partial >unmap requests. > > Suggested-by: Dave Airlie > Signed-off-by: Danilo Krummrich > --- > Documentation/gpu/drm-mm.rst| 31 + > drivers/gpu/drm/Makefile|1 + > drivers/gpu/drm/drm_gem.c |3 + > drivers/gpu/drm/drm_gpuva_mgr.c | 1687 +++ > include/drm/drm_drv.h |6 + > include/drm/drm_gem.h | 75 ++ > include/drm/drm_gpuva_mgr.h | 681 + > 7 files changed, 2484 insertions(+) > create mode 100644 drivers/gpu/drm/drm_gpuva_mgr.c > create mode 100644 include/drm/drm_gpuva_mgr.h > > diff --git a/Documentation/gpu/drm-mm.rst b/Documentation/gpu/drm-mm.rst > index a52e6f4117d6..c9f120cfe730 100644 > --- a/Documentation/gpu/drm-mm.rst > +++ b/Documentation/gpu/drm-mm.rst > @@ -466,6 +466,37 @@ DRM MM Range Allocator Function References > .. kernel-doc:: drivers/gpu/drm/drm_mm.c > :export: > > +DRM GPU VA Manager > +== > + > +Overview > + > + > +.. kernel-doc:: drivers/gpu/drm/drm_gpuva_mgr.c > + :doc: Overview > + > +Split and Merge > +--- > + > +.. kernel-doc:: drivers/gpu/drm/drm_gpuva_mgr.c > + :doc: Split and Merge > + > +Locking > +--- > + > +.. kernel-doc:: drivers/gpu/drm/drm_gpuva_mgr.c > + :doc: Locking > + > + > +DRM GPU VA Manager Function References > +-- > + > +.. kernel-doc:: include/drm/drm_gpuva_mgr.h > + :internal: > + > +.. kernel-doc:: drivers/gpu/drm/drm_gpuva_mgr.c > + :export: > + > DRM Buddy Allocator > === > > diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile > index 9c6446eb3c83..8eeed446a078 100644 > --- a/drivers/gpu/drm/Makefile > +++ b/drivers/gpu/drm/Makefile > @@ -45,6 +45,7 @@ drm-y := \ > drm_vblank.o \ > drm_vblank_work.o \ > drm_vma_manager.o \ > + drm_gpuva_mgr.o \ > drm_writeback.o > drm-$(CONFIG_DRM_LEGACY) += \ > drm_agpsupport.o \ > diff --git a/drivers/gpu/drm/drm_gem.c b/drivers/gpu/drm/drm_gem.c > index 1a5a2cd0d4ec..cd878ebddbd0 100644 > --- a/drivers/gpu/drm/drm_gem.c > +++ b/drivers/gpu/drm/drm_gem.c > @@ -164,6 +164,9 @@ void drm_gem_private_object_init(struct drm_device *dev, > if (!obj->resv) > obj->resv = >_resv; > > + if (drm_core_check_feature(dev, DRIVER_GEM_GPUVA)) > + drm_gem_gpuva_init(obj); > + > drm_vma_node_reset(>vma_node); > INIT_LIST_HEAD(>lru_node); > } > diff --git a/drivers/gpu/drm/drm_gpuva_mgr.c b/drivers/gpu/drm/drm_gpuva_mgr.c > new file mode 100644 > index ..dd8dd7fef14b > --- /dev/null > +++ b/drivers/gpu/drm/drm_gpuva_mgr.c > @@ -0,0 +1,1687 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (c) 2022 Red Hat. > + * > + * Permission is hereby granted, free of charge, to any person obtaining a > + * copy of this software and associated documentation files (the "Software"), > + * to deal in the Software without restriction, including without limitation > + * the rights to use, copy, modify, merge, publish, distribute, sublicense, > + * and/or sell copies of the Software, and to permit persons to whom the > + * Software is furnished to do so, subject to the following conditions: > + * > + * The above copyright notice and this permission notice shall be included in > + * all copies or substantial portions of the Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL > + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR > + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, > + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR > + * OTHER DEALINGS IN THE SOFTWARE. > + * > + * Authors: > + * Danilo Krummrich > + * > + */ > + > +#include > +#include > + > +/** > + * DOC: Overview > + * > + * The DRM GPU VA Manager, represented by struct drm_gpuva_manager keeps > track > + * of
Re: [PATCH v2 05/22] drm/msm/dpu: always use MSM_DP/DSI_CONTROLLER_n
On 6/12/2023 5:09 PM, Dmitry Baryshkov wrote: In several catalog entries we did not use existing MSM_DP_CONTROLLER_n constants. Fill them in. Also use freshly defined MSM_DSI_CONTROLLER_n for DSI interfaces. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 6 +++--- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 8 drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 8 drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 4 ++-- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 8 drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 4 ++-- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 4 ++-- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 4 ++-- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 4 ++-- 13 files changed, 29 insertions(+), 29 deletions(-) Patch itself is fine. But sm6375 and sm6350 are missing as this needs to be rebased on top of the tip of msm-next-lumag.
Re: [PATCH v3 2/2] drm/msm/dpu: remove struct drm_dsc_config from struct msm_display_info
On 6/13/2023 3:19 PM, Kuogee Hsieh wrote:
ince struct drm_dsc_config is stored at atomic_enable() instead
S got cut off in since
of display setup time during boot up, saving struct drm_dsc_config
at struct msm_display_info is not necessary. Lets drop the dsc member
from struct msm_display_info.
Signed-off-by: Kuogee Hsieh
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 2 --
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 2 --
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 --
3 files changed, 6 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index e00cd39..50ce2ef 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -2309,8 +2309,6 @@ static int dpu_encoder_setup_display(struct
dpu_encoder_virt *dpu_enc,
dpu_enc->idle_pc_supported =
dpu_kms->catalog->caps->has_idle_pc;
- dpu_enc->dsc = disp_info->dsc;
-
mutex_lock(_enc->enc_lock);
for (i = 0; i < disp_info->num_of_h_tiles && !ret; i++) {
/*
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
index 90e1925..4c05fd5 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
@@ -28,7 +28,6 @@
* @is_cmd_mode Boolean to indicate if the CMD mode is requested
* @is_te_using_watchdog_timer: Boolean to indicate watchdog TE is
* used instead of panel TE in cmd mode panels
- * @dsc: DSC configuration data for DSC-enabled displays
*/
struct msm_display_info {
enum dpu_intf_type intf_type;
@@ -36,7 +35,6 @@ struct msm_display_info {
uint32_t h_tile_instance[MAX_H_TILES_PER_DISPLAY];
bool is_cmd_mode;
bool is_te_using_watchdog_timer;
- struct drm_dsc_config *dsc;
};
/**
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 613384b..5e77e09 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -544,8 +544,6 @@ static int _dpu_kms_initialize_dsi(struct drm_device *dev,
info.is_cmd_mode = msm_dsi_is_cmd_mode(priv->dsi[i]);
- info.dsc = msm_dsi_get_dsc_config(priv->dsi[i]);
-
encoder = dpu_encoder_init(dev, DRM_MODE_ENCODER_DSI, );
if (IS_ERR(encoder)) {
DPU_ERROR("encoder init failed for dsi display\n");
Re: [PATCH v3 0/2] retrieve DSI DSC through priv-dsi[0]
On 6/13/2023 3:19 PM, Kuogee Hsieh wrote: moving retrieving struct drm_dsc_cofnig from setup_display to atomic_enable() and delete struct drm_dsc_config from struct msm_display_info. This needs re-wording. Currently, struct drm_dsc_config is retrieved from DSI driver in dpu_encoder_setup_display() and this model works for non-pluggable displays. However this does not scale for pluggable displays because the struct drm_dsc_config is no longer valid after a disconnect and needs to be retrieved from the sink again. Move retrieval of struct drm_dsc_config from dpu_encoder_setup_display() to dpu_encoder_virt_atomic_enable() to make the code path common between pluggable and non-pluggable displays. And also delete struct drm_dsc_config from struct msm_display_info as it will now be unused. Kuogee Hsieh (2): drm/msm/dpu: retrieve DSI DSC struct through priv->dsi[0] drm/msm/dpu: remove struct drm_dsc_config from struct msm_display_info drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 44 - drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 2 -- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 -- 3 files changed, 30 insertions(+), 18 deletions(-)
Re: [PATCH v5] drm/dp_mst: Clear MSG_RDY flag before sending new message
Alright, managed to figure out my MST woes! Just tested with nouveau and I see
no regressions :)
Reviewed-by: Lyude Paul
On Fri, 2023-06-09 at 18:49 +0800, Wayne Lin wrote:
> [Why]
> The sequence for collecting down_reply from source perspective should
> be:
>
> Request_n->repeat (get partial reply of Request_n->clear message ready
> flag to ack DPRX that the message is received) till all partial
> replies for Request_n are received->new Request_n+1.
>
> Now there is chance that drm_dp_mst_hpd_irq() will fire new down
> request in the tx queue when the down reply is incomplete. Source is
> restricted to generate interveleaved message transactions so we should
> avoid it.
>
> Also, while assembling partial reply packets, reading out DPCD DOWN_REP
> Sideband MSG buffer + clearing DOWN_REP_MSG_RDY flag should be
> wrapped up as a complete operation for reading out a reply packet.
> Kicking off a new request before clearing DOWN_REP_MSG_RDY flag might
> be risky. e.g. If the reply of the new request has overwritten the
> DPRX DOWN_REP Sideband MSG buffer before source writing one to clear
> DOWN_REP_MSG_RDY flag, source then unintentionally flushes the reply
> for the new request. Should handle the up request in the same way.
>
> [How]
> Separete drm_dp_mst_hpd_irq() into 2 steps. After acking the MST IRQ
> event, driver calls drm_dp_mst_hpd_irq_send_new_request() and might
> trigger drm_dp_mst_kick_tx() only when there is no on going message
> transaction.
>
> Changes since v1:
> * Reworked on review comments received
> -> Adjust the fix to let driver explicitly kick off new down request
> when mst irq event is handled and acked
> -> Adjust the commit message
>
> Changes since v2:
> * Adjust the commit message
> * Adjust the naming of the divided 2 functions and add a new input
> parameter "ack".
> * Adjust code flow as per review comments.
>
> Changes since v3:
> * Update the function description of drm_dp_mst_hpd_irq_handle_event
>
> Changes since v4:
> * Change ack of drm_dp_mst_hpd_irq_handle_event() to be an array align
> the size of esi[]
>
> Signed-off-by: Wayne Lin
> Cc: sta...@vger.kernel.org
> ---
> .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 32 +--
> drivers/gpu/drm/display/drm_dp_mst_topology.c | 54 ---
> drivers/gpu/drm/i915/display/intel_dp.c | 7 +--
> drivers/gpu/drm/nouveau/dispnv50/disp.c | 12 +++--
> include/drm/display/drm_dp_mst_helper.h | 7 ++-
> 5 files changed, 81 insertions(+), 31 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index d5cec03eaa8d..ec629b4037e4 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -3263,6 +3263,7 @@ static void dm_handle_mst_sideband_msg(struct
> amdgpu_dm_connector *aconnector)
>
> while (dret == dpcd_bytes_to_read &&
> process_count < max_process_count) {
> + u8 ack[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = {};
> u8 retry;
> dret = 0;
>
> @@ -3271,28 +3272,29 @@ static void dm_handle_mst_sideband_msg(struct
> amdgpu_dm_connector *aconnector)
> DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1],
> esi[2]);
> /* handle HPD short pulse irq */
> if (aconnector->mst_mgr.mst_state)
> - drm_dp_mst_hpd_irq(
> - >mst_mgr,
> - esi,
> - _irq_handled);
> + drm_dp_mst_hpd_irq_handle_event(>mst_mgr,
> + esi,
> + ack,
> + _irq_handled);
>
> if (new_irq_handled) {
> /* ACK at DPCD to notify down stream */
> - const int ack_dpcd_bytes_to_write =
> - dpcd_bytes_to_read - 1;
> -
> for (retry = 0; retry < 3; retry++) {
> - u8 wret;
> -
> - wret = drm_dp_dpcd_write(
> - >dm_dp_aux.aux,
> - dpcd_addr + 1,
> - [1],
> - ack_dpcd_bytes_to_write);
> - if (wret == ack_dpcd_bytes_to_write)
> + ssize_t wret;
> +
> + wret =
> drm_dp_dpcd_writeb(>dm_dp_aux.aux,
> + dpcd_addr + 1,
> + ack[1]);
> + if (wret == 1)
> break;
> }
>
> + if (retry == 3) {
> +
Re: [PATCH v4 0/2] arm64: dts: qcom: add DP Controller to SM8550 DTS
On Tue, 13 Jun 2023 09:30:11 +0200, Neil Armstrong wrote: > The DP output is shared with the USB3 SuperSpeed lanes and is > usually connected to an USB-C port which Altmode is controlled > by the PMIC Glink infrastructure. > > DT changes tying the DP controller to the USB-C port on the QRD > board will be sent later. > > [...] Applied, thanks! [1/2] arm64: dts: qcom: sm8550: fix low_svs RPMhPD labels commit: bbde65f9da9291a77636e1467b28f27ced1b4ece [2/2] arm64: dts: qcom: sm8550: add display port nodes commit: 66adfbc4d33993865a180016db73520a15e754c9 Best regards, -- Bjorn Andersson
Re: (subset) [PATCH v2 0/4] video: backlight: lp855x: modernize bindings
On Fri, 19 May 2023 20:07:24 +0200, Artur Weber wrote: > Convert TI LP855X backlight controller bindings from TXT to YAML and, > while we're at it, rework some of the code related to PWM handling. > Also correct existing DTS files to avoid introducing new dtb_check > errors. > > Signed-off-by: Artur Weber > > [...] Applied, thanks! [4/4] arm64: dts: adapt to LP855X bindings changes commit: ebdcfc8c42c2b9d5ca1b27d8ee558eefb3e904d8 Best regards, -- Bjorn Andersson
[PATCH v3 0/2] retrieve DSI DSC through priv-dsi[0]
moving retrieving struct drm_dsc_cofnig from setup_display to atomic_enable() and delete struct drm_dsc_config from struct msm_display_info. Kuogee Hsieh (2): drm/msm/dpu: retrieve DSI DSC struct through priv->dsi[0] drm/msm/dpu: remove struct drm_dsc_config from struct msm_display_info drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 44 - drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 2 -- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 -- 3 files changed, 30 insertions(+), 18 deletions(-) -- 2.7.4
[PATCH v3 2/2] drm/msm/dpu: remove struct drm_dsc_config from struct msm_display_info
ince struct drm_dsc_config is stored at atomic_enable() instead
of display setup time during boot up, saving struct drm_dsc_config
at struct msm_display_info is not necessary. Lets drop the dsc member
from struct msm_display_info.
Signed-off-by: Kuogee Hsieh
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 2 --
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 2 --
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 --
3 files changed, 6 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index e00cd39..50ce2ef 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -2309,8 +2309,6 @@ static int dpu_encoder_setup_display(struct
dpu_encoder_virt *dpu_enc,
dpu_enc->idle_pc_supported =
dpu_kms->catalog->caps->has_idle_pc;
- dpu_enc->dsc = disp_info->dsc;
-
mutex_lock(_enc->enc_lock);
for (i = 0; i < disp_info->num_of_h_tiles && !ret; i++) {
/*
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
index 90e1925..4c05fd5 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
@@ -28,7 +28,6 @@
* @is_cmd_modeBoolean to indicate if the CMD mode is requested
* @is_te_using_watchdog_timer: Boolean to indicate watchdog TE is
* used instead of panel TE in cmd mode panels
- * @dsc: DSC configuration data for DSC-enabled displays
*/
struct msm_display_info {
enum dpu_intf_type intf_type;
@@ -36,7 +35,6 @@ struct msm_display_info {
uint32_t h_tile_instance[MAX_H_TILES_PER_DISPLAY];
bool is_cmd_mode;
bool is_te_using_watchdog_timer;
- struct drm_dsc_config *dsc;
};
/**
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 613384b..5e77e09 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -544,8 +544,6 @@ static int _dpu_kms_initialize_dsi(struct drm_device *dev,
info.is_cmd_mode = msm_dsi_is_cmd_mode(priv->dsi[i]);
- info.dsc = msm_dsi_get_dsc_config(priv->dsi[i]);
-
encoder = dpu_encoder_init(dev, DRM_MODE_ENCODER_DSI, );
if (IS_ERR(encoder)) {
DPU_ERROR("encoder init failed for dsi display\n");
--
2.7.4
[PATCH v3 1/2] drm/msm/dpu: retrieve DSI DSC struct through priv->dsi[0]
Currently struct drm_dsc_config for DSI is populated at display
setup during system boot up. This mechanism works fine with
embedded display but not for pluggable displays as the
struct drm_dsc_config will become stale once external display
is unplugged.
Move storing of DSI DSC struct to atomic_enable() so that same
mechanism will work for both embedded display and pluggable
displays.
Signed-off-by: Kuogee Hsieh
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 42 -
1 file changed, 30 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 2e1873d..e00cd39 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -543,11 +543,24 @@ bool dpu_encoder_use_dsc_merge(struct drm_encoder
*drm_enc)
return (num_dsc > 0) && (num_dsc > intf_count);
}
+static struct drm_dsc_config *dpu_encoder_get_dsc_config(struct drm_encoder
*drm_enc)
+{
+ struct msm_drm_private *priv = drm_enc->dev->dev_private;
+ struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
+ int index = dpu_enc->disp_info.h_tile_instance[0];
+
+if (dpu_enc->disp_info.intf_type == INTF_DSI)
+ return msm_dsi_get_dsc_config(priv->dsi[index]);
+
+ return NULL;
+}
+
static struct msm_display_topology dpu_encoder_get_topology(
struct dpu_encoder_virt *dpu_enc,
struct dpu_kms *dpu_kms,
struct drm_display_mode *mode,
- struct drm_crtc_state *crtc_state)
+ struct drm_crtc_state *crtc_state,
+ struct drm_dsc_config *dsc)
{
struct msm_display_topology topology = {0};
int i, intf_count = 0;
@@ -579,7 +592,7 @@ static struct msm_display_topology dpu_encoder_get_topology(
topology.num_intf = intf_count;
- if (dpu_enc->dsc) {
+ if (dsc) {
/*
* In case of Display Stream Compression (DSC), we would use
* 2 DSC encoders, 2 layer mixers and 1 interface
@@ -605,6 +618,7 @@ static int dpu_encoder_virt_atomic_check(
struct drm_display_mode *adj_mode;
struct msm_display_topology topology;
struct dpu_global_state *global_state;
+ struct drm_dsc_config *dsc;
int i = 0;
int ret = 0;
@@ -640,7 +654,9 @@ static int dpu_encoder_virt_atomic_check(
}
}
- topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode,
crtc_state);
+ dsc = dpu_encoder_get_dsc_config(drm_enc);
+
+ topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode,
crtc_state, dsc);
/*
* Release and Allocate resources on every modeset
@@ -1072,14 +1088,12 @@ static void dpu_encoder_virt_atomic_mode_set(struct
drm_encoder *drm_enc,
dpu_enc->hw_pp[i] = i < num_pp ? to_dpu_hw_pingpong(hw_pp[i])
: NULL;
- if (dpu_enc->dsc) {
- num_dsc = dpu_rm_get_assigned_resources(_kms->rm,
global_state,
- drm_enc->base.id,
DPU_HW_BLK_DSC,
- hw_dsc,
ARRAY_SIZE(hw_dsc));
- for (i = 0; i < num_dsc; i++) {
- dpu_enc->hw_dsc[i] = to_dpu_hw_dsc(hw_dsc[i]);
- dsc_mask |= BIT(dpu_enc->hw_dsc[i]->idx - DSC_0);
- }
+ num_dsc = dpu_rm_get_assigned_resources(_kms->rm, global_state,
+ drm_enc->base.id,
DPU_HW_BLK_DSC,
+ hw_dsc, ARRAY_SIZE(hw_dsc));
+ for (i = 0; i < num_dsc; i++) {
+ dpu_enc->hw_dsc[i] = to_dpu_hw_dsc(hw_dsc[i]);
+ dsc_mask |= BIT(dpu_enc->hw_dsc[i]->idx - DSC_0);
}
dpu_enc->dsc_mask = dsc_mask;
@@ -1187,6 +1201,8 @@ static void dpu_encoder_virt_atomic_enable(struct
drm_encoder *drm_enc,
dpu_enc = to_dpu_encoder_virt(drm_enc);
+ dpu_enc->dsc = dpu_encoder_get_dsc_config(drm_enc);
+
mutex_lock(_enc->enc_lock);
cur_mode = _enc->base.crtc->state->adjusted_mode;
@@ -2109,8 +2125,10 @@ void dpu_encoder_helper_phys_cleanup(struct
dpu_encoder_phys *phys_enc)
phys_enc->hw_pp->merge_3d->idx);
}
- if (dpu_enc->dsc)
+ if (dpu_enc->dsc) {
dpu_encoder_unprep_dsc(dpu_enc);
+ dpu_enc->dsc = NULL;
+ }
intf_cfg.stream_sel = 0; /* Don't care value for video mode */
intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc);
--
2.7.4
Re: [PATCH v2 04/22] drm/msm: enumerate DSI interfaces
On 6/12/2023 5:09 PM, Dmitry Baryshkov wrote: Follow the DP example and define MSM_DSI_CONTROLLER_n enumeration. Signed-off-by: Dmitry Baryshkov --- Reviewed-by: Abhinav Kumar
Re: [PATCH v2 03/22] drm/msm/dpu: remove unused INTF_NONE interfaces
On 6/12/2023 5:09 PM, Dmitry Baryshkov wrote: sm6115 and qcm2290 do not have INTF_0. Drop corresponding interface definitions. And sm6375 as you are touching that too Signed-off-by: Dmitry Baryshkov --- You can fix that while applying. Reviewed-by: Abhinav Kumar
Re: [PATCH v2 02/22] drm/msm/dpu: correct MERGE_3D length
On 6/12/2023 5:09 PM, Dmitry Baryshkov wrote:
Each MERGE_3D block has just two registers. Correct the block length
accordingly.
Fixes: 4369c93cf36b ("drm/msm/dpu: initial support for merge3D hardware block")
Signed-off-by: Dmitry Baryshkov
---
LGTM,
Reviewed-by: Abhinav Kumar
Re: [PATCH v2 01/22] drm/msm/dpu: fix sc7280 and sc7180 PINGPONG done interrupts
On 6/12/2023 5:09 PM, Dmitry Baryshkov wrote:
During IRQ conversion we have lost the PP_DONE interrupts for sc7280
platform. This was left unnoticed, because this interrupt is only used
for CMD outputs and probably no sc7[12]80 systems use DSI CMD panels.
Fixes: 667e9985ee24 ("drm/msm/dpu: replace IRQ lookup with the data in hw
catalog")
Signed-off-by: Dmitry Baryshkov
---
Yes, was indeed a mistake
Reviewed-by: Abhinav Kumar
Re: [PATCH] drm/nouveau/kms/nv50-: Fix drm_dp_remove_payload() invocation
On Tue, Jun 13, 2023 at 11:05 PM Lyude Paul wrote:
>
> We changed the semantics for this in:
>
> e761cc20946a ("drm/display/dp_mst: Handle old/new payload states in
> drm_dp_remove_payload()")
>
> But I totally forgot to update this properly in nouveau. So, let's do that.
>
> Signed-off-by: Lyude Paul
Reviewed-by: Karol Herbst
> ---
> drivers/gpu/drm/nouveau/dispnv50/disp.c | 8 ++--
> 1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c
> b/drivers/gpu/drm/nouveau/dispnv50/disp.c
> index 5bb777ff13130..1637e08b548c2 100644
> --- a/drivers/gpu/drm/nouveau/dispnv50/disp.c
> +++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c
> @@ -909,15 +909,19 @@ nv50_msto_prepare(struct drm_atomic_state *state,
> struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
> struct nv50_mstc *mstc = msto->mstc;
> struct nv50_mstm *mstm = mstc->mstm;
> - struct drm_dp_mst_atomic_payload *payload;
> + struct drm_dp_mst_topology_state *old_mst_state;
> + struct drm_dp_mst_atomic_payload *payload, *old_payload;
>
> NV_ATOMIC(drm, "%s: msto prepare\n", msto->encoder.name);
>
> + old_mst_state = drm_atomic_get_old_mst_topology_state(state, mgr);
> +
> payload = drm_atomic_get_mst_payload_state(mst_state, mstc->port);
> + old_payload = drm_atomic_get_mst_payload_state(old_mst_state,
> mstc->port);
>
> // TODO: Figure out if we want to do a better job of handling VCPI
> allocation failures here?
> if (msto->disabled) {
> - drm_dp_remove_payload(mgr, mst_state, payload, payload);
> + drm_dp_remove_payload(mgr, mst_state, old_payload, payload);
>
> nvif_outp_dp_mst_vcpi(>outp->outp,
> msto->head->base.index, 0, 0, 0, 0);
> } else {
> --
> 2.40.1
>
Re: [PATCH] drm/panel: move some dsi commands from unprepare to disable
[added Dmitry to Cc, since he suggested doing this in [1]]
On Tue, Jun 13, 2023 at 12:36:52AM +0100, Caleb Connolly wrote:
> The commit 007ac0262b0d ("drm/msm/dsi: switch to DRM_PANEL_BRIDGE")
> breaks panels which send DSI commands in their .unprepare callbacks.
> Migrate to using .disable for that for some SDM845 panels.
>
> Co-developed-by: Joel Selvaraj
> Signed-off-by: Joel Selvaraj
> Signed-off-by: Caleb Connolly
> ---
> drivers/gpu/drm/panel/panel-ebbg-ft8719.c | 18 +++---
> drivers/gpu/drm/panel/panel-novatek-nt36672a.c | 11 ++-
> drivers/gpu/drm/panel/panel-visionox-rm69299.c | 11 ++-
> 3 files changed, 27 insertions(+), 13 deletions(-)
After Dmitry's description in [1] it's still not quite clear to me if
the MSM DSI driver behaves wrong here (perhaps just "differently"?) or
if most of the panel drivers have this set up wrong.
This patch suggests that panel drivers shouldn't send any DSI commands
in .unprepare(). If this is really the case I think this change should
be applied to all panel drivers, not just the ones that happen to be
used with SDM845 devices. There are several others that also send DSI
commands in .unprepare().
I'm still quite confused about what exactly is supposed to be in
(un)prepare and what in enable/disable. I've seen some related
discussion every now and then but it's still quite inconsistent across
different panel drivers... Can someone clarify this?
Thanks!
Stephan
[1]:
https://lore.kernel.org/linux-arm-msm/CAA8EJpq_9iC1rkiZVom28Kv_B3QLd4pBgFObxBfSpJ+Xh=m...@mail.gmail.com/
Re: [PATCH] dt-bindings: display: Add missing property types
On Tue, Jun 13, 2023 at 02:11:14PM -0600, Rob Herring wrote: > A couple of display bridge properties are missing a type definition. Add > the types to them. > > Signed-off-by: Rob Herring Reviewed-by: Conor Dooley Cheers, Conor. signature.asc Description: PGP signature
[PATCH] drm/nouveau/kms/nv50-: Fix drm_dp_remove_payload() invocation
We changed the semantics for this in:
e761cc20946a ("drm/display/dp_mst: Handle old/new payload states in
drm_dp_remove_payload()")
But I totally forgot to update this properly in nouveau. So, let's do that.
Signed-off-by: Lyude Paul
---
drivers/gpu/drm/nouveau/dispnv50/disp.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c
b/drivers/gpu/drm/nouveau/dispnv50/disp.c
index 5bb777ff13130..1637e08b548c2 100644
--- a/drivers/gpu/drm/nouveau/dispnv50/disp.c
+++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c
@@ -909,15 +909,19 @@ nv50_msto_prepare(struct drm_atomic_state *state,
struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
struct nv50_mstc *mstc = msto->mstc;
struct nv50_mstm *mstm = mstc->mstm;
- struct drm_dp_mst_atomic_payload *payload;
+ struct drm_dp_mst_topology_state *old_mst_state;
+ struct drm_dp_mst_atomic_payload *payload, *old_payload;
NV_ATOMIC(drm, "%s: msto prepare\n", msto->encoder.name);
+ old_mst_state = drm_atomic_get_old_mst_topology_state(state, mgr);
+
payload = drm_atomic_get_mst_payload_state(mst_state, mstc->port);
+ old_payload = drm_atomic_get_mst_payload_state(old_mst_state,
mstc->port);
// TODO: Figure out if we want to do a better job of handling VCPI
allocation failures here?
if (msto->disabled) {
- drm_dp_remove_payload(mgr, mst_state, payload, payload);
+ drm_dp_remove_payload(mgr, mst_state, old_payload, payload);
nvif_outp_dp_mst_vcpi(>outp->outp,
msto->head->base.index, 0, 0, 0, 0);
} else {
--
2.40.1
Re: [PATCH] dt-bindings: backlight: kinetic,ktz8866: Add missing type for "current-num-sinks"
On Tue, Jun 13, 2023 at 02:10:22PM -0600, Rob Herring wrote: > "current-num-sinks" is missing a type, add it. > > Signed-off-by: Rob Herring Reviewed-by: Conor Dooley Cheers, Conor. signature.asc Description: PGP signature
Re: [PATCH] nouveau_connector: add nv_encoder pointer check for NULL
Nice catch!
Reviewed-by: Lyude Paul
Will push upstream
On Fri, 2023-05-12 at 13:33 +0300, Natalia Petrova wrote:
> Pointer nv_encoder could be dereferenced at nouveau_connector.c
> in case it's equal to NULL by jumping to goto label.
> This patch adds a NULL-check to avoid it.
>
> Found by Linux Verification Center (linuxtesting.org) with SVACE.
>
> Fixes: 3195c5f9784a ("drm/nouveau: set encoder for lvds")
> Signed-off-by: Natalia Petrova
> ---
> drivers/gpu/drm/nouveau/nouveau_connector.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.c
> b/drivers/gpu/drm/nouveau/nouveau_connector.c
> index 43a9d1e1cf71..90ba6d0a9c80 100644
> --- a/drivers/gpu/drm/nouveau/nouveau_connector.c
> +++ b/drivers/gpu/drm/nouveau/nouveau_connector.c
> @@ -729,7 +729,8 @@ nouveau_connector_detect_lvds(struct drm_connector
> *connector, bool force)
> #endif
>
> nouveau_connector_set_edid(nv_connector, edid);
> - nouveau_connector_set_encoder(connector, nv_encoder);
> + if (nv_encoder)
> + nouveau_connector_set_encoder(connector, nv_encoder);
> return status;
> }
>
--
Cheers,
Lyude Paul (she/her)
Software Engineer at Red Hat
Re: [PATCH] drm/msm/dp: Drop aux devices together with DP controller
Hi Doug On 6/13/2023 12:33 PM, Doug Anderson wrote: Hi, On Mon, Jun 12, 2023 at 3:40 PM Dmitry Baryshkov wrote: On 13/06/2023 01:01, Bjorn Andersson wrote: Using devres to depopulate the aux bus made sure that upon a probe deferral the EDP panel device would be destroyed and recreated upon next attempt. But the struct device which the devres is tied to is the DPUs (drm_dev->dev), which may be happen after the DP controller is torn down. Indications of this can be seen in the commonly seen EDID-hexdump full of zeros in the log, or the occasional/rare KASAN fault where the panel's attempt to read the EDID information causes a use after free on DP resources. It's tempting to move the devres to the DP controller's struct device, but the resources used by the device(s) on the aux bus are explicitly torn down in the error path. I hoped that proper usage of of_dp_aux_populate_bus(), with the callback function being non-NULL would have solved at least this part. But it seems I'll never see this patch. Agreed. This has been pending for > 1 year now with no significant progress. Abhinav: Is there anything that can be done about this? Not following up on agreed-to cleanups in a timely manner doesn't set a good precedent. Next time the Qualcomm display wants to land something and promises to land a followup people will be less likely to believe them... Both QC and Google know there were other factors which delayed this last 3-4 months. But, I do not have any concrete justification to give you for the delays before that apart from perhaps other higher priority chrome and upstream bugs which kept cropping up. Hence, all I can offer is my apologies for the delay. After seeing this patch on the list, we have revived this effort now and re-assigned this within our team to take over from where that was left off. It will need some time to transition but this will see the end of the tunnel soon. Thanks Abhinav
Re: [PATCH] drm/nouveau/dp: check for NULL nv_connector->native_mode
Reviewed-by: Lyude Paul
Will push upstream in a bit
On Fri, 2023-05-12 at 14:15 +0300, Natalia Petrova wrote:
> Add checking for NULL before calling nouveau_connector_detect_depth() in
> nouveau_connector_get_modes() function because nv_connector->native_mode
> could be dereferenced there since connector pointer passed to
> nouveau_connector_detect_depth() and the same value of
> nv_connector->native_mode is used there.
>
> Found by Linux Verification Center (linuxtesting.org) with SVACE.
>
> Fixes: d4c2c99bdc83 ("drm/nouveau/dp: remove broken display depth function,
> use the improved one")
>
> Signed-off-by: Natalia Petrova
> ---
> drivers/gpu/drm/nouveau/nouveau_connector.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.c
> b/drivers/gpu/drm/nouveau/nouveau_connector.c
> index 086b66b60d91..5dbf025e6873 100644
> --- a/drivers/gpu/drm/nouveau/nouveau_connector.c
> +++ b/drivers/gpu/drm/nouveau/nouveau_connector.c
> @@ -966,7 +966,7 @@ nouveau_connector_get_modes(struct drm_connector
> *connector)
> /* Determine display colour depth for everything except LVDS now,
>* DP requires this before mode_valid() is called.
>*/
> - if (connector->connector_type != DRM_MODE_CONNECTOR_LVDS)
> + if (connector->connector_type != DRM_MODE_CONNECTOR_LVDS &&
> nv_connector->native_mode)
> nouveau_connector_detect_depth(connector);
>
> /* Find the native mode if this is a digital panel, if we didn't
> @@ -987,7 +987,7 @@ nouveau_connector_get_modes(struct drm_connector
> *connector)
>* "native" mode as some VBIOS tables require us to use the
>* pixel clock as part of the lookup...
>*/
> - if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)
> + if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS &&
> nv_connector->native_mode)
> nouveau_connector_detect_depth(connector);
>
> if (nv_encoder->dcb->type == DCB_OUTPUT_TV)
--
Cheers,
Lyude Paul (she/her)
Software Engineer at Red Hat
[PATCH] dt-bindings: display: Add missing property types
A couple of display bridge properties are missing a type definition. Add the types to them. Signed-off-by: Rob Herring --- .../devicetree/bindings/display/bridge/analogix,dp.yaml | 1 + .../devicetree/bindings/display/bridge/nxp,tda998x.yaml | 1 + 2 files changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/display/bridge/analogix,dp.yaml b/Documentation/devicetree/bindings/display/bridge/analogix,dp.yaml index c9b06885cc63..62f0521b0924 100644 --- a/Documentation/devicetree/bindings/display/bridge/analogix,dp.yaml +++ b/Documentation/devicetree/bindings/display/bridge/analogix,dp.yaml @@ -26,6 +26,7 @@ properties: const: dp force-hpd: +type: boolean description: Indicate driver need force hpd when hpd detect failed, this is used for some eDP screen which don not have a hpd signal. diff --git a/Documentation/devicetree/bindings/display/bridge/nxp,tda998x.yaml b/Documentation/devicetree/bindings/display/bridge/nxp,tda998x.yaml index c4bf54397473..21d995f29a1e 100644 --- a/Documentation/devicetree/bindings/display/bridge/nxp,tda998x.yaml +++ b/Documentation/devicetree/bindings/display/bridge/nxp,tda998x.yaml @@ -20,6 +20,7 @@ properties: maxItems: 1 video-ports: +$ref: /schemas/types.yaml#/definitions/uint32 default: 0x230145 maximum: 0xff description: -- 2.39.2
[PATCH] dt-bindings: backlight: kinetic, ktz8866: Add missing type for "current-num-sinks"
"current-num-sinks" is missing a type, add it. Signed-off-by: Rob Herring --- .../devicetree/bindings/leds/backlight/kinetic,ktz8866.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/leds/backlight/kinetic,ktz8866.yaml b/Documentation/devicetree/bindings/leds/backlight/kinetic,ktz8866.yaml index e1191453c2f0..11b6fc36183d 100644 --- a/Documentation/devicetree/bindings/leds/backlight/kinetic,ktz8866.yaml +++ b/Documentation/devicetree/bindings/leds/backlight/kinetic,ktz8866.yaml @@ -33,6 +33,7 @@ properties: current-num-sinks: description: number of the LED current sinks' channels. +$ref: /schemas/types.yaml#/definitions/uint32 enum: [1, 2, 3, 4, 5, 6] kinetic,current-ramp-delay-ms: -- 2.39.2
Re: [PATCH] drm/msm/dp: Drop aux devices together with DP controller
Hi,
On Mon, Jun 12, 2023 at 3:40 PM Dmitry Baryshkov
wrote:
>
> On 13/06/2023 01:01, Bjorn Andersson wrote:
> > Using devres to depopulate the aux bus made sure that upon a probe
> > deferral the EDP panel device would be destroyed and recreated upon next
> > attempt.
> >
> > But the struct device which the devres is tied to is the DPUs
> > (drm_dev->dev), which may be happen after the DP controller is torn
> > down.
> >
> > Indications of this can be seen in the commonly seen EDID-hexdump full
> > of zeros in the log, or the occasional/rare KASAN fault where the
> > panel's attempt to read the EDID information causes a use after free on
> > DP resources.
> >
> > It's tempting to move the devres to the DP controller's struct device,
> > but the resources used by the device(s) on the aux bus are explicitly
> > torn down in the error path.
>
> I hoped that proper usage of of_dp_aux_populate_bus(), with the callback
> function being non-NULL would have solved at least this part. But it
> seems I'll never see this patch.
Agreed. This has been pending for > 1 year now with no significant
progress. Abhinav: Is there anything that can be done about this? Not
following up on agreed-to cleanups in a timely manner doesn't set a
good precedent. Next time the Qualcomm display wants to land something
and promises to land a followup people will be less likely to believe
them...
> > The KASAN-reported use-after-free also
> > remains, as the DP aux "module" explicitly frees its devres-allocated
> > memory in this code path.
> >
> > As such, explicitly depopulate the aux bus in the error path, and in the
> > component unbind path, to avoid these issues.
> >
> > Fixes: 2b57f726611e ("drm/msm/dp: fix aux-bus EP lifetime")
> > Signed-off-by: Bjorn Andersson
>
> Reviewed-by: Dmitry Baryshkov
Reviewed-by: Douglas Anderson
RE: [PATCH v5 01/11] i2c: Enhance i2c_new_ancillary_device API
Hi Wolfram, > Subject: RE: [PATCH v5 01/11] i2c: Enhance i2c_new_ancillary_device API > > Hi Wolfram, > > Thanks for the feedback. > > > Subject: RE: [PATCH v5 01/11] i2c: Enhance i2c_new_ancillary_device > > API > > > > Hi Wolfram, > > > > Thanks for the feedback. > > > > > Subject: Re: [PATCH v5 01/11] i2c: Enhance i2c_new_ancillary_device > > > API > > > > > > Hi everyone, > > > > > > > Perhaps we should first think through what an ancillary device > > > > really is. My understanding is that it is used to talk to > > > > secondary addresses of a multi-address I2C slave device. > > > > > > As I mentioned somewhere before, this is not the case. Ancillary > > > devices are when one *driver* handles more than one address. > > > Everything else has been handled differently in the past (for all > > > the > > uses I am aware of). > > > > > > Yet, I have another idea which is so simple that I wonder if it > > > maybe has already been discussed so far? > > > > > > * have two regs in the bindings > > > > OK, it is inline with DT maintainers expectation as it is matching > > with real hw as single device node having two regs. > > > > > * use the second reg with i2c_new_client_device to instantiate the > > > RTC sibling. 'struct i2c_board_info', which is one parameter, should > > > have enough options to pass data, e.g it has a software_node. > > > > OK, I can see the below can be passed from PMIC to new client device. > > > > client->addr = info->addr; > > > > client->init_irq = info->irq; > > > > > > > > Should work or did I miss something here? > > > > I guess it will work. We instantiate appropriate device based On PMIC > > revision and slave address and IRQ resource passed through 'struct > > i2c_board_info' > > > > Will check this and update you. > > info.irq = irq; -->Irq fine > info.addr = addr; -->slave address fine > size = strscpy(info.type, name, sizeof(info.type)); -->instantiation based > on PMIC version fine. > > 1) How do we share clk details on instantiated device to find is it > connected to external crystal or external clock source? as we cannot pass > of_node between PMIC and "i2c_board_info" as it results in pinctrl > failure. info->platformdata and > Client->dev.platformdata to retrieve this info?? Or I2C instantiation based on actual oscillator bit value, ie, two i2c_device_id's with one for setting oscillator bit and another for clearing oscillator bit PMIC driver parses the clock details. Based on firmware version and clock, It instantiates either i2c_device_id with setting oscillator bit or clearing oscillator bit. Cheers, Biju
Re: [syzbot] kernel BUG in vmf_insert_pfn_prot
syzbot suspects this issue was fixed by commit: commit a5b44c4adb1699661d22e5152fb26885f30a2e4c Author: Thomas Zimmermann Date: Mon Mar 20 15:07:44 2023 + drm/fbdev-generic: Always use shadow buffering bisection log: https://syzkaller.appspot.com/x/bisect.txt?x=1025ee0728 start commit: 0326074ff465 Merge tag 'net-next-6.1' of git://git.kernel... git tree: upstream kernel config: https://syzkaller.appspot.com/x/.config?x=d323d85b1f8a4ed7 dashboard link: https://syzkaller.appspot.com/bug?extid=2d4f8693f438d2bd4bdb syz repro: https://syzkaller.appspot.com/x/repro.syz?x=14fd118288 C reproducer: https://syzkaller.appspot.com/x/repro.c?x=1756751488 If the result looks correct, please mark the issue as fixed by replying with: #syz fix: drm/fbdev-generic: Always use shadow buffering For information about bisection process see: https://goo.gl/tpsmEJ#bisection
[PATCH] drm/mediatek: Add valid modifier check
Add a check to mtk_drm_mode_fb_create() that rejects any modifier that is not the AFBC mode supported by MT8195's display overlays. Tested by booting ChromeOS and verifying the UI works, and by running the ChromeOS kms_addfb_basic binary, which has a test called "addfb25-bad-modifier" that attempts to create a framebuffer with the modifier DRM_FORMAT_MOD_INVALID and verifies the ADDFB2 ioctl returns EINVAL. Signed-off-by: Justin Green --- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index cd5b18ef7951..2096e8a794ad 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -51,6 +51,13 @@ mtk_drm_mode_fb_create(struct drm_device *dev, if (info->num_planes != 1) return ERR_PTR(-EINVAL); + if (cmd->modifier[0] && + cmd->modifier[0] != DRM_FORMAT_MOD_ARM_AFBC( + AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 | + AFBC_FORMAT_MOD_SPLIT | + AFBC_FORMAT_MOD_SPARSE)) + return ERR_PTR(-EINVAL); + return drm_gem_fb_create(dev, file, cmd); } -- 2.41.0.162.gfafddb0af9-goog
Re: [PATCH v6 4/6] drm/msm/dpu: Set DATA_COMPRESS on command mode for DCE/DSC 1.2
On 2023-06-09 15:57:16, Jessica Zhang wrote:
> Add a DPU INTF op to set the DCE_DATA_COMPRESS bit to enable the
> DCE/DSC 1.2 datapath
>
> Note: For now, this op is called for command mode encoders only. Changes to
> set DATA_COMPRESS for video mode encoders will be posted along with DSC
> v1.2 support for DP.
>
> Signed-off-by: Jessica Zhang
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 3 +++
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 13 +
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 3 +++
> 3 files changed, 19 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
> index 63ba0082b6ee..b856c6286c85 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
> @@ -67,6 +67,9 @@ static void _dpu_encoder_phys_cmd_update_intf_cfg(
> phys_enc->hw_intf->ops.bind_pingpong_blk(
> phys_enc->hw_intf,
> phys_enc->hw_pp->idx);
> +
> + if (intf_cfg.dsc != 0 && phys_enc->hw_intf->ops.enable_compression)
> + phys_enc->hw_intf->ops.enable_compression(phys_enc->hw_intf);
It was probably not necessary to drop this after adding dsc!=0:
Reviewed-by: Marijn Suijten
> }
>
> static void dpu_encoder_phys_cmd_pp_tx_done_irq(void *arg, int irq_idx)
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
> index 530f82e34c1e..5b0f6627e29b 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
> @@ -91,6 +91,7 @@
>
> #define INTF_CFG2_DATABUS_WIDEN BIT(0)
> #define INTF_CFG2_DATA_HCTL_EN BIT(4)
> +#define INTF_CFG2_DCE_DATA_COMPRESS BIT(12)
>
>
> static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx,
> @@ -512,6 +513,15 @@ static void dpu_hw_intf_disable_autorefresh(struct
> dpu_hw_intf *intf,
>
> }
>
> +static void dpu_hw_intf_enable_compression(struct dpu_hw_intf *ctx)
> +{
> + u32 intf_cfg2 = DPU_REG_READ(>hw, INTF_CONFIG2);
> +
> + intf_cfg2 |= INTF_CFG2_DCE_DATA_COMPRESS;
> +
> + DPU_REG_WRITE(>hw, INTF_CONFIG2, intf_cfg2);
> +}
> +
> static void _setup_intf_ops(struct dpu_hw_intf_ops *ops,
> unsigned long cap)
> {
> @@ -532,6 +542,9 @@ static void _setup_intf_ops(struct dpu_hw_intf_ops *ops,
> ops->vsync_sel = dpu_hw_intf_vsync_sel;
> ops->disable_autorefresh = dpu_hw_intf_disable_autorefresh;
> }
> +
> + if (cap & BIT(DPU_INTF_DATA_COMPRESS))
> + ops->enable_compression = dpu_hw_intf_enable_compression;
> }
>
> struct dpu_hw_intf *dpu_hw_intf_init(const struct dpu_intf_cfg *cfg,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
> index 33895eca1211..99e21c4137f9 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
> @@ -70,6 +70,7 @@ struct intf_status {
> * @get_autorefresh:Retrieve autorefresh config from hardware
> * Return: 0 on success, -ETIMEDOUT on timeout
> * @vsync_sel: Select vsync signal for tear-effect
> configuration
> + * @enable_compression: Enable data compression
> */
> struct dpu_hw_intf_ops {
> void (*setup_timing_gen)(struct dpu_hw_intf *intf,
> @@ -106,6 +107,8 @@ struct dpu_hw_intf_ops {
>* Disable autorefresh if enabled
>*/
> void (*disable_autorefresh)(struct dpu_hw_intf *intf, uint32_t
> encoder_id, u16 vdisplay);
> +
> + void (*enable_compression)(struct dpu_hw_intf *intf);
> };
>
> struct dpu_hw_intf {
>
> --
> 2.40.1
>
Re: [PATCH v2] drm/bridge: ti-sn65dsi86: Fix auxiliary bus lifetime
Quoting Douglas Anderson (2023-06-13 06:58:13)
> Memory for the "struct device" for any given device isn't supposed to
> be released until the device's release() is called. This is important
> because someone might be holding a kobject reference to the "struct
> device" and might try to access one of its members even after any
> other cleanup/uninitialization has happened.
>
> Code analysis of ti-sn65dsi86 shows that this isn't quite right. When
> the code was written, it was believed that we could rely on the fact
> that the child devices would all be freed before the parent devices
> and thus we didn't need to worry about a release() function. While I
> still believe that the parent's "struct device" is guaranteed to
> outlive the child's "struct device" (because the child holds a kobject
> reference to the parent), the parent's "devm" allocated memory is a
> different story. That appears to be freed much earlier.
>
> Let's make this better for ti-sn65dsi86 by allocating each auxiliary
> with kzalloc and then free that memory in the release().
>
> Fixes: bf73537f411b ("drm/bridge: ti-sn65dsi86: Break GPIO and MIPI-to-eDP
> bridge into sub-drivers")
> Suggested-by: Stephen Boyd
> Signed-off-by: Douglas Anderson
> ---
Reviewed-by: Stephen Boyd
Re: [PATCH v3 00/17] Imagination Technologies PowerVR DRM driver
On 13/06/2023 16:47, Sarah Walker wrote: > This patch series adds the initial DRM driver for Imagination Technologies > PowerVR > GPUs, starting with those based on our Rogue architecture. It's worth pointing > out that this is a new driver, written from the ground up, rather than a > refactored version of our existing downstream driver (pvrsrvkm). > ... > > maple_tree: split up MA_STATE() > macro:https://lists.freedesktop.org/archives/dri-devel/2023-June/407927.html > drm: manager to keep track of GPUs VA mappings: > https://lists.freedesktop.org/archives/dri-devel/2023-June/407928.html > drm/sched: Convert drm scheduler to use a work queue rather than kthread: > https://lists.freedesktop.org/archives/dri-devel/2023-April/398458.html > drm/sched: Move schedule policy to scheduler / entity: > https://lists.freedesktop.org/archives/dri-devel/2023-April/398461.html > drm/sched: Add DRM_SCHED_POLICY_SINGLE_ENTITY scheduling policy: > https://lists.freedesktop.org/archives/dri-devel/2023-April/398460.html > drm/sched: Start run wq before TDR in drm_sched_start: > https://lists.freedesktop.org/archives/dri-devel/2023-April/398462.html > drm/sched: Submit job before starting TDR: > https://lists.freedesktop.org/archives/dri-devel/2023-April/398466.html > drm/sched: Add helper to set TDR timeout: > https://lists.freedesktop.org/archives/dri-devel/2023-April/398464.html > drm: fix drmm_mutex_init(): > https://lists.freedesktop.org/archives/dri-devel/2023-May/404863.html > drm/sched: Make sure we wait for all dependencies in kill_jobs_cb(): > https://lists.freedesktop.org/archives/dri-devel/2023-June/408901.html > drm/sched: Call drm_sched_fence_set_parent() from > drm_sched_fence_scheduled(): > https://lists.freedesktop.org/archives/dri-devel/2023-June/408904.html > > [1] https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15243 > [2] > https://gitlab.freedesktop.org/mesa/mesa/-/tree/main/src/imagination/vulkan > [3] https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15507 > > v3: > * Use drm_sched for scheduling > * Use GPU VA manager > * Use runtime PM > * Use drm_gem_shmem > * GPU watchdog and device loss handling No changes in the bindings? So you decided to just ignore the comments? Sorry, that's not a good approach. Implement all the comments or respond to them. Best regards, Krzysztof
Re: [PATCH v3 02/17] dt-bindings: gpu: Add Imagination Technologies PowerVR GPU
On 13/06/2023 16:47, Sarah Walker wrote: > Add the device tree binding documentation for the Series AXE GPU used in > TI AM62 SoCs. > I don't see improvements. That's a NAK :( This is a friendly reminder during the review process. It seems my previous comments were not fully addressed. Maybe my feedback got lost between the quotes, maybe you just forgot to apply it. Please go back to the previous discussion and either implement all requested changes or keep discussing them. Thank you. Best regards, Krzysztof
Re: [PATCH 1/9] dt-bindings: mfd: Add bindings for SAM9X7 LCD controller
On Tue, Jun 13, 2023 at 08:17:13PM +0200, Krzysztof Kozlowski wrote: > On 13/06/2023 09:04, Manikandan Muralidharan wrote: > > Add new compatible string for the XLCD controller on SAM9X7 SoC. > > > > Signed-off-by: Manikandan Muralidharan > > --- > > Documentation/devicetree/bindings/mfd/atmel-hlcdc.txt | 1 + > > 1 file changed, 1 insertion(+) > > > > diff --git a/Documentation/devicetree/bindings/mfd/atmel-hlcdc.txt > > b/Documentation/devicetree/bindings/mfd/atmel-hlcdc.txt > > index 5f8880cc757e..7c77b6bf4adb 100644 > > --- a/Documentation/devicetree/bindings/mfd/atmel-hlcdc.txt > > +++ b/Documentation/devicetree/bindings/mfd/atmel-hlcdc.txt > > @@ -8,6 +8,7 @@ Required properties: > > "atmel,sama5d3-hlcdc" > > "atmel,sama5d4-hlcdc" > > "microchip,sam9x60-hlcdc" > > + "microchip,sam9x7-xlcdc" > > Google says sam9x7 is a series, not a SoC. Please add compatibles for > specific SoCs, not for series. We had this one a few weeks ago, see https://lore.kernel.org/all/add5e49e-8416-ba9f-819a-da944938c...@microchip.com/ and its parents. Outcome of that seemed to be that using "sam9x7" was fine. signature.asc Description: PGP signature
Re: [PATCH v8 1/2] dt-bindings: display: ti, am65x-dss: Add am625 dss compatible
On 08/06/2023 18:37, Aradhya Bhatia wrote: > The DSS controller on TI's AM625 SoC is an update from that on TI's > AM65X SoC. The former has an additional OLDI TX on its first video port > that helps output cloned video or WUXGA (1920x1200@60fps) resolution > video output over a dual-link mode to reduce the required OLDI clock > output. > > The second video port is same from AM65x DSS and it outputs DPI video > data. It can support 2K resolutions @ 60fps, independently. > Acked-by: Krzysztof Kozlowski Best regards, Krzysztof
Re: [PATCH 1/9] dt-bindings: mfd: Add bindings for SAM9X7 LCD controller
On Tue, Jun 13, 2023 at 12:34:18PM +0530, Manikandan Muralidharan wrote: > Add new compatible string for the XLCD controller on SAM9X7 SoC. You should probably indicate here why this is not compatible with the existing SoCs that are supported. To hazard a guess, it is the HLCDC IP (I forget the exact letters!)? If so, Acked-by: Conor Dooley Cheers, Conor. > > Signed-off-by: Manikandan Muralidharan > --- > Documentation/devicetree/bindings/mfd/atmel-hlcdc.txt | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/Documentation/devicetree/bindings/mfd/atmel-hlcdc.txt > b/Documentation/devicetree/bindings/mfd/atmel-hlcdc.txt > index 5f8880cc757e..7c77b6bf4adb 100644 > --- a/Documentation/devicetree/bindings/mfd/atmel-hlcdc.txt > +++ b/Documentation/devicetree/bindings/mfd/atmel-hlcdc.txt > @@ -8,6 +8,7 @@ Required properties: > "atmel,sama5d3-hlcdc" > "atmel,sama5d4-hlcdc" > "microchip,sam9x60-hlcdc" > + "microchip,sam9x7-xlcdc" > - reg: base address and size of the HLCDC device registers. > - clock-names: the name of the 3 clocks requested by the HLCDC device. > Should contain "periph_clk", "sys_clk" and "slow_clk". > -- > 2.25.1 > signature.asc Description: PGP signature
Re: [PATCH 1/9] dt-bindings: mfd: Add bindings for SAM9X7 LCD controller
On 13/06/2023 09:04, Manikandan Muralidharan wrote: > Add new compatible string for the XLCD controller on SAM9X7 SoC. > > Signed-off-by: Manikandan Muralidharan > --- > Documentation/devicetree/bindings/mfd/atmel-hlcdc.txt | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/Documentation/devicetree/bindings/mfd/atmel-hlcdc.txt > b/Documentation/devicetree/bindings/mfd/atmel-hlcdc.txt > index 5f8880cc757e..7c77b6bf4adb 100644 > --- a/Documentation/devicetree/bindings/mfd/atmel-hlcdc.txt > +++ b/Documentation/devicetree/bindings/mfd/atmel-hlcdc.txt > @@ -8,6 +8,7 @@ Required properties: > "atmel,sama5d3-hlcdc" > "atmel,sama5d4-hlcdc" > "microchip,sam9x60-hlcdc" > + "microchip,sam9x7-xlcdc" Google says sam9x7 is a series, not a SoC. Please add compatibles for specific SoCs, not for series. Best regards, Krzysztof
Re: [PATCH 6/9] drm: atmel_hlcdc: Add support for XLCDC in atmel LCD driver
On Tue, Jun 13, 2023 at 12:34:23PM +0530, Manikandan Muralidharan wrote: > - XLCDC in SAM9X7 has different sets of registers and additional > configuration bits when compared to previous HLCDC IP. Read/write > operation on the controller registers is now separated using the > XLCDC status flag. > - HEO scaling, window resampling, Alpha blending, YUV-to-RGB > conversion in XLCDC is derived and handled using additional > configuration bits and registers. > - Writing one to the Enable fields of each layer in LCD_ATTRE > is required to reflect the values set in Configuration, FBA, Enable > registers of each layer > > Signed-off-by: Manikandan Muralidharan > [hari.prasat...@microchip.com: update the attribute field for each layer] > Signed-off-by: Hari Prasath Gujulan Elango > [durai.manicka...@microchip.com: implement status flag to seprate register > update] These things inside [] look suspiciously like they should be co-developed-bys... signature.asc Description: PGP signature
Re: [PATCH 5/9] drm: atmel-hlcdc: add compatible string check for XLCDC and HLCDC
On Tue, Jun 13, 2023 at 12:34:22PM +0530, Manikandan Muralidharan wrote:
> From: Durai Manickam KR
>
> Add compatible string check to differentiate XLCDC and HLCDC code
> within the atmel-hlcdc driver files.
>
> Signed-off-by: Durai Manickam KR
> Signed-off-by: Manikandan Muralidharan
> ---
> drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c | 7 +++
> drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h | 1 +
> 2 files changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c
> b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c
> index d7ad828e9e8c..fbbd2592efc7 100644
> --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c
> +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c
> @@ -761,6 +761,13 @@ static int atmel_hlcdc_dc_load(struct drm_device *dev)
> if (!dc)
> return -ENOMEM;
>
> + /* SAM9X7 supports XLCDC */
> + if (!strcmp(match->compatible, "microchip,sam9x7-xlcdc"))
> + dc->is_xlcdc = true;
> + else
> + /* Other SoC's that supports HLCDC IP */
Should this be "Other SoCs that do not support HLCDC IP"?
> + dc->is_xlcdc = false;
> +
> dc->desc = match->data;
> dc->hlcdc = dev_get_drvdata(dev->dev->parent);
> dev->dev_private = dc;
> diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h
> b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h
> index aed1742b3665..804e4d476f2b 100644
> --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h
> +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h
> @@ -451,6 +451,7 @@ struct atmel_hlcdc_dc {
> u32 imr;
> struct drm_atomic_state *state;
> } suspend;
> + bool is_xlcdc;
> };
>
> extern struct atmel_hlcdc_formats atmel_hlcdc_plane_rgb_formats;
> --
> 2.25.1
>
signature.asc
Description: PGP signature
Re: [PATCH v3 05/17] drm/imagination: Get GPU resources
On 6/13/23 9:47 AM, Sarah Walker wrote:
Acquire clock, regulator and register resources, and enable/map as
appropriate.
Signed-off-by: Sarah Walker
---
drivers/gpu/drm/imagination/Makefile | 1 +
drivers/gpu/drm/imagination/pvr_device.c | 271 +++
drivers/gpu/drm/imagination/pvr_device.h | 214 ++
drivers/gpu/drm/imagination/pvr_drv.c| 11 +-
4 files changed, 496 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/imagination/pvr_device.c
diff --git a/drivers/gpu/drm/imagination/Makefile
b/drivers/gpu/drm/imagination/Makefile
index 62ccf0ccbd51..186f920d615b 100644
--- a/drivers/gpu/drm/imagination/Makefile
+++ b/drivers/gpu/drm/imagination/Makefile
@@ -4,6 +4,7 @@
subdir-ccflags-y := -I$(srctree)/$(src)
powervr-y := \
+ pvr_device.o \
pvr_drv.o \
obj-$(CONFIG_DRM_POWERVR) += powervr.o
diff --git a/drivers/gpu/drm/imagination/pvr_device.c
b/drivers/gpu/drm/imagination/pvr_device.c
new file mode 100644
index ..790c36cebec1
--- /dev/null
+++ b/drivers/gpu/drm/imagination/pvr_device.c
@@ -0,0 +1,271 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/* Copyright (c) 2022 Imagination Technologies Ltd. */
+
+#include "pvr_device.h"
+
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/**
+ * pvr_device_reg_init() - Initialize kernel access to a PowerVR device's
+ * control registers.
+ * @pvr_dev: Target PowerVR device.
+ *
+ * Sets struct pvr_device->regs.
+ *
+ * This method of mapping the device control registers into memory ensures that
+ * they are unmapped when the driver is detached (i.e. no explicit cleanup is
+ * required).
+ *
+ * Return:
+ * * 0 on success, or
+ * * Any error returned by devm_platform_ioremap_resource().
+ */
+static int
+pvr_device_reg_init(struct pvr_device *pvr_dev)
+{
+ struct drm_device *drm_dev = from_pvr_device(pvr_dev);
+ struct platform_device *plat_dev = to_platform_device(drm_dev->dev);
+ struct resource *regs_resource;
+ void __iomem *regs;
+ int err;
+
+ pvr_dev->regs_resource = NULL;
+ pvr_dev->regs = NULL;
+
+ regs = devm_platform_get_and_ioremap_resource(plat_dev, 0,
_resource);
+ if (IS_ERR(regs)) {
+ err = PTR_ERR(regs);
+ drm_err(drm_dev, "failed to ioremap gpu registers (err=%d)\n",
+ err);
+ return err;
+ }
+
+ pvr_dev->regs = regs;
+ pvr_dev->regs_resource = regs_resource;
+
+ return 0;
+}
+
+/**
+ * pvr_device_reg_fini() - Deinitialize kernel access to a PowerVR device's
+ * control registers.
+ * @pvr_dev: Target PowerVR device.
+ *
+ * This is essentially a no-op, since pvr_device_reg_init() already ensures
that
+ * struct pvr_device->regs is unmapped when the device is detached. This
+ * function just sets struct pvr_device->regs to %NULL.
+ */
+static __always_inline void
+pvr_device_reg_fini(struct pvr_device *pvr_dev)
+{
+ pvr_dev->regs = NULL;
This function isn't needed, kinda defeats the purpose of using devm_*()
if you go an manually have no-op functions to unwind it..
+}
+
+/**
+ * pvr_device_clk_init() - Initialize clocks required by a PowerVR device
+ * @pvr_dev: Target PowerVR device.
+ *
+ * Sets struct pvr_device->core_clk, struct pvr_device->sys_clk and
+ * struct pvr_device->mem_clk.
+ *
+ * Three clocks are required by the PowerVR device: core, sys and mem. On
+ * return, this function guarantees that the clocks are in one of the following
+ * states:
+ *
+ * * All successfully initialized,
+ * * Core errored, sys and mem uninitialized,
+ * * Core deinitialized, sys errored, mem uninitialized, or
+ * * Core and sys deinitialized, mem errored.
+ *
+ * Return:
+ * * 0 on success,
+ * * Any error returned by devm_clk_get(), or
+ * * Any error returned by clk_prepare_enable().
+ */
+static int pvr_device_clk_init(struct pvr_device *pvr_dev)
+{
+ struct drm_device *drm_dev = from_pvr_device(pvr_dev);
+ struct clk *core_clk;
+ struct clk *sys_clk;
+ struct clk *mem_clk;
+ int err;
+
+ pvr_dev->core_clk = NULL;
+ pvr_dev->sys_clk = NULL;
+ pvr_dev->mem_clk = NULL;
You could NULL these out on the error path, but is that even needed, looks
like if this functions fails we bail on the whole init where this is all
deallocated (plus NULL'd out again in that path).
+
+ core_clk = devm_clk_get(drm_dev->dev, "core");
+ if (IS_ERR(core_clk)) {
+ err = PTR_ERR(core_clk);
+ drm_err(drm_dev, "failed to get core clock (err=%d)\n", err);
+ goto err_out;
+ }
+
+ sys_clk = devm_clk_get(drm_dev->dev, "sys");
+ if (IS_ERR(sys_clk))
+ sys_clk = NULL;
+
+ mem_clk = devm_clk_get(drm_dev->dev, "mem");
+ if (IS_ERR(mem_clk))
+ mem_clk = NULL;
+
+ err =
Re: [PATCH v3] drm/bridge: ti-sn65dsi86: Avoid possible buffer overflow
Hi,
On Thu, Jun 8, 2023 at 8:15 AM Doug Anderson wrote:
>
> Hi,
>
> On Wed, Jun 7, 2023 at 6:25 PM Su Hui wrote:
> >
> > Smatch error:buffer overflow 'ti_sn_bridge_refclk_lut' 5 <= 5.
> >
> > Fixes: cea86c5bb442 ("drm/bridge: ti-sn65dsi86: Implement the pwm_chip")
> > Signed-off-by: Su Hui
> > ---
> > drivers/gpu/drm/bridge/ti-sn65dsi86.c | 4
> > 1 file changed, 4 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c
> > b/drivers/gpu/drm/bridge/ti-sn65dsi86.c
> > index 7a748785c545..4676cf2900df 100644
> > --- a/drivers/gpu/drm/bridge/ti-sn65dsi86.c
> > +++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c
> > @@ -298,6 +298,10 @@ static void ti_sn_bridge_set_refclk_freq(struct
> > ti_sn65dsi86 *pdata)
> > if (refclk_lut[i] == refclk_rate)
> > break;
> >
> > + /* avoid buffer overflow and "1" is the default rate in the
> > datasheet. */
> > + if (i >= refclk_lut_size)
> > + i = 1;
> > +
>
> Looks great now, thanks!
>
> Reviewed-by: Douglas Anderson
>
> Unless someone beats me to it or objects, I'll plan to commit this to
> drm-misc-fixes early next week.
Pushed to drm-misc-fixes:
95011f267c44 drm/bridge: ti-sn65dsi86: Avoid possible buffer overflow
RE: [PATCH v5 01/11] i2c: Enhance i2c_new_ancillary_device API
Hi Wolfram, Thanks for the feedback. > Subject: RE: [PATCH v5 01/11] i2c: Enhance i2c_new_ancillary_device API > > Hi Wolfram, > > Thanks for the feedback. > > > Subject: Re: [PATCH v5 01/11] i2c: Enhance i2c_new_ancillary_device > > API > > > > Hi everyone, > > > > > Perhaps we should first think through what an ancillary device > > > really is. My understanding is that it is used to talk to secondary > > > addresses of a multi-address I2C slave device. > > > > As I mentioned somewhere before, this is not the case. Ancillary > > devices are when one *driver* handles more than one address. > > Everything else has been handled differently in the past (for all the > uses I am aware of). > > > > Yet, I have another idea which is so simple that I wonder if it maybe > > has already been discussed so far? > > > > * have two regs in the bindings > > OK, it is inline with DT maintainers expectation as it is matching with > real hw as single device node having two regs. > > > * use the second reg with i2c_new_client_device to instantiate the > > RTC sibling. 'struct i2c_board_info', which is one parameter, should > > have enough options to pass data, e.g it has a software_node. > > OK, I can see the below can be passed from PMIC to new client device. > > client->addr = info->addr; > > client->init_irq = info->irq; > > > > > Should work or did I miss something here? > > I guess it will work. We instantiate appropriate device based On PMIC > revision and slave address and IRQ resource passed through 'struct > i2c_board_info' > > Will check this and update you. info.irq = irq; -->Irq fine info.addr = addr; -->slave address fine size = strscpy(info.type, name, sizeof(info.type)); -->instantiation based on PMIC version fine. 1) How do we share clk details on instantiated device to find is it connected to external crystal or external clock source? as we cannot pass of_node between PMIC and "i2c_board_info" as it results in pinctrl failure. info->platformdata and Client->dev.platformdata to retrieve this info?? Cheers, Biju
Re: [PATCH] udmabuf: revert 'Add support for mapping hugepages (v4)'
On 13.06.23 10:26, Kasireddy, Vivek wrote: Hi David, On 12.06.23 09:10, Kasireddy, Vivek wrote: Hi Mike, Hi Vivek, Sorry for the late reply; I just got back from vacation. If it is unsafe to directly use the subpages of a hugetlb page, then reverting this patch seems like the only option for addressing this issue immediately. So, this patch is Acked-by: Vivek Kasireddy As far as the use-case is concerned, there are two main users of the udmabuf driver: Qemu and CrosVM VMMs. However, it appears Qemu is the only one that uses hugetlb pages (when hugetlb=on is set) as the backing store for Guest (Linux, Android and Windows) system memory. The main goal is to share the pages associated with the Guest allocated framebuffer (FB) with the Host GPU driver and other components in a zero-copy way. To that end, the guest GPU driver (virtio-gpu) allocates 4k size pages (associated with the FB) and pins them before sharing the (guest) physical (or dma) addresses (and lengths) with Qemu. Qemu then translates the addresses into file offsets and shares these offsets with udmabuf. Is my understanding correct, that we can effectively long-term pin (worse than mlock) 64 MiB per UDMABUF_CREATE, allowing eventually !root The 64 MiB limit is the theoretical upper bound that we have not seen hit in practice. Typically, for a 1920x1080 resolution (commonly used in Guests), the size of the FB is ~8 MB (1920x1080x4). And, most modern Graphics compositors flip between two FBs. Okay, but users with privileges to open that file can just create as many as they want? I think I'll have to play with it. users ll /dev/udmabuf crw-rw 1 root kvm 10, 125 12. Jun 08:12 /dev/udmabuf to bypass there effective MEMLOCK limit, fragmenting physical memory and breaking swap? Right, it does not look like the mlock limits are honored. That should be added. Regarding the udmabuf_vm_fault(), I assume we're mapping pages we obtained from the memfd ourselves into a special VMA (mmap() of the mmap operation is really needed only if any component on the Host needs CPU access to the buffer. But in most scenarios, we try to ensure direct GPU access (h/w acceleration via gl) to these pages. udmabuf). I'm not sure how well shmem pages are prepared for getting mapped by someone else into an arbitrary VMA (page->index?). Most drm/gpu drivers use shmem pages as the backing store for FBs and other buffers and also provide mmap capability. What concerns do you see with this approach? Are these mmaping the pages the way udmabuf maps these pages (IOW, on-demand fault where we core-mm will adjust the mapcount etc)? Skimming over at shmem_read_mapping_page() users, I assume most of them use a VM_PFNMAP mapping (or don't mmap them at all), where we won't be messing with the struct page at all. (That might even allow you to mmap hugetlb sub-pages, because the struct page -- and mapcount -- will be ignored completely and not touched.) ... also, just imagine someone doing FALLOC_FL_PUNCH_HOLE / ftruncate() on the memfd. What's mapped into the memfd no longer corresponds to what's pinned / mapped into the VMA. IIUC, making use of the DMA_BUF_IOCTL_SYNC ioctl would help with any coherency issues: https://www.kernel.org/doc/html/v6.2/driver-api/dma-buf.html#c.dma_buf_sync Would it as of now? udmabuf_create() pulls the shmem pages out of the memfd, not sure how DMA_BUF_IOCTL_SYNC would help to update that whenever the pages inside the memfd would change (e.g., FALLOC_FL_PUNCH_HOLE + realloc). But that's most probably simply "not supported". Was linux-mm (and especially shmem maintainers, ccing Hugh) involved in the upstreaming of udmabuf? It does not appear so from the link below although other key lists were cc'd: https://patchwork.freedesktop.org/patch/246100/?series=39879=7 That's unfortunate :( -- Cheers, David / dhildenb
Re: [PATCH v3 02/17] dt-bindings: gpu: Add Imagination Technologies PowerVR GPU
On 6/13/23 9:47 AM, Sarah Walker wrote:
Add the device tree binding documentation for the Series AXE GPU used in
TI AM62 SoCs.
Signed-off-by: Sarah Walker
---
.../devicetree/bindings/gpu/img,powervr.yaml | 71 +++
MAINTAINERS | 7 ++
2 files changed, 78 insertions(+)
create mode 100644 Documentation/devicetree/bindings/gpu/img,powervr.yaml
diff --git a/Documentation/devicetree/bindings/gpu/img,powervr.yaml
b/Documentation/devicetree/bindings/gpu/img,powervr.yaml
new file mode 100644
index ..652343876d1c
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpu/img,powervr.yaml
@@ -0,0 +1,71 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (c) 2022 Imagination Technologies Ltd.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpu/img,powervr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Imagination Technologies PowerVR GPU
+
+maintainers:
+ - Sarah Walker
+
+properties:
+ compatible:
+oneOf:
oneOf shouldn't be needed, you can just do the enum followed by const.
+ - items:
+ - enum:
+ - ti,am62-gpu
+ - const: img,powervr-seriesaxe
+
+ reg:
+maxItems: 1
+
+ clocks:
+minItems: 1
+maxItems: 3
+
+ clock-names:
+items:
+ - const: core
+ - const: mem
+ - const: sys
+minItems: 1
+
+ interrupts:
+items:
+ - description: GPU interrupt
+
+ interrupt-names:
+items:
+ - const: gpu
+
+ power-domains:
+maxItems: 1
+
+ power-supply: true
Why do you need power-supply?
Andrew
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - interrupts
+ - interrupt-names
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+#include
+
+gpu: gpu@fd0 {
+compatible = "ti,am62-gpu", "img,powervr-seriesaxe";
+reg = <0x0fd0 0x2>;
+power-domains = <_pds 187>;
+clocks = <_clks 187 0>;
+clock-names = "core";
+interrupts = ;
+interrupt-names = "gpu";
+};
diff --git a/MAINTAINERS b/MAINTAINERS
index b344e1318ac3..a41517843a10 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -10084,6 +10084,13 @@ IMGTEC IR DECODER DRIVER
S:Orphan
F:drivers/media/rc/img-ir/
+IMGTEC POWERVR DRM DRIVER
+M: Frank Binns
+M: Sarah Walker
+M: Donald Robson
+S: Supported
+F: Documentation/devicetree/bindings/gpu/img,powervr.yaml
+
IMON SOUNDGRAPH USB IR RECEIVER
M:Sean Young
L:linux-me...@vger.kernel.org
[PATCH] drm/virtio: conditionally allocate virtio_gpu_fence
We don't want to create a fence for every command submission. It's
only necessary when userspace provides a waitable token for submission.
This could be:
1) bo_handles, to be used with VIRTGPU_WAIT
2) out_fence_fd, to be used with dma_fence apis
3) a ring_idx provided with VIRTGPU_CONTEXT_PARAM_POLL_RINGS_MASK
+ DRM event API
4) syncobjs in the future
The use case for just submitting a command to the host, and expecting
no response. For example, gfxstream has GFXSTREAM_CONTEXT_PING that
just wakes up the host side worker threads. There's also
CROSS_DOMAIN_CMD_SEND which just sends data to the Wayland server.
This prevents the need to signal the automatically created
virtio_gpu_fence.
Signed-off-by: Gurchetan Singh
---
drivers/gpu/drm/virtio/virtgpu_submit.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/virtio/virtgpu_submit.c
b/drivers/gpu/drm/virtio/virtgpu_submit.c
index cf3c04b16a7a..add106c06ab2 100644
--- a/drivers/gpu/drm/virtio/virtgpu_submit.c
+++ b/drivers/gpu/drm/virtio/virtgpu_submit.c
@@ -168,9 +168,13 @@ static int virtio_gpu_init_submit(struct virtio_gpu_submit
*submit,
memset(submit, 0, sizeof(*submit));
- out_fence = virtio_gpu_fence_alloc(vgdev, fence_ctx, ring_idx);
- if (!out_fence)
- return -ENOMEM;
+ if ((exbuf->flags & VIRTGPU_EXECBUF_FENCE_FD_OUT) ||
+ ((exbuf->flags & VIRTGPU_EXECBUF_RING_IDX) &&
+ (vfpriv->ring_idx_mask & BIT_ULL(ring_idx))) ||
+ exbuf->num_bo_handles)
+ out_fence = virtio_gpu_fence_alloc(vgdev, fence_ctx, ring_idx);
+ else
+ out_fence = NULL;
err = virtio_gpu_fence_event_create(dev, file, out_fence, ring_idx);
if (err) {
--
2.34.1
Re: [PATCH v14 1/2] drm: add kms driver for loongson display controller
On 2023/6/14 00:20, Sui Jingfeng wrote: We will remote this workaround at next version. remote -> remove
Re: [2/2] drm: Remove struct drm_driver.gem_prime_mmap
Wow, so many drivers get nuked!
On 2023/6/13 22:51, Thomas Zimmermann wrote:
All drivers initialize this field with drm_gem_prime_mmap(). Call
the function directly and remove the field. Simplifies the code and
resolves a long-standing TODO item.
Signed-off-by: Thomas Zimmermann
Reviewed-by: Alex Deucher
I have tested this patch briefly with drm/amdgpu(RX560), Running
glmark2, the rendered scene looks OK.
But single driver is self-sharing. I think I should test this more with
multiple video card.
---
Documentation/gpu/todo.rst | 9 -
drivers/accel/ivpu/ivpu_drv.c | 1 -
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 1 -
drivers/gpu/drm/drm_fbdev_dma.c | 6 +-
drivers/gpu/drm/drm_prime.c | 14 ++
drivers/gpu/drm/etnaviv/etnaviv_drv.c | 1 -
drivers/gpu/drm/exynos/exynos_drm_drv.c | 1 -
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c | 1 -
drivers/gpu/drm/lima/lima_drv.c | 1 -
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 1 -
drivers/gpu/drm/msm/msm_drv.c | 1 -
drivers/gpu/drm/msm/msm_drv.h | 1 -
drivers/gpu/drm/msm/msm_gem_prime.c | 5 -
drivers/gpu/drm/nouveau/nouveau_drm.c | 1 -
drivers/gpu/drm/panfrost/panfrost_drv.c | 1 -
drivers/gpu/drm/pl111/pl111_drv.c | 1 -
drivers/gpu/drm/radeon/radeon_drv.c | 1 -
drivers/gpu/drm/renesas/rcar-du/rcar_du_drv.c | 1 -
drivers/gpu/drm/rockchip/rockchip_drm_drv.c | 1 -
drivers/gpu/drm/v3d/v3d_drv.c | 1 -
drivers/gpu/drm/virtio/virtgpu_drv.c| 1 -
drivers/gpu/drm/xen/xen_drm_front.c | 1 -
include/drm/drm_drv.h | 14 --
include/drm/drm_gem_dma_helper.h| 6 ++
include/drm/drm_gem_shmem_helper.h | 1 -
include/drm/drm_gem_vram_helper.h | 1 -
26 files changed, 5 insertions(+), 69 deletions(-)
diff --git a/Documentation/gpu/todo.rst b/Documentation/gpu/todo.rst
index 68bdafa0284f5..ca1efad8c89c3 100644
--- a/Documentation/gpu/todo.rst
+++ b/Documentation/gpu/todo.rst
@@ -319,15 +319,6 @@ Contact: Daniel Vetter, Noralf Tronnes
Level: Advanced
-struct drm_gem_object_funcs
-
-GEM objects can now have a function table instead of having the callbacks on
the
-DRM driver struct. This is now the preferred way. Callbacks in drivers have
been
-converted, except for struct drm_driver.gem_prime_mmap.
-
-Level: Intermediate
-
connector register/unregister fixes
---
diff --git a/drivers/accel/ivpu/ivpu_drv.c b/drivers/accel/ivpu/ivpu_drv.c
index 2df7643b843d5..9f2b9fdcc5498 100644
--- a/drivers/accel/ivpu/ivpu_drv.c
+++ b/drivers/accel/ivpu/ivpu_drv.c
@@ -376,7 +376,6 @@ static const struct drm_driver driver = {
.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
.gem_prime_import = ivpu_gem_prime_import,
- .gem_prime_mmap = drm_gem_prime_mmap,
.ioctls = ivpu_drm_ioctls,
.num_ioctls = ARRAY_SIZE(ivpu_drm_ioctls),
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index c9a41c997c6c7..7681f79f462eb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -2809,7 +2809,6 @@ static const struct drm_driver amdgpu_kms_driver = {
.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
.gem_prime_import = amdgpu_gem_prime_import,
- .gem_prime_mmap = drm_gem_prime_mmap,
.name = DRIVER_NAME,
.desc = DRIVER_DESC,
diff --git a/drivers/gpu/drm/drm_fbdev_dma.c b/drivers/gpu/drm/drm_fbdev_dma.c
index d86773fa8ab00..8217f1ddc0075 100644
--- a/drivers/gpu/drm/drm_fbdev_dma.c
+++ b/drivers/gpu/drm/drm_fbdev_dma.c
@@ -54,12 +54,8 @@ static void drm_fbdev_dma_fb_destroy(struct fb_info *info)
static int drm_fbdev_dma_fb_mmap(struct fb_info *info, struct vm_area_struct
*vma)
{
struct drm_fb_helper *fb_helper = info->par;
- struct drm_device *dev = fb_helper->dev;
-
- if (drm_WARN_ON_ONCE(dev, !fb_helper->dev->driver->gem_prime_mmap))
- return -ENODEV;
- return fb_helper->dev->driver->gem_prime_mmap(fb_helper->buffer->gem, vma);
+ return drm_gem_prime_mmap(fb_helper->buffer->gem, vma);
}
static const struct fb_ops drm_fbdev_dma_fb_ops = {
diff --git a/drivers/gpu/drm/drm_prime.c b/drivers/gpu/drm/drm_prime.c
index d29dafce9bb0a..6bcf324ef81c9 100644
--- a/drivers/gpu/drm/drm_prime.c
+++ b/drivers/gpu/drm/drm_prime.c
@@ -715,8 +715,6 @@ EXPORT_SYMBOL(drm_gem_dmabuf_vunmap);
* the same codepath that is used for regular GEM buffer mapping on the DRM
fd.
*
Re: [PATCH drm-next v4 02/14] maple_tree: split up MA_STATE() macro
* Danilo Krummrich [230606 18:31]:
> Split up the MA_STATE() macro such that components using the maple tree
> can easily inherit from struct ma_state and build custom tree walk
> macros to hide their internals from users.
>
> Example:
>
> struct sample_iterator {
> struct ma_state mas;
> struct sample_mgr *mgr;
> };
>
> \#define SAMPLE_ITERATOR(name, __mgr, start) \
> struct sample_iterator name = { \
> .mas = MA_STATE_INIT(&(__mgr)->mt, start, 0), \
> .mgr = __mgr, \
> }
>
> \#define sample_iter_for_each_range(it__, entry__, end__) \
> mas_for_each(&(it__).mas, entry__, end__)
>
> --
>
> struct sample *sample;
> SAMPLE_ITERATOR(si, min);
>
> sample_iter_for_each_range(, sample, max) {
> frob(mgr, sample);
> }
>
> Signed-off-by: Danilo Krummrich
Reviewed-by: Liam R. Howlett
> ---
> include/linux/maple_tree.h | 7 +--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/include/linux/maple_tree.h b/include/linux/maple_tree.h
> index 1fadb5f5978b..87d55334f1c2 100644
> --- a/include/linux/maple_tree.h
> +++ b/include/linux/maple_tree.h
> @@ -423,8 +423,8 @@ struct ma_wr_state {
> #define MA_ERROR(err) \
> ((struct maple_enode *)(((unsigned long)err << 2) | 2UL))
>
> -#define MA_STATE(name, mt, first, end)
> \
> - struct ma_state name = {\
> +#define MA_STATE_INIT(mt, first, end)
> \
> + { \
> .tree = mt, \
> .index = first, \
> .last = end,\
> @@ -435,6 +435,9 @@ struct ma_wr_state {
> .mas_flags = 0, \
> }
>
> +#define MA_STATE(name, mt, first, end)
> \
> + struct ma_state name = MA_STATE_INIT(mt, first, end)
> +
> #define MA_WR_STATE(name, ma_state, wr_entry)
> \
> struct ma_wr_state name = { \
> .mas = ma_state,\
> --
> 2.40.1
>
>
Re: [PATCH v3 4/4] drm/stm: add an option to change FB bpp
On 6/13/23 17:26, Raphael Gallais-Pou wrote:
On 6/13/23 16:52, Michael Nazzareno Trimarchi wrote:
Hi
On Tue, Jun 13, 2023 at 4:41 PM Philippe CORNU
wrote:
On 6/9/23 08:20, Dario Binacchi wrote:
Boards that use the STM32F{4,7} series have limited amounts of RAM. The
added parameter allows users to size, within certain limits, the memory
footprint required by the framebuffer.
Signed-off-by: Dario Binacchi
---
Changes in v3:
- drop [4/6] dt-bindings: display: simple: add Rocktech RK043FN48H
Applied to https://anongit.freedesktop.org/git/drm/drm-misc.git
(drm-misc-next):
https://cgit.freedesktop.org/drm/drm-misc/commit/?id=c42a37a27c777d63961dd634a30f7c887949491a
- drop [5/6] drm/panel: simple: add support for Rocktech RK043FN48H panel
Applied to https://anongit.freedesktop.org/git/drm/drm-misc.git
(drm-misc-next)
https://cgit.freedesktop.org/drm/drm-misc/commit/?id=13cdd12a9f934158f4ec817cf048fcb4384aa9dc
drivers/gpu/drm/stm/drv.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/stm/drv.c b/drivers/gpu/drm/stm/drv.c
index 40df7d8c..65be2b442a6a 100644
--- a/drivers/gpu/drm/stm/drv.c
+++ b/drivers/gpu/drm/stm/drv.c
@@ -30,6 +30,11 @@
#define STM_MAX_FB_WIDTH2048
#define STM_MAX_FB_HEIGHT 2048 /* same as width to handle orientation */
+static uint stm_bpp = 16;
+
+MODULE_PARM_DESC(bpp, "bits-per-pixel (default: 16)");
+module_param_named(bpp, stm_bpp, uint, 0644);
+
static const struct drm_mode_config_funcs drv_mode_config_funcs = {
.fb_create = drm_gem_fb_create,
.atomic_check = drm_atomic_helper_check,
@@ -93,6 +98,7 @@ static int drv_load(struct drm_device *ddev)
ddev->mode_config.min_height = 0;
ddev->mode_config.max_width = STM_MAX_FB_WIDTH;
ddev->mode_config.max_height = STM_MAX_FB_HEIGHT;
+ ddev->mode_config.preferred_depth = stm_bpp;
ddev->mode_config.funcs = _mode_config_funcs;
ddev->mode_config.normalize_zpos = true;
@@ -203,7 +209,7 @@ static int stm_drm_platform_probe(struct platform_device
*pdev)
if (ret)
goto err_put;
- drm_fbdev_dma_setup(ddev, 16);
+ drm_fbdev_dma_setup(ddev, stm_bpp);
return 0;
Acked-by: Philippe Cornu
Many thanks,
Philippe :-)
According to the latest review on usb patchset: "Please do not add new
module parameters, this is not the 1990's anymore.
We have per-device settings everywhere, this makes that impossible.
Just use a DT value, if it is wrong, then fix the DT value! No need to
have the kernel override it, that's not what DT files are for."
I actually am conflicted about this idea, but I still think that here the best
option would be to put a device-tree property.
In which context here the module parameters could be used ? I think a module
parameter would be quite troublesome for userspace applications in that case.
Raphaël
I think it makes more sense to have dts parameters. Should maybe apply here too
Michael
Hi Raphaël & Michael,
Many thanks for your comments.
Dario's usage of this stm driver is STM32 MCUs (STM32F4 & F7...) where,
sometimes, old userland fbdev-based applications are used, and I imagine
it is maybe "easier" to use a module parameter (through the kernel
command line or whatever...) in these use cases (even if using dt is
always better and not that complex).
Moreover, as I did not find any drm drivers with drm_fbdev_dma_setup()
using a dt property "as example" (but always hard-coded value), then I
decided to not block this proposal :)
Thanks to your feedback, I am reconsidering my position. And sorry
Dario, hope you understand it will take more time for reviewing your patch.
Does anyone have an opinion to share on this point?
Many thanks,
Philippe :-)
Re: drm/etnaviv: disable MLCG and pulse eater on GPU reset
Hi, Lucas
I love your patch, perhaps something to improve:
The MLCG stand for "Module Level Clock Gating",
without reading the commit message, I guess there may have people don't
know its meaning.
There are still more thing in this patch can only be understand relay on
guessing... :-)
But drm/etnaviv drvier still works with this patch applied, so
On 2023/6/7 20:58, Lucas Stach wrote:
Module level clock gating and the pulse eater might interfere with
the GPU reset, as they both have the potential to stop the clock
and thus reset propagation to parts of the GPU.
Signed-off-by: Lucas Stach
Reviewed-by: Christian Gmeiner
Tested-by: Sui Jingfeng
---
I'm not aware of any cases where this would have been an issue, but
it is what the downstream driver does and fundametally seems like
the right thing to do.
---
drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
index de8c9894967c..41aab1aa330b 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
@@ -505,8 +505,19 @@ static int etnaviv_hw_reset(struct etnaviv_gpu *gpu)
timeout = jiffies + msecs_to_jiffies(1000);
while (time_is_after_jiffies(timeout)) {
- /* enable clock */
unsigned int fscale = 1 << (6 - gpu->freq_scale);
+ u32 pulse_eater = 0x01590880;
+
+ /* disable clock gating */
+ gpu_write_power(gpu, VIVS_PM_POWER_CONTROLS, 0x0);
+
+ /* disable pulse eater */
+ pulse_eater |= BIT(17);
+ gpu_write_power(gpu, VIVS_PM_PULSE_EATER, pulse_eater);
+ pulse_eater |= BIT(0);
+ gpu_write_power(gpu, VIVS_PM_PULSE_EATER, pulse_eater);
+
+ /* enable clock */
control = VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale);
etnaviv_gpu_load_clock(gpu, control);
--
Jingfeng
Re: [RFC] Plane color pipeline KMS uAPI
On 6/13/2023 4:23 AM, Pekka Paalanen wrote:
On Mon, 12 Jun 2023 12:56:57 -0400
Christopher Braga wrote:
On 6/12/2023 5:21 AM, Pekka Paalanen wrote:
On Fri, 9 Jun 2023 19:11:25 -0400
Christopher Braga wrote:
On 6/9/2023 12:30 PM, Simon Ser wrote:
Hi Christopher,
On Friday, June 9th, 2023 at 17:52, Christopher Braga
wrote:
The new COLOROP objects also expose a number of KMS properties. Each has a
type, a reference to the next COLOROP object in the linked list, and other
type-specific properties. Here is an example for a 1D LUT operation:
Color operation 42
├─ "type": enum {Bypass, 1D curve} = 1D curve
├─ "1d_curve_type": enum {LUT, sRGB, PQ, BT.709, HLG, …} = LUT
The options sRGB / PQ / BT.709 / HLG would select hard-coded 1D
curves? Will different hardware be allowed to expose a subset of these
enum values?
Yes. Only hardcoded LUTs supported by the HW are exposed as enum entries.
├─ "lut_size": immutable range = 4096
├─ "lut_data": blob
└─ "next": immutable color operation ID = 43
Some hardware has per channel 1D LUT values, while others use the same
LUT for all channels. We will definitely need to expose this in the
UAPI in some form.
Hm, I was assuming per-channel 1D LUTs here, just like the existing GAMMA_LUT/
DEGAMMA_LUT properties work. If some hardware can't support that, it'll need
to get exposed as another color operation block.
To configure this hardware block, user-space can fill a KMS blob with
4096 u32
entries, then set "lut_data" to the blob ID. Other color operation types
might
have different properties.
The bit-depth of the LUT is an important piece of information we should
include by default. Are we assuming that the DRM driver will always
reduce the input values to the resolution supported by the pipeline?
This could result in differences between the hardware behavior
and the shader behavior.
Additionally, some pipelines are floating point while others are fixed.
How would user space know if it needs to pack 32 bit integer values vs
32 bit float values?
Again, I'm deferring to the existing GAMMA_LUT/DEGAMMA_LUT. These use a common
definition of LUT blob (u16 elements) and it's up to the driver to convert.
Using a very precise format for the uAPI has the nice property of making the
uAPI much simpler to use. User-space sends high precision data and it's up to
drivers to map that to whatever the hardware accepts.
Conversion from a larger uint type to a smaller type sounds low effort,
however if a block works in a floating point space things are going to
get messy really quickly. If the block operates in FP16 space and the
interface is 16 bits we are good, but going from 32 bits to FP16 (such
as in the matrix case or 3DLUT) is less than ideal.
Hi Christopher,
are you thinking of precision loss, or the overhead of conversion?
Conversion from N-bit fixed point to N-bit floating-point is generally
lossy, too, and the other direction as well.
What exactly would be messy?
Overheard of conversion is the primary concern here. Having to extract
and / or calculate the significand + exponent components in the kernel
is burdensome and imo a task better suited for user space. This also has
to be done every blob set, meaning that if user space is re-using
pre-calculated blobs we would be repeating the same conversion
operations in kernel space unnecessarily.
What is burdensome in that calculation? I don't think you would need to
use any actual floating-point instructions. Logarithm for finding the
exponent is about finding the highest bit set in an integer and
everything is conveniently expressed in base-2. Finding significand is
just masking the integer based on the exponent.
Oh it definitely can be done, but I think this is just a difference of
opinion at this point. At the end of the day we will do it if we have
to, but it is just more optimal if a more agreeable common type is used.
Can you not cache the converted data, keyed by the DRM blob unique
identity vs. the KMS property it is attached to?
If the userspace compositor has N common transforms (ex: standard P3 ->
sRGB matrix), they would likely have N unique blobs. Obviously from the
kernel end we wouldn't want to cache the transform of every blob passed
down through the UAPI.
You can assume that userspace will not be re-creating DRM blobs without
a reason to believe the contents have changed. If the same blob is set
on the same property repeatedly, I would definitely not expect a driver
to convert the data again.
If the blob ID is unchanged there is no issue since caching the last
result is already common. As you say, blobs are immutable so no update
is needed. I'd question why the compositor keeps trying to send down the
same blob ID though.
If a driver does that, it seems like it
should be easy to avoid, though I'm no kernel dev. Even if the
conversion was just a memcpy, I would still posit it
Re: [PATCH v14 1/2] drm: add kms driver for loongson display controller
Hi,
On 2023/5/21 20:21, WANG Xuerui wrote:
+
+static int __init loongson_module_init(void)
+{
+ struct pci_dev *pdev = NULL;
+
+ if (video_firmware_drivers_only())
+ return -ENODEV;
+
+ /* Multiple video card workaround */
+ while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev))) {
+ if (pdev->vendor != PCI_VENDOR_ID_LOONGSON) {
+ pr_info("Discrete graphic card detected, abort\n");
Why is it that the iGPU cannot be used together with a dGPU? I can't
see why this is technically the case so some more explanations could
be beneficial to other readers and LoongArch devs.
We will remote this workaround at next version. we find some way to keep
multiple GPU driver co-exixt in the system. The reason we choose to
workaround is because it is both easy and effective to solve bugs.
After the dGPU is mounted on the motherboard,
1) the integrate register don't receive write or read access anymore.
sometime cause its can't receive vblank interrupt, causing vblank
timeout etc.
Have something to do with the PCI driver layer and/or PCI/vgaarb layer.
2) For ls7a1000, both the display controller and gpu is special,
when dGPU is mounted, we are multiple gpu system.
we should made the vgaarb works correct , this is relay on firmware
and efi support to be complete.
In the past, our system don't support firmware framebuffer even.
3) It need us we implement PRIME, for cross driver buffer sharing.
loongson display don't has scatter-gather able DMA. Can't access
non physical contiguous GTT buffer.
We can only expect
1) the CPU do the copy.
2) DC driver export dumb buffer, and GPU driver import this buffer,
and resolve the tiled buffer to the linear.
3) shared buffer has to pinned at GTT
4) Using space X server also has bug for parser the PCI device on
complex patch.
5) Even on X86, there are motherboard vendor choose to black the iGPU
when the dGPU is mounted.
It perhaps better black the iGPU at firmware layer.
But our firmware engineer don't know about this for a very long time.
But as its already as is, we will try to improve this at the next version.
--
Jingfeng
RE: [PATCH v5 01/11] i2c: Enhance i2c_new_ancillary_device API
Hi Geert, Thanks for the feedback. > Subject: Re: [PATCH v5 01/11] i2c: Enhance i2c_new_ancillary_device API > > Hi Biju, > > On Tue, Jun 13, 2023 at 12:45 PM Biju Das > wrote: > > > Subject: Re: [PATCH v5 01/11] i2c: Enhance i2c_new_ancillary_device > > > API On Mon, Jun 12, 2023 at 10:43 PM Wolfram Sang > wrote: > > > > > Perhaps we should first think through what an ancillary device > > > > > really is. My understanding is that it is used to talk to > > > > > secondary addresses of a multi-address I2C slave device. > > > > > > > > As I mentioned somewhere before, this is not the case. Ancillary > > > > devices are when one *driver* handles more than one address. > > > > Everything else has been handled differently in the past (for all > > > > the > > > uses I am aware of). > > > > > > > > Yet, I have another idea which is so simple that I wonder if it > > > > maybe has already been discussed so far? > > > > > > > > * have two regs in the bindings > > > > * use the second reg with i2c_new_client_device to instantiate the > > > > RTC sibling. 'struct i2c_board_info', which is one parameter, > should > > > > have enough options to pass data, e.g it has a software_node. > > > > > > > > Should work or did I miss something here? > > > > > > That should work, mostly (i2c_new_dummy_device() also calls > > > i2c_new_client_device()). And as i2c_board_info has an of_node > > > member (something I had missed before!), the new I2C device can > > > access the clocks in the DT node using the standard way. > > > > Looks like, I cannot assign of_node member like below as it results in > > pinctrl failure[1] during device bind. > > > > info.of_node = client->dev.of_node; > > > > [1] > > pinctrl-rzg2l 1103.pinctrl: pin P43_0 already requested by 3-0012; > > cannot claim for 3-006f pinctrl-rzg2l 1103.pinctrl: pin-344 > > (3-006f) status -22 pinctrl-rzg2l 1103.pinctrl: could not request > > pin 344 (P43_0) from group pmic on device pinctrl-rzg2l > > raa215300 3-006f: Error applying setting, reverse things back > > Where do you have a reference to pin P43_0 in your DT? The reference to pin P43_0 is added in the PMIC node. I have done modification on my board to test PMIC INT# on RZ/G2L SMARC EVK by wiring R83 on SoM module and PMOD0 PIN7. > The last versions you posted did not have any pinctrl properties? By default, PMIC_INT# is not populated RZ/G2L SMARC EVK, so I haven't added Support for PMIC_INT# for the patches posted till date. Yesterday I checked with HW people, is there a way to enable PMIC_INT# and they told me to do the above HW modification. Today I found this issue, with this modified HW and PMIC INT# enabled on the DT, while assigning of_node of PMIC with info.of_node. It is just a coincidence. Cheers, Biju
Re: [PATCH v2 00/10] drm/panel and i2c-hid: Allow panels and touchscreens to power sequence together
Hi,
On Tue, Jun 13, 2023 at 5:06 AM Maxime Ripard wrote:
>
> > > What I'm trying to say is: could we just make it work by passing a bunch
> > > of platform_data, 2-3 callbacks and a device registration from the panel
> > > driver directly?
> >
> > I think I'm still confused about what you're proposing. Sorry! :( Let
> > me try rephrasing why I'm confused and perhaps we can get on the same
> > page. :-)
> >
> > First, I guess I'm confused about how you have one of these devices
> > "register" the other device.
> >
> > I can understand how one device might "register" its sub-devices in
> > the MFD case. To make it concrete, we can look at a PMIC like
> > max77686.c. The parent MFD device gets probed and then it's in charge
> > of creating all of its sub-devices. These sub-devices are intimately
> > tied to one another. They have shared data structures and can
> > coordinate power sequencing and whatnot. All good.
>
> We don't necessarily need to use MFD, but yeah, we could just register a
> device for the i2c-hid driver to probe from (using
> i2c_new_client_device?)
I think this can work for devices where the panel and touchscreen are
truly integrated where the panel driver knows enough about the related
touchscreen to fully describe and instantiate it. It doesn't work
quite as well for cases where the power and reset lines are shared
just because of what a given board designer did. To handle that, each
panel driver would need to get enough DT properties added to it so
that it could fully describe any arbitrary touchscreen, right?
Let's think about the generic panel-edp driver. This driver runs the
panel on many sc7180-trogdor laptops, including coachz, lazor, and
pompom. All three of those boards have a shared power rail for the
touchscreen and panel. If you look at "sc7180-trogdor-coachz.dtsi",
you can see the touchscreen currently looks like this:
ap_ts: touchscreen@5d {
compatible = "goodix,gt7375p";
reg = <0x5d>;
pinctrl-names = "default";
pinctrl-0 = <_int_l>, <_reset_l>;
interrupt-parent = <>;
interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = < 8 GPIO_ACTIVE_LOW>;
vdd-supply = <_ts>;
};
In "sc7180-trogdor-lazor.dtsi" we have:
ap_ts: touchscreen@10 {
compatible = "hid-over-i2c";
reg = <0x10>;
pinctrl-names = "default";
pinctrl-0 = <_int_l>, <_reset_l>;
interrupt-parent = <>;
interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
post-power-on-delay-ms = <20>;
hid-descr-addr = <0x0001>;
vdd-supply = <_ts>;
};
In both cases "pp3300_ts" is simply another name for "pp3300_dx_edp"
So I think to do what you propose, we need to add this information to
the panel-edp DT node so that it could dynamically construct the i2c
device for the touchscreen:
a) Which touchscreen is actually connected (generic hid-over-i2c,
goodix, ...). I guess this would be a "compatible" string?
b) Which i2c bus that device is hooked up to.
c) Which i2c address that device is hooked up to.
d) What the touchscreen interrupt GPIO is.
e) Possibly what the "hid-descr-addr" for the touchscreen is.
f) Any extra timing information needed to be passed to the touchscreen
driver, like "post-power-on-delay-ms"
The "pinctrl" stuff would be easy to subsume into the panel's DT node,
at least. ...and, in this case, we could skip the "vdd-supply" since
the panel and eDP are sharing power rails (which is what got us into
this situation). ...but, the above is still a lot. At this point, it
would make sense to have a sub-node under the panel to describe it,
which we could do but it starts to feel weird. We'd essentially be
describing an i2c device but not under the i2c controller it belongs
to.
I guess I'd also say that the above design also need additional code
if/when someone had a touchscreen that used a different communication
method, like SPI.
So I guess the tl;dr of all the above is that I think it could all work if:
1. We described the touchscreen in a sub-node of the panel.
2. We added a property to the panel saying what the true parent of the
touchscreen was (an I2C controller, a SPI controller, ...) and what
type of controller it was ("SPI" vs "I2C").
3. We added some generic helpers that panels could call that would
understand how to instantiate the touchscreen under the appropriate
controller.
4. From there, we added a new private / generic API between panels and
touchscreens letting them know that the panel was turning on/off.
That seems much more complex to me, though. It also seems like an
awkward way to describe it in DT.
> > In any case, is there any chance that we're in violent agreement
>
> Is it even violent? Sorry if it came across that way, it's really isn't
> on my end.
Sorry, maybe a poor choice of words on my end. I've heard that term
thrown about when two people spend a lot of time discussing something
/ trying to persuade the other person only to find out in the end that
they were both on the same side of the issue. ;-)
> > and that if you
Re: [PATCH] drm/msm/dpu: Configure DP INTF/PHY selector
On Tue, Jun 13, 2023 at 01:31:40AM +0300, Dmitry Baryshkov wrote:
> On 13/06/2023 01:10, Bjorn Andersson wrote:
> > From: Bjorn Andersson
> >
> > Some platforms provides a mechanism for configuring the mapping between
> > (one or two) DisplayPort intfs and their PHYs.
> >
> > In particular SC8180X provides this functionality, without a default
> > configuration, resulting in no connection between its two external
> > DisplayPort controllers and any PHYs.
> >
> > The change implements the logic for optionally configuring which phy
> > each of the intfs should be connected to, provides a new entry in the
> > DPU catalog for specifying how many intfs to configure and marks the
> > SC8180X DPU to program 2 entries.
> >
> > For now the request is simply to program the mapping 1:1, any support
> > for alternative mappings is left until the use case arrise.
> >
> > Note that e.g. msm-4.14 unconditionally maps intf 0 to phy 0 on all
> > rlatforms, so perhaps this is needed in order to get DisplayPort working
> > on some other platforms as well.
> >
> > Signed-off-by: Bjorn Andersson
> > Signed-off-by: Bjorn Andersson
> > ---
> > .../msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 1 +
> > .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h| 2 ++
> > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c| 23 +++
> > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h| 8 +++
> > drivers/gpu/drm/msm/disp/dpu1/dpu_hwio.h | 1 +
> > drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 10
> > 6 files changed, 45 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> > b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> > index 8ed2b263c5ea..9da952692a69 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> > @@ -19,6 +19,7 @@ static const struct dpu_caps sc8180x_dpu_caps = {
> > .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
> > .max_hdeci_exp = MAX_HORZ_DECIMATION,
> > .max_vdeci_exp = MAX_VERT_DECIMATION,
> > + .num_dp_intf_sel = 2,
> > };
> > static const struct dpu_ubwc_cfg sc8180x_ubwc_cfg = {
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> > b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> > index ac4a9e73705c..4cb8d096d8ec 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> > @@ -357,6 +357,7 @@ struct dpu_rotation_cfg {
> >* @pixel_ram_size size of latency hiding and de-tiling buffer in
> > bytes
> >* @max_hdeci_exp max horizontal decimation supported (max is
> > 2^value)
> >* @max_vdeci_exp max vertical decimation supported (max is 2^value)
> > + * @num_dp_intf_selnumber of DP intfs to configure PHY selection for
> >*/
> > struct dpu_caps {
> > u32 max_mixer_width;
> > @@ -371,6 +372,7 @@ struct dpu_caps {
> > u32 pixel_ram_size;
> > u32 max_hdeci_exp;
> > u32 max_vdeci_exp;
> > + u32 num_dp_intf_sel;
> > };
> > /**
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
> > b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
> > index 963bdb5e0252..5afa99cb148c 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
> > @@ -250,6 +250,27 @@ static void dpu_hw_intf_audio_select(struct dpu_hw_mdp
> > *mdp)
> > DPU_REG_WRITE(c, HDMI_DP_CORE_SELECT, 0x1);
> > }
> > +static void dpu_hw_dp_phy_intf_sel(struct dpu_hw_mdp *mdp, unsigned int
> > *phys,
> > + unsigned int num_intfs)
> > +{
> > + struct dpu_hw_blk_reg_map *c = >hw;
> > + unsigned int intf;
> > + u32 sel = 0;
> > +
> > + if (!num_intfs)
> > + return;
> > +
> > + for (intf = 0; intf < num_intfs; intf++) {
> > + /* Specify the PHY (1-indexed) for @intf */
> > + sel |= (phys[intf] + 1) << (intf * 3);
> > +
> > + /* Specify the @intf (1-indexed) of targeted PHY */
> > + sel |= (intf + 1) << (6 + phys[intf] * 3);
>
> From what I can see, phys[intf] is const. What about defining indexed masks
> instead?
>
intf is the loop variable. What am I missing?
> > + }
> > +
> > + DPU_REG_WRITE(c, DP_PHY_INTF_SEL, sel);
> > +}
> > +
> > static void _setup_mdp_ops(struct dpu_hw_mdp_ops *ops,
> > unsigned long cap)
> > {
> > @@ -264,6 +285,8 @@ static void _setup_mdp_ops(struct dpu_hw_mdp_ops *ops,
> > ops->get_safe_status = dpu_hw_get_safe_status;
> > + ops->dp_phy_intf_sel = dpu_hw_dp_phy_intf_sel;
>
> Should this be gated for DPU < 4.0? Or 5.0?
>
> > +
> > if (cap & BIT(DPU_MDP_AUDIO_SELECT))
> > ops->intf_audio_select = dpu_hw_intf_audio_select;
> > }
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h
> > b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h
> > index a1a9e44bed36..8446d74d59b0 100644
> > ---
Re: linux-next: Tree for Jun 13 (drivers/gpu/drm/i915/display/)
On 6/12/23 23:59, Stephen Rothwell wrote: > Hi all, > > Changes since 20230609: > In file included from : ./../drivers/gpu/drm/i915/display/intel_display_power.h:255:70: error: 'struct seq_file' declared inside parameter list will not be visible outside of this definition or declaration [-Werror] 255 | void intel_display_power_debug(struct drm_i915_private *i915, struct seq_file *m); | ^~~~ cc1: all warnings being treated as errors In file included from ./../drivers/gpu/drm/i915/display/intel_display_power_well.h:10, from : ./../drivers/gpu/drm/i915/display/intel_display_power.h:255:70: error: 'struct seq_file' declared inside parameter list will not be visible outside of this definition or declaration [-Werror] 255 | void intel_display_power_debug(struct drm_i915_private *i915, struct seq_file *m); | ^~~~ cc1: all warnings being treated as errors -- ~Randy
Re: [Intel-gfx] [PATCH] drm/i915/pxp/mtl: intel_pxp_init_hw needs runtime-pm inside pm-complete
On 6/1/2023 8:59 AM, Alan Previn wrote:
In the case of failed suspend flow or cases where the kernel does not go
into full suspend but goes from suspend_prepare back to resume_complete,
we get called for a pm_complete but without runtime_pm guaranteed.
Thus, ensure we take the runtime_pm when calling intel_pxp_init_hw
from within intel_pxp_resume_complete.
LGTM,
Reviewed-by: Vinay Belgaumkar
Signed-off-by: Alan Previn
---
drivers/gpu/drm/i915/pxp/intel_pxp_pm.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
index 1a04067f61fc..1d184dcd63c7 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
@@ -36,6 +36,8 @@ void intel_pxp_suspend(struct intel_pxp *pxp)
void intel_pxp_resume_complete(struct intel_pxp *pxp)
{
+ intel_wakeref_t wakeref;
+
if (!intel_pxp_is_enabled(pxp))
return;
@@ -48,7 +50,8 @@ void intel_pxp_resume_complete(struct intel_pxp *pxp)
if (!HAS_ENGINE(pxp->ctrl_gt, GSC0) && !pxp->pxp_component)
return;
- intel_pxp_init_hw(pxp);
+ with_intel_runtime_pm(>ctrl_gt->i915->runtime_pm, wakeref)
+ intel_pxp_init_hw(pxp);
}
void intel_pxp_runtime_suspend(struct intel_pxp *pxp)
base-commit: a66da4c33d8ede541aea9ba6d0d73b556a072d54
Re: [PATCH 2/2] drm: Remove struct drm_driver.gem_prime_mmap
On Tue, Jun 13, 2023 at 11:05 AM Thomas Zimmermann wrote:
>
> All drivers initialize this field with drm_gem_prime_mmap(). Call
> the function directly and remove the field. Simplifies the code and
> resolves a long-standing TODO item.
>
> Signed-off-by: Thomas Zimmermann
Series is:
Reviewed-by: Alex Deucher
> ---
> Documentation/gpu/todo.rst | 9 -
> drivers/accel/ivpu/ivpu_drv.c | 1 -
> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 1 -
> drivers/gpu/drm/drm_fbdev_dma.c | 6 +-
> drivers/gpu/drm/drm_prime.c | 14 ++
> drivers/gpu/drm/etnaviv/etnaviv_drv.c | 1 -
> drivers/gpu/drm/exynos/exynos_drm_drv.c | 1 -
> drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c | 1 -
> drivers/gpu/drm/lima/lima_drv.c | 1 -
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 1 -
> drivers/gpu/drm/msm/msm_drv.c | 1 -
> drivers/gpu/drm/msm/msm_drv.h | 1 -
> drivers/gpu/drm/msm/msm_gem_prime.c | 5 -
> drivers/gpu/drm/nouveau/nouveau_drm.c | 1 -
> drivers/gpu/drm/panfrost/panfrost_drv.c | 1 -
> drivers/gpu/drm/pl111/pl111_drv.c | 1 -
> drivers/gpu/drm/radeon/radeon_drv.c | 1 -
> drivers/gpu/drm/renesas/rcar-du/rcar_du_drv.c | 1 -
> drivers/gpu/drm/rockchip/rockchip_drm_drv.c | 1 -
> drivers/gpu/drm/v3d/v3d_drv.c | 1 -
> drivers/gpu/drm/virtio/virtgpu_drv.c| 1 -
> drivers/gpu/drm/xen/xen_drm_front.c | 1 -
> include/drm/drm_drv.h | 14 --
> include/drm/drm_gem_dma_helper.h| 6 ++
> include/drm/drm_gem_shmem_helper.h | 1 -
> include/drm/drm_gem_vram_helper.h | 1 -
> 26 files changed, 5 insertions(+), 69 deletions(-)
>
> diff --git a/Documentation/gpu/todo.rst b/Documentation/gpu/todo.rst
> index 68bdafa0284f5..ca1efad8c89c3 100644
> --- a/Documentation/gpu/todo.rst
> +++ b/Documentation/gpu/todo.rst
> @@ -319,15 +319,6 @@ Contact: Daniel Vetter, Noralf Tronnes
>
> Level: Advanced
>
> -struct drm_gem_object_funcs
>
> -
> -GEM objects can now have a function table instead of having the callbacks on
> the
> -DRM driver struct. This is now the preferred way. Callbacks in drivers have
> been
> -converted, except for struct drm_driver.gem_prime_mmap.
> -
> -Level: Intermediate
> -
> connector register/unregister fixes
> ---
>
> diff --git a/drivers/accel/ivpu/ivpu_drv.c b/drivers/accel/ivpu/ivpu_drv.c
> index 2df7643b843d5..9f2b9fdcc5498 100644
> --- a/drivers/accel/ivpu/ivpu_drv.c
> +++ b/drivers/accel/ivpu/ivpu_drv.c
> @@ -376,7 +376,6 @@ static const struct drm_driver driver = {
> .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
> .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
> .gem_prime_import = ivpu_gem_prime_import,
> - .gem_prime_mmap = drm_gem_prime_mmap,
>
> .ioctls = ivpu_drm_ioctls,
> .num_ioctls = ARRAY_SIZE(ivpu_drm_ioctls),
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> index c9a41c997c6c7..7681f79f462eb 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> @@ -2809,7 +2809,6 @@ static const struct drm_driver amdgpu_kms_driver = {
> .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
> .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
> .gem_prime_import = amdgpu_gem_prime_import,
> - .gem_prime_mmap = drm_gem_prime_mmap,
>
> .name = DRIVER_NAME,
> .desc = DRIVER_DESC,
> diff --git a/drivers/gpu/drm/drm_fbdev_dma.c b/drivers/gpu/drm/drm_fbdev_dma.c
> index d86773fa8ab00..8217f1ddc0075 100644
> --- a/drivers/gpu/drm/drm_fbdev_dma.c
> +++ b/drivers/gpu/drm/drm_fbdev_dma.c
> @@ -54,12 +54,8 @@ static void drm_fbdev_dma_fb_destroy(struct fb_info *info)
> static int drm_fbdev_dma_fb_mmap(struct fb_info *info, struct vm_area_struct
> *vma)
> {
> struct drm_fb_helper *fb_helper = info->par;
> - struct drm_device *dev = fb_helper->dev;
> -
> - if (drm_WARN_ON_ONCE(dev, !fb_helper->dev->driver->gem_prime_mmap))
> - return -ENODEV;
>
> - return fb_helper->dev->driver->gem_prime_mmap(fb_helper->buffer->gem,
> vma);
> + return drm_gem_prime_mmap(fb_helper->buffer->gem, vma);
> }
>
> static const struct fb_ops drm_fbdev_dma_fb_ops = {
> diff --git a/drivers/gpu/drm/drm_prime.c b/drivers/gpu/drm/drm_prime.c
> index d29dafce9bb0a..6bcf324ef81c9 100644
> --- a/drivers/gpu/drm/drm_prime.c
> +++ b/drivers/gpu/drm/drm_prime.c
> @@ -715,8 +715,6 @@ EXPORT_SYMBOL(drm_gem_dmabuf_vunmap);
> * the same codepath that is used for regular GEM buffer mapping on the DRM
> fd.
> * The fake GEM offset is added to vma->vm_pgoff
Re: [PATCH v3 4/4] drm/stm: add an option to change FB bpp
On 6/13/23 16:52, Michael Nazzareno Trimarchi wrote:
> Hi
>
> On Tue, Jun 13, 2023 at 4:41 PM Philippe CORNU
> wrote:
>>
>>
>> On 6/9/23 08:20, Dario Binacchi wrote:
>>> Boards that use the STM32F{4,7} series have limited amounts of RAM. The
>>> added parameter allows users to size, within certain limits, the memory
>>> footprint required by the framebuffer.
>>>
>>> Signed-off-by: Dario Binacchi
>>>
>>> ---
>>>
>>> Changes in v3:
>>> - drop [4/6] dt-bindings: display: simple: add Rocktech RK043FN48H
>>>Applied to https://anongit.freedesktop.org/git/drm/drm-misc.git
>>> (drm-misc-next):
>>>
>>> https://cgit.freedesktop.org/drm/drm-misc/commit/?id=c42a37a27c777d63961dd634a30f7c887949491a
>>> - drop [5/6] drm/panel: simple: add support for Rocktech RK043FN48H panel
>>>Applied to https://anongit.freedesktop.org/git/drm/drm-misc.git
>>> (drm-misc-next)
>>>
>>> https://cgit.freedesktop.org/drm/drm-misc/commit/?id=13cdd12a9f934158f4ec817cf048fcb4384aa9dc
>>>
>>> drivers/gpu/drm/stm/drv.c | 8 +++-
>>> 1 file changed, 7 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/gpu/drm/stm/drv.c b/drivers/gpu/drm/stm/drv.c
>>> index 40df7d8c..65be2b442a6a 100644
>>> --- a/drivers/gpu/drm/stm/drv.c
>>> +++ b/drivers/gpu/drm/stm/drv.c
>>> @@ -30,6 +30,11 @@
>>> #define STM_MAX_FB_WIDTH2048
>>> #define STM_MAX_FB_HEIGHT 2048 /* same as width to handle orientation */
>>>
>>> +static uint stm_bpp = 16;
>>> +
>>> +MODULE_PARM_DESC(bpp, "bits-per-pixel (default: 16)");
>>> +module_param_named(bpp, stm_bpp, uint, 0644);
>>> +
>>> static const struct drm_mode_config_funcs drv_mode_config_funcs = {
>>> .fb_create = drm_gem_fb_create,
>>> .atomic_check = drm_atomic_helper_check,
>>> @@ -93,6 +98,7 @@ static int drv_load(struct drm_device *ddev)
>>> ddev->mode_config.min_height = 0;
>>> ddev->mode_config.max_width = STM_MAX_FB_WIDTH;
>>> ddev->mode_config.max_height = STM_MAX_FB_HEIGHT;
>>> + ddev->mode_config.preferred_depth = stm_bpp;
>>> ddev->mode_config.funcs = _mode_config_funcs;
>>> ddev->mode_config.normalize_zpos = true;
>>>
>>> @@ -203,7 +209,7 @@ static int stm_drm_platform_probe(struct
>>> platform_device *pdev)
>>> if (ret)
>>> goto err_put;
>>>
>>> - drm_fbdev_dma_setup(ddev, 16);
>>> + drm_fbdev_dma_setup(ddev, stm_bpp);
>>>
>>> return 0;
>>>
>> Acked-by: Philippe Cornu
>> Many thanks,
>> Philippe :-)
>>
> According to the latest review on usb patchset: "Please do not add new
> module parameters, this is not the 1990's anymore.
> We have per-device settings everywhere, this makes that impossible.
> Just use a DT value, if it is wrong, then fix the DT value! No need to
> have the kernel override it, that's not what DT files are for."
I actually am conflicted about this idea, but I still think that here the best
option would be to put a device-tree property.
In which context here the module parameters could be used ? I think a module
parameter would be quite troublesome for userspace applications in that case.
Raphaël
>
> I think it makes more sense to have dts parameters. Should maybe apply here
> too
>
> Michael
[PATCH v3 14/17] drm/imagination: Implement job submission and scheduling
Implement job submission ioctl. Job scheduling is implemented using
drm_sched.
Jobs are submitted in a stream format. This is intended to allow the UAPI
data format to be independent of the actual FWIF structures in use, which
vary depending on the GPU in use.
The stream formats are documented at:
https://gitlab.freedesktop.org/mesa/mesa/-/blob/73fe6db819d951c02ce57eefcbd9b31b85900f33/src/imagination/csbgen/rogue_kmd_stream.xml
This patch depends on:
drm/sched: Convert drm scheduler to use a work queue rather than kthread:
https://lists.freedesktop.org/archives/dri-devel/2023-April/398458.html
drm/sched: Move schedule policy to scheduler / entity:
https://lists.freedesktop.org/archives/dri-devel/2023-April/398461.html
drm/sched: Add DRM_SCHED_POLICY_SINGLE_ENTITY scheduling policy:
https://lists.freedesktop.org/archives/dri-devel/2023-April/398460.html
drm/sched: Start run wq before TDR in drm_sched_start:
https://lists.freedesktop.org/archives/dri-devel/2023-April/398462.html
drm/sched: Submit job before starting TDR:
https://lists.freedesktop.org/archives/dri-devel/2023-April/398466.html
drm/sched: Add helper to set TDR timeout:
https://lists.freedesktop.org/archives/dri-devel/2023-April/398464.html
drm: fix drmm_mutex_init():
https://lists.freedesktop.org/archives/dri-devel/2023-May/404863.html
drm/sched: Make sure we wait for all dependencies in kill_jobs_cb():
https://lists.freedesktop.org/archives/dri-devel/2023-June/408901.html
drm/sched: Call drm_sched_fence_set_parent() from drm_sched_fence_scheduled():
https://lists.freedesktop.org/archives/dri-devel/2023-June/408904.html
Signed-off-by: Sarah Walker
---
drivers/gpu/drm/imagination/Makefile |2 +
drivers/gpu/drm/imagination/pvr_context.c | 127 +-
drivers/gpu/drm/imagination/pvr_context.h | 35 +
drivers/gpu/drm/imagination/pvr_device.c |4 +
drivers/gpu/drm/imagination/pvr_device.h | 46 +
drivers/gpu/drm/imagination/pvr_drv.c | 34 +-
drivers/gpu/drm/imagination/pvr_job.c | 834
drivers/gpu/drm/imagination/pvr_job.h | 147 ++
drivers/gpu/drm/imagination/pvr_power.c | 17 +
drivers/gpu/drm/imagination/pvr_queue.c | 1203 +
drivers/gpu/drm/imagination/pvr_queue.h | 157 +++
drivers/gpu/drm/imagination/pvr_stream.c |2 +-
drivers/gpu/drm/imagination/pvr_stream_defs.c | 226
13 files changed, 2827 insertions(+), 7 deletions(-)
create mode 100644 drivers/gpu/drm/imagination/pvr_job.c
create mode 100644 drivers/gpu/drm/imagination/pvr_job.h
create mode 100644 drivers/gpu/drm/imagination/pvr_queue.c
create mode 100644 drivers/gpu/drm/imagination/pvr_queue.h
diff --git a/drivers/gpu/drm/imagination/Makefile
b/drivers/gpu/drm/imagination/Makefile
index 786a7bf6c773..85cd0c0c70cd 100644
--- a/drivers/gpu/drm/imagination/Makefile
+++ b/drivers/gpu/drm/imagination/Makefile
@@ -18,7 +18,9 @@ powervr-y := \
pvr_fw_trace.o \
pvr_gem.o \
pvr_hwrt.o \
+ pvr_job.o \
pvr_power.o \
+ pvr_queue.o \
pvr_stream.o \
pvr_stream_defs.o \
pvr_vm.o \
diff --git a/drivers/gpu/drm/imagination/pvr_context.c
b/drivers/gpu/drm/imagination/pvr_context.c
index 809bc0e3..4a72be95faed 100644
--- a/drivers/gpu/drm/imagination/pvr_context.c
+++ b/drivers/gpu/drm/imagination/pvr_context.c
@@ -6,10 +6,12 @@
#include "pvr_device.h"
#include "pvr_drv.h"
#include "pvr_gem.h"
+#include "pvr_job.h"
#include "pvr_power.h"
#include "pvr_rogue_fwif.h"
#include "pvr_rogue_fwif_common.h"
#include "pvr_rogue_fwif_resetframework.h"
+#include "pvr_stream.h"
#include "pvr_stream_defs.h"
#include "pvr_vm.h"
@@ -159,6 +161,116 @@ static int init_fw_objs(struct pvr_context *ctx,
return -EINVAL;
}
+/**
+ * pvr_context_destroy_queues() - Destroy all queues attached to a context.
+ * @ctx: Context to destroy queues on.
+ *
+ * Should be called when the last reference to a context object is dropped.
+ * It releases all resources attached to the queues bound to this context.
+ */
+static void pvr_context_destroy_queues(struct pvr_context *ctx)
+{
+ switch (ctx->type) {
+ case DRM_PVR_CTX_TYPE_RENDER:
+ pvr_queue_destroy(ctx->queues.fragment);
+ pvr_queue_destroy(ctx->queues.geometry);
+ break;
+ case DRM_PVR_CTX_TYPE_COMPUTE:
+ pvr_queue_destroy(ctx->queues.compute);
+ break;
+ case DRM_PVR_CTX_TYPE_TRANSFER_FRAG:
+ pvr_queue_destroy(ctx->queues.transfer);
+ break;
+ }
+}
+
+/**
+ * pvr_context_create_queues() - Create all queues attached to a context.
+ * @ctx: Context to create queues on.
+ * @args: Context creation arguments passed by userspace.
+ * @fw_ctx_map: CPU mapping of the FW context object.
+ *
+ * Return:
+ * * 0 on success, or
+ * * A negative error code otherwise.
+ */
+static int pvr_context_create_queues(struct
[PATCH v3 17/17] arm64: dts: ti: k3-am62-main: Add GPU device node [DO NOT MERGE]
Add the Series AXE GPU node to the AM62 device tree.
Signed-off-by: Sarah Walker
---
arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi
b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi
index b3e4857bbbe4..ad13414acf18 100644
--- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi
@@ -892,4 +892,17 @@ mcasp2: audio-controller@2b2 {
power-domains = <_pds 192 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
};
+
+gpu: gpu@fd0 {
+compatible = "ti,am62-gpu", "img,powervr-seriesaxe";
+reg = <0 0x0fd0 0 0x2>;
+power-domains = <_pds 187 TI_SCI_PD_EXCLUSIVE>;
+clocks = <_clks 187 0>;
+clock-names = "core";
+interrupts = ;
+interrupt-names = "gpu";
+#cooling-cells = <2>;
+#cooling-min-level = <0>;
+#cooling-max-level = <3>;
+};
};
--
2.40.1
[PATCH v3 04/17] drm/imagination: Add skeleton PowerVR driver
This adds the basic skeleton of the driver. The driver registers
itself with DRM on probe. Ioctl handlers are currently implemented
as stubs.
Signed-off-by: Sarah Walker
---
MAINTAINERS | 1 +
drivers/gpu/drm/Kconfig | 2 +
drivers/gpu/drm/Makefile | 1 +
drivers/gpu/drm/imagination/Kconfig | 15 +
drivers/gpu/drm/imagination/Makefile | 9 +
drivers/gpu/drm/imagination/pvr_device.h | 169
drivers/gpu/drm/imagination/pvr_drv.c| 530 +++
drivers/gpu/drm/imagination/pvr_drv.h| 22 +
8 files changed, 749 insertions(+)
create mode 100644 drivers/gpu/drm/imagination/Kconfig
create mode 100644 drivers/gpu/drm/imagination/Makefile
create mode 100644 drivers/gpu/drm/imagination/pvr_device.h
create mode 100644 drivers/gpu/drm/imagination/pvr_drv.c
create mode 100644 drivers/gpu/drm/imagination/pvr_drv.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 3ad9de48a463..4a6107ec91cb 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -10090,6 +10090,7 @@ M: Sarah Walker
M: Donald Robson
S: Supported
F: Documentation/devicetree/bindings/gpu/img,powervr.yaml
+F: drivers/gpu/drm/imagination/
F: include/uapi/drm/pvr_drm.h
IMON SOUNDGRAPH USB IR RECEIVER
diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index bb2e48cc6cd6..dc3fb60eec6f 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -365,6 +365,8 @@ source "drivers/gpu/drm/solomon/Kconfig"
source "drivers/gpu/drm/sprd/Kconfig"
+source "drivers/gpu/drm/imagination/Kconfig"
+
config DRM_HYPERV
tristate "DRM Support for Hyper-V synthetic video device"
depends on DRM && PCI && MMU && HYPERV
diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
index ba1a4878fb55..a1418574ccc4 100644
--- a/drivers/gpu/drm/Makefile
+++ b/drivers/gpu/drm/Makefile
@@ -195,3 +195,4 @@ obj-y += gud/
obj-$(CONFIG_DRM_HYPERV) += hyperv/
obj-y += solomon/
obj-$(CONFIG_DRM_SPRD) += sprd/
+obj-$(CONFIG_DRM_POWERVR) += imagination/
diff --git a/drivers/gpu/drm/imagination/Kconfig
b/drivers/gpu/drm/imagination/Kconfig
new file mode 100644
index ..9cda99f66a8d
--- /dev/null
+++ b/drivers/gpu/drm/imagination/Kconfig
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0 OR MIT
+# Copyright (c) 2022 Imagination Technologies Ltd.
+
+config DRM_POWERVR
+ tristate "Imagination Technologies PowerVR Graphics"
+ depends on ARM64
+ depends on DRM
+ select DRM_GEM_SHMEM_HELPER
+ select DRM_SCHED
+ select FW_LOADER
+ help
+ Choose this option if you have a system that has an Imagination
+ Technologies PowerVR Rogue GPU.
+
+ If "M" is selected, the module will be called powervr.
diff --git a/drivers/gpu/drm/imagination/Makefile
b/drivers/gpu/drm/imagination/Makefile
new file mode 100644
index ..62ccf0ccbd51
--- /dev/null
+++ b/drivers/gpu/drm/imagination/Makefile
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0 OR MIT
+# Copyright (c) 2022 Imagination Technologies Ltd.
+
+subdir-ccflags-y := -I$(srctree)/$(src)
+
+powervr-y := \
+ pvr_drv.o \
+
+obj-$(CONFIG_DRM_POWERVR) += powervr.o
diff --git a/drivers/gpu/drm/imagination/pvr_device.h
b/drivers/gpu/drm/imagination/pvr_device.h
new file mode 100644
index ..3d2865d726b8
--- /dev/null
+++ b/drivers/gpu/drm/imagination/pvr_device.h
@@ -0,0 +1,169 @@
+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
+/* Copyright (c) 2022 Imagination Technologies Ltd. */
+
+#ifndef PVR_DEVICE_H
+#define PVR_DEVICE_H
+
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+/**
+ * struct pvr_device - powervr-specific wrapper for drm_device
+ */
+struct pvr_device {
+ /**
+* @base: The underlying drm_device.
+*
+* Do not access this member directly, instead call
+* from_pvr_device().
+*/
+ struct drm_device base;
+};
+
+/**
+ * struct pvr_file - powervr-specific data to be assigned to
+ * drm_file.driver_priv
+ */
+struct pvr_file {
+ /**
+* @file: A reference to the parent drm_file.
+*
+* Do not access this member directly, instead call from_pvr_file().
+*/
+ struct drm_file *file;
+
+ /**
+* @pvr_dev: A reference to the powervr-specific wrapper for the
+* associated device. Saves on repeated calls to
+* to_pvr_device().
+*/
+ struct pvr_device *pvr_dev;
+};
+
+static __always_inline struct drm_device *
+from_pvr_device(struct pvr_device *pvr_dev)
+{
+ return _dev->base;
+}
+
+static __always_inline struct pvr_device *
+to_pvr_device(struct drm_device *drm_dev)
+{
+ return container_of(drm_dev, struct pvr_device, base);
+}
+
+static __always_inline struct drm_file *
+from_pvr_file(struct pvr_file *pvr_file)
[PATCH v3 01/17] sizes.h: Add entries between 32G and 64T
From: Matt Coster Signed-off-by: Matt Coster --- include/linux/sizes.h | 9 + 1 file changed, 9 insertions(+) diff --git a/include/linux/sizes.h b/include/linux/sizes.h index 84aa448d8bb3..c3a00b967d18 100644 --- a/include/linux/sizes.h +++ b/include/linux/sizes.h @@ -47,8 +47,17 @@ #define SZ_8G _AC(0x2, ULL) #define SZ_16G _AC(0x4, ULL) #define SZ_32G _AC(0x8, ULL) +#define SZ_64G _AC(0x10, ULL) +#define SZ_128G_AC(0x20, ULL) +#define SZ_256G_AC(0x40, ULL) +#define SZ_512G_AC(0x80, ULL) #define SZ_1T _AC(0x100, ULL) +#define SZ_2T _AC(0x200, ULL) +#define SZ_4T _AC(0x400, ULL) +#define SZ_8T _AC(0x800, ULL) +#define SZ_16T _AC(0x1000, ULL) +#define SZ_32T _AC(0x2000, ULL) #define SZ_64T _AC(0x4000, ULL) #endif /* __LINUX_SIZES_H__ */ -- 2.40.1
[PATCH v3 12/17] drm/imagination: Implement free list and HWRT create and destroy ioctls
Implement ioctls to create and destroy free lists and HWRT datasets. Free
lists are used for GPU-side memory allocation during geometry processing.
HWRT datasets are the FW-side structures representing render targets.
Signed-off-by: Sarah Walker
---
drivers/gpu/drm/imagination/Makefile| 2 +
drivers/gpu/drm/imagination/pvr_ccb.c | 23 +
drivers/gpu/drm/imagination/pvr_device.h| 24 +
drivers/gpu/drm/imagination/pvr_drv.c | 104 +++-
drivers/gpu/drm/imagination/pvr_free_list.c | 577
drivers/gpu/drm/imagination/pvr_free_list.h | 185 +++
drivers/gpu/drm/imagination/pvr_hwrt.c | 559 +++
drivers/gpu/drm/imagination/pvr_hwrt.h | 163 ++
8 files changed, 1633 insertions(+), 4 deletions(-)
create mode 100644 drivers/gpu/drm/imagination/pvr_free_list.c
create mode 100644 drivers/gpu/drm/imagination/pvr_free_list.h
create mode 100644 drivers/gpu/drm/imagination/pvr_hwrt.c
create mode 100644 drivers/gpu/drm/imagination/pvr_hwrt.h
diff --git a/drivers/gpu/drm/imagination/Makefile
b/drivers/gpu/drm/imagination/Makefile
index 89a101dfb7f3..6edf64bed724 100644
--- a/drivers/gpu/drm/imagination/Makefile
+++ b/drivers/gpu/drm/imagination/Makefile
@@ -8,12 +8,14 @@ powervr-y := \
pvr_device.o \
pvr_device_info.o \
pvr_drv.o \
+ pvr_free_list.o \
pvr_fw.o \
pvr_fw_meta.o \
pvr_fw_mips.o \
pvr_fw_startstop.o \
pvr_fw_trace.o \
pvr_gem.o \
+ pvr_hwrt.o \
pvr_power.o \
pvr_vm.o \
pvr_vm_mips.o
diff --git a/drivers/gpu/drm/imagination/pvr_ccb.c
b/drivers/gpu/drm/imagination/pvr_ccb.c
index 621470d04ea8..6cf8ed705845 100644
--- a/drivers/gpu/drm/imagination/pvr_ccb.c
+++ b/drivers/gpu/drm/imagination/pvr_ccb.c
@@ -4,6 +4,7 @@
#include "pvr_ccb.h"
#include "pvr_device.h"
#include "pvr_drv.h"
+#include "pvr_free_list.h"
#include "pvr_fw.h"
#include "pvr_gem.h"
#include "pvr_power.h"
@@ -127,6 +128,28 @@ process_fwccb_command(struct pvr_device *pvr_dev, struct
rogue_fwif_fwccb_cmd *c
WARN_ON(pvr_power_reset(pvr_dev));
break;
+ case ROGUE_FWIF_FWCCB_CMD_FREELISTS_RECONSTRUCTION: {
+ struct rogue_fwif_fwccb_cmd_freelists_reconstruction_data *data
=
+ >cmd_data.cmd_freelists_reconstruction;
+ struct rogue_fwif_kccb_cmd resp_cmd;
+ struct rogue_fwif_freelists_reconstruction_data *resp_data =
+ _cmd.cmd_data.free_lists_reconstruction_data;
+ u32 i;
+
+ for (i = 0; i < data->freelist_count; i++)
+ pvr_free_list_reconstruct(pvr_dev,
data->freelist_ids[i]);
+
+ resp_cmd.cmd_type =
ROGUE_FWIF_KCCB_CMD_FREELISTS_RECONSTRUCTION_UPDATE;
+ resp_cmd.kccb_flags = 0;
+ resp_data->freelist_count = data->freelist_count;
+
+ memcpy(resp_data->freelist_ids, data->freelist_ids,
+ data->freelist_count *
sizeof(resp_data->freelist_ids[0]));
+
+ WARN_ON(pvr_kccb_send_cmd(pvr_dev, _cmd, NULL));
+ break;
+ }
+
default:
drm_info(from_pvr_device(pvr_dev), "Received unknown FWCCB
command %x\n",
cmd->cmd_type);
diff --git a/drivers/gpu/drm/imagination/pvr_device.h
b/drivers/gpu/drm/imagination/pvr_device.h
index ecd044564653..9431ebe64656 100644
--- a/drivers/gpu/drm/imagination/pvr_device.h
+++ b/drivers/gpu/drm/imagination/pvr_device.h
@@ -144,6 +144,14 @@ struct pvr_device {
/** @fw_dev: Firmware related data. */
struct pvr_fw_device fw_dev;
+ /**
+* @free_list_ids: Array of free lists belonging to this device. Array
members
+* are of type "struct pvr_free_list *".
+*
+* This array is used to allocate IDs used by the firmware.
+*/
+ struct xarray free_list_ids;
+
struct {
/** @work: Work item for watchdog callback. */
struct delayed_work work;
@@ -224,6 +232,22 @@ struct pvr_file {
*/
struct pvr_device *pvr_dev;
+ /**
+* @free_list_handles: Array of free lists belonging to this file. Array
+* members are of type "struct pvr_free_list *".
+*
+* This array is used to allocate handles returned to userspace.
+*/
+ struct xarray free_list_handles;
+
+ /**
+* @hwrt_handles: Array of HWRT datasets belonging to this file. Array
+* members are of type "struct pvr_hwrt_dataset *".
+*
+* This array is used to allocate handles returned to userspace.
+*/
+ struct xarray hwrt_handles;
+
/**
* @vm_ctx_handles: Array of VM contexts belonging to this file. Array
* members are of type "struct pvr_vm_context *".
diff --git a/drivers/gpu/drm/imagination/pvr_drv.c
[PATCH v3 10/17] drm/imagination: Implement firmware infrastructure and META FW support
The infrastructure includes parsing of the firmware image, initialising
FW-side structures, handling the kernel and firmware command
ringbuffers and starting & stopping the firmware processor.
This patch also adds the necessary support code for the META firmware
processor.
This patch depends on:
drm: fix drmm_mutex_init():
https://lists.freedesktop.org/archives/dri-devel/2023-May/404863.html
Signed-off-by: Sarah Walker
---
drivers/gpu/drm/imagination/Makefile |5 +
drivers/gpu/drm/imagination/pvr_ccb.c | 637
drivers/gpu/drm/imagination/pvr_ccb.h | 62 +
drivers/gpu/drm/imagination/pvr_device.c | 89 +-
drivers/gpu/drm/imagination/pvr_device.h | 56 +
drivers/gpu/drm/imagination/pvr_fw.c | 1386 +
drivers/gpu/drm/imagination/pvr_fw.h | 409 -
drivers/gpu/drm/imagination/pvr_fw_info.h | 115 ++
drivers/gpu/drm/imagination/pvr_fw_meta.c | 610
drivers/gpu/drm/imagination/pvr_fw_meta.h | 14 +
.../gpu/drm/imagination/pvr_fw_startstop.c| 280
.../gpu/drm/imagination/pvr_fw_startstop.h| 13 +
drivers/gpu/drm/imagination/pvr_fw_trace.c| 99 ++
drivers/gpu/drm/imagination/pvr_fw_trace.h| 78 +
drivers/gpu/drm/imagination/pvr_power.c | 94 +-
drivers/gpu/drm/imagination/pvr_vm.c | 45 +-
16 files changed, 3973 insertions(+), 19 deletions(-)
create mode 100644 drivers/gpu/drm/imagination/pvr_ccb.c
create mode 100644 drivers/gpu/drm/imagination/pvr_ccb.h
create mode 100644 drivers/gpu/drm/imagination/pvr_fw.c
create mode 100644 drivers/gpu/drm/imagination/pvr_fw_info.h
create mode 100644 drivers/gpu/drm/imagination/pvr_fw_meta.c
create mode 100644 drivers/gpu/drm/imagination/pvr_fw_meta.h
create mode 100644 drivers/gpu/drm/imagination/pvr_fw_startstop.c
create mode 100644 drivers/gpu/drm/imagination/pvr_fw_startstop.h
create mode 100644 drivers/gpu/drm/imagination/pvr_fw_trace.c
create mode 100644 drivers/gpu/drm/imagination/pvr_fw_trace.h
diff --git a/drivers/gpu/drm/imagination/Makefile
b/drivers/gpu/drm/imagination/Makefile
index 00036b075505..f6fe9fbea094 100644
--- a/drivers/gpu/drm/imagination/Makefile
+++ b/drivers/gpu/drm/imagination/Makefile
@@ -4,9 +4,14 @@
subdir-ccflags-y := -I$(srctree)/$(src)
powervr-y := \
+ pvr_ccb.o \
pvr_device.o \
pvr_device_info.o \
pvr_drv.o \
+ pvr_fw.o \
+ pvr_fw_meta.o \
+ pvr_fw_startstop.o \
+ pvr_fw_trace.o \
pvr_gem.o \
pvr_power.o \
pvr_vm.o
diff --git a/drivers/gpu/drm/imagination/pvr_ccb.c
b/drivers/gpu/drm/imagination/pvr_ccb.c
new file mode 100644
index ..621470d04ea8
--- /dev/null
+++ b/drivers/gpu/drm/imagination/pvr_ccb.c
@@ -0,0 +1,637 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/* Copyright (c) 2022 Imagination Technologies Ltd. */
+
+#include "pvr_ccb.h"
+#include "pvr_device.h"
+#include "pvr_drv.h"
+#include "pvr_fw.h"
+#include "pvr_gem.h"
+#include "pvr_power.h"
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define RESERVE_SLOT_TIMEOUT (1 * HZ) /* 1s */
+
+/**
+ * pvr_ccb_init() - Initialise a CCB
+ * @pvr_dev: Device pointer.
+ * @pvr_ccb: Pointer to CCB structure to initialise.
+ * @num_cmds_log2: Log2 of number of commands in this CCB.
+ * @cmd_size: Command size for this CCB.
+ *
+ * Return:
+ * * Zero on success, or
+ * * Any error code returned by pvr_fw_object_create_and_map().
+ */
+static int
+pvr_ccb_init(struct pvr_device *pvr_dev, struct pvr_ccb *pvr_ccb,
+u32 num_cmds_log2, size_t cmd_size)
+{
+ u32 num_cmds = 1 << num_cmds_log2;
+ u32 ccb_size = num_cmds * cmd_size;
+ int err;
+
+ err = drmm_mutex_init(from_pvr_device(pvr_dev), _ccb->lock);
+ if (err)
+ goto err_out;
+
+ /*
+* Map CCB and control structure as uncached, so we don't have to flush
+* CPU cache repeatedly when polling for space.
+*/
+ pvr_ccb->ctrl = pvr_fw_object_create_and_map(pvr_dev,
sizeof(*pvr_ccb->ctrl),
+
PVR_BO_FW_FLAGS_DEVICE_UNCACHED,
+_ccb->ctrl_obj);
+ if (IS_ERR(pvr_ccb->ctrl)) {
+ err = PTR_ERR(pvr_ccb->ctrl);
+ goto err_out;
+ }
+
+ pvr_ccb->ccb = pvr_fw_object_create_and_map(pvr_dev, ccb_size,
+
PVR_BO_FW_FLAGS_DEVICE_UNCACHED |
+ DRM_PVR_BO_CREATE_ZEROED,
+ _ccb->ccb_obj);
+ if (IS_ERR(pvr_ccb->ccb)) {
+ err = PTR_ERR(pvr_ccb->ccb);
+ goto err_free_ctrl;
+ }
+
+ pvr_fw_object_get_fw_addr(pvr_ccb->ctrl_obj, _ccb->ctrl_fw_addr);
+ pvr_fw_object_get_fw_addr(pvr_ccb->ccb_obj, _ccb->ccb_fw_addr);
+
+
[PATCH v3 03/17] drm/imagination/uapi: Add PowerVR driver UAPI
Add the UAPI implementation for the PowerVR driver.
Signed-off-by: Sarah Walker
---
MAINTAINERS|1 +
include/uapi/drm/pvr_drm.h | 1333
2 files changed, 1334 insertions(+)
create mode 100644 include/uapi/drm/pvr_drm.h
diff --git a/MAINTAINERS b/MAINTAINERS
index a41517843a10..3ad9de48a463 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -10090,6 +10090,7 @@ M: Sarah Walker
M: Donald Robson
S: Supported
F: Documentation/devicetree/bindings/gpu/img,powervr.yaml
+F: include/uapi/drm/pvr_drm.h
IMON SOUNDGRAPH USB IR RECEIVER
M: Sean Young
diff --git a/include/uapi/drm/pvr_drm.h b/include/uapi/drm/pvr_drm.h
new file mode 100644
index ..2f7bc96aaf52
--- /dev/null
+++ b/include/uapi/drm/pvr_drm.h
@@ -0,0 +1,1333 @@
+/* SPDX-License-Identifier: (GPL-2.0 WITH Linux-syscall-note) OR MIT */
+/* Copyright (c) 2022 Imagination Technologies Ltd. */
+
+#ifndef PVR_DRM_UAPI_H
+#define PVR_DRM_UAPI_H
+
+#include "drm.h"
+
+#include
+#include
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/**
+ * DOC: PowerVR UAPI
+ *
+ * The PowerVR IOCTL argument structs have a few limitations in place, in
+ * addition to the standard kernel restrictions:
+ *
+ * - All members must be type-aligned.
+ * - The overall struct must be padded to 64-bit alignment.
+ * - Explicit padding is almost always required. This takes the form of
+ *``_padding_[x]`` members of sufficient size to pad to the next
power-of-two
+ *alignment, where [x] is the offset into the struct in hexadecimal. Arrays
+ *are never used for alignment. Padding fields must be zeroed; this is
+ *always checked.
+ * - Unions may only appear as the last member of a struct.
+ * - Individual union members may grow in the future. The space between the
+ *end of a union member and the end of its containing union is considered
+ *"implicit padding" and must be zeroed. This is always checked.
+ *
+ * In addition to the IOCTL argument structs, the PowerVR UAPI makes use of
+ * DEV_QUERY argument structs. These are used to fetch information about the
+ * device and runtime. These structs are subject to the same rules set out
+ * above.
+ */
+
+/**
+ * struct drm_pvr_obj_array - Container used to pass arrays of objects
+ *
+ * It is not unusual to have to extend objects to pass new parameters, and the
DRM
+ * ioctl infrastructure is supporting that by padding ioctl arguments with
zeros
+ * when the data passed by userspace is smaller than the struct defined in the
+ * drm_ioctl_desc, thus keeping things backward compatible. This type is just
+ * applying the same concepts to indirect objects passed through arrays
referenced
+ * from the main ioctl arguments structure: the stride basically defines the
size
+ * of the object passed by userspace, which allows the kernel driver to pad
with
+ * zeros when it's smaller than the size of the object it expects.
+ *
+ * Use ``DRM_PVR_OBJ_ARRAY()`` to fill object array fields, unless you
+ * have a very good reason not to.
+ */
+struct drm_pvr_obj_array {
+ /** @stride: Stride of object struct. Used for versioning. */
+ __u32 stride;
+
+ /** @count: Number of objects in the array. */
+ __u32 count;
+
+ /** @array: User pointer to an array of objects. */
+ __u64 array;
+};
+
+/**
+ * DRM_PVR_OBJ_ARRAY() - Helper macro for filling drm_pvr_obj_array.
+ * @cnt: Number of elements pointed to py @ptr.
+ * @ptr: Pointer to start of a C array.
+ *
+ * Return: Literal of type drm_pvr_obj_array.
+ */
+#define DRM_PVR_OBJ_ARRAY(cnt, ptr) \
+ { .stride = sizeof((ptr)[0]), .count = (cnt), .array =
(__u64)(uintptr_t)(ptr) }
+
+/**
+ * DOC: PowerVR IOCTL interface
+ */
+
+/**
+ * PVR_IOCTL() - Build a PowerVR IOCTL number
+ * @_ioctl: An incrementing id for this IOCTL. Added to %DRM_COMMAND_BASE.
+ * @_mode: Must be one of %DRM_IOR, %DRM_IOW or %DRM_IOWR.
+ * @_data: The type of the args struct passed by this IOCTL.
+ *
+ * The struct referred to by @_data must have a ``drm_pvr_ioctl_`` prefix and
an
+ * ``_args suffix``. They are therefore omitted from @_data.
+ *
+ * This should only be used to build the constants described below; it should
+ * never be used to call an IOCTL directly.
+ *
+ * Return: An IOCTL number to be passed to ioctl() from userspace.
+ */
+#define PVR_IOCTL(_ioctl, _mode, _data) \
+ _mode(DRM_COMMAND_BASE + (_ioctl), struct drm_pvr_ioctl_##_data##_args)
+
+#define DRM_IOCTL_PVR_DEV_QUERY PVR_IOCTL(0x00, DRM_IOWR, dev_query)
+#define DRM_IOCTL_PVR_CREATE_BO PVR_IOCTL(0x01, DRM_IOWR, create_bo)
+#define DRM_IOCTL_PVR_GET_BO_MMAP_OFFSET PVR_IOCTL(0x02, DRM_IOWR,
get_bo_mmap_offset)
+#define DRM_IOCTL_PVR_CREATE_VM_CONTEXT PVR_IOCTL(0x03, DRM_IOWR,
create_vm_context)
+#define DRM_IOCTL_PVR_DESTROY_VM_CONTEXT PVR_IOCTL(0x04, DRM_IOW,
destroy_vm_context)
+#define DRM_IOCTL_PVR_VM_MAP PVR_IOCTL(0x05, DRM_IOW, vm_map)
+#define
[PATCH v3 07/17] drm/imagination: Add GPU ID parsing and firmware loading
Read the GPU ID register at probe time and select the correct
features/quirks/enhancements. Use the GPU ID to form the firmware
file name and load the firmware.
The features/quirks/enhancements arrays are currently hardcoded in
the driver for the supported GPUs. We are looking at moving this
information to the firmware image.
Signed-off-by: Sarah Walker
---
drivers/gpu/drm/imagination/Makefile | 1 +
drivers/gpu/drm/imagination/pvr_device.c | 359
drivers/gpu/drm/imagination/pvr_device.h | 221 +++
drivers/gpu/drm/imagination/pvr_device_info.c | 223 +++
drivers/gpu/drm/imagination/pvr_device_info.h | 133 +
drivers/gpu/drm/imagination/pvr_drv.c | 553 +-
drivers/gpu/drm/imagination/pvr_drv.h | 108
drivers/gpu/drm/imagination/pvr_fw.h | 20 +
8 files changed, 1617 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/imagination/pvr_device_info.c
create mode 100644 drivers/gpu/drm/imagination/pvr_device_info.h
create mode 100644 drivers/gpu/drm/imagination/pvr_fw.h
diff --git a/drivers/gpu/drm/imagination/Makefile
b/drivers/gpu/drm/imagination/Makefile
index 186f920d615b..d713b1280776 100644
--- a/drivers/gpu/drm/imagination/Makefile
+++ b/drivers/gpu/drm/imagination/Makefile
@@ -5,6 +5,7 @@ subdir-ccflags-y := -I$(srctree)/$(src)
powervr-y := \
pvr_device.o \
+ pvr_device_info.o \
pvr_drv.o \
obj-$(CONFIG_DRM_POWERVR) += powervr.o
diff --git a/drivers/gpu/drm/imagination/pvr_device.c
b/drivers/gpu/drm/imagination/pvr_device.c
index 790c36cebec1..2e03763f2eb7 100644
--- a/drivers/gpu/drm/imagination/pvr_device.c
+++ b/drivers/gpu/drm/imagination/pvr_device.c
@@ -2,20 +2,32 @@
/* Copyright (c) 2022 Imagination Technologies Ltd. */
#include "pvr_device.h"
+#include "pvr_device_info.h"
+
+#include "pvr_fw.h"
+#include "pvr_rogue_cr_defs.h"
#include
+#include
#include
#include
#include
#include
#include
+#include
#include
+#include
#include
+#include
#include
#include
#include
#include
+#include
+
+/* Major number for the supported version of the firmware. */
+#define PVR_FW_VERSION_MAJOR 1
/**
* pvr_device_reg_init() - Initialize kernel access to a PowerVR device's
@@ -205,6 +217,246 @@ pvr_device_regulator_init(struct pvr_device *pvr_dev)
return err;
}
+/**
+ * pvr_device_clk_core_get_freq - Get current PowerVR device core clock
frequency
+ * @pvr_dev: Target PowerVR device.
+ * @freq_out: Pointer to location to store core clock frequency in Hz.
+ *
+ * Returns:
+ * * 0 on success, or
+ * * -%EINVAL if frequency can not be determined.
+ */
+int
+pvr_device_clk_core_get_freq(struct pvr_device *pvr_dev, u32 *freq_out)
+{
+ u32 freq = clk_get_rate(pvr_dev->core_clk);
+
+ if (!freq)
+ return -EINVAL;
+
+ *freq_out = freq;
+ return 0;
+}
+
+/**
+ * pvr_build_firmware_filename() - Construct a PowerVR firmware filename
+ * @pvr_dev: Target PowerVR device.
+ * @base: First part of the filename.
+ * @major: Major version number.
+ *
+ * A PowerVR firmware filename consists of three parts separated by underscores
+ * (``'_'``) along with a '.fw' file suffix. The first part is the exact value
+ * of @base, the second part is the hardware version string derived from
@pvr_fw
+ * and the final part is the firmware version number constructed from @major
with
+ * a 'v' prefix, e.g. powervr/rogue_4.40.2.51_v1.fw.
+ *
+ * The returned string will have been slab allocated and must be freed with
+ * kfree().
+ *
+ * Return:
+ * * The constructed filename on success, or
+ * * Any error returned by kasprintf().
+ */
+static char *
+pvr_build_firmware_filename(struct pvr_device *pvr_dev, const char *base,
+ u8 major)
+{
+ struct pvr_gpu_id *gpu_id = _dev->gpu_id;
+
+ return kasprintf(GFP_KERNEL, "%s_%d.%d.%d.%d_v%d.fw", base, gpu_id->b,
+gpu_id->v, gpu_id->n, gpu_id->c, major);
+}
+
+/**
+ * pvr_request_firmware() - Load firmware for a PowerVR device
+ * @pvr_dev: Target PowerVR device.
+ *
+ * See pvr_build_firmware_filename() for details on firmware file naming.
+ *
+ * Return:
+ * * 0 on success,
+ * * Any error returned by pvr_build_firmware_filename(), or
+ * * Any error returned by request_firmware().
+ */
+static int
+pvr_request_firmware(struct pvr_device *pvr_dev)
+{
+ struct drm_device *drm_dev = _dev->base;
+ char *filename;
+ const struct firmware *fw;
+ int err;
+
+ filename = pvr_build_firmware_filename(pvr_dev, "powervr/rogue",
+ PVR_FW_VERSION_MAJOR);
+ if (IS_ERR(filename))
+ return PTR_ERR(filename);
+
+ /*
+* This function takes a copy of , meaning we can free our
+* instance before returning.
+*/
+ err = request_firmware(, filename, pvr_dev->base.dev);
+ if (err) {
+
[PATCH v3 13/17] drm/imagination: Implement context creation/destruction ioctls
Implement ioctls for the creation and destruction of contexts. Contexts are
used for job submission and each is associated with a particular job type.
Signed-off-by: Sarah Walker
---
drivers/gpu/drm/imagination/Makefile | 4 +
drivers/gpu/drm/imagination/pvr_cccb.c| 230
drivers/gpu/drm/imagination/pvr_cccb.h| 102 ++
drivers/gpu/drm/imagination/pvr_context.c | 327 ++
drivers/gpu/drm/imagination/pvr_context.h | 155 +
drivers/gpu/drm/imagination/pvr_device.h | 21 ++
drivers/gpu/drm/imagination/pvr_drv.c | 26 +-
drivers/gpu/drm/imagination/pvr_stream.c | 309 +
drivers/gpu/drm/imagination/pvr_stream.h | 75
drivers/gpu/drm/imagination/pvr_stream_defs.c | 125 +++
drivers/gpu/drm/imagination/pvr_stream_defs.h | 16 +
11 files changed, 1388 insertions(+), 2 deletions(-)
create mode 100644 drivers/gpu/drm/imagination/pvr_cccb.c
create mode 100644 drivers/gpu/drm/imagination/pvr_cccb.h
create mode 100644 drivers/gpu/drm/imagination/pvr_context.c
create mode 100644 drivers/gpu/drm/imagination/pvr_context.h
create mode 100644 drivers/gpu/drm/imagination/pvr_stream.c
create mode 100644 drivers/gpu/drm/imagination/pvr_stream.h
create mode 100644 drivers/gpu/drm/imagination/pvr_stream_defs.c
create mode 100644 drivers/gpu/drm/imagination/pvr_stream_defs.h
diff --git a/drivers/gpu/drm/imagination/Makefile
b/drivers/gpu/drm/imagination/Makefile
index 6edf64bed724..786a7bf6c773 100644
--- a/drivers/gpu/drm/imagination/Makefile
+++ b/drivers/gpu/drm/imagination/Makefile
@@ -5,6 +5,8 @@ subdir-ccflags-y := -I$(srctree)/$(src)
powervr-y := \
pvr_ccb.o \
+ pvr_cccb.o \
+ pvr_context.o \
pvr_device.o \
pvr_device_info.o \
pvr_drv.o \
@@ -17,6 +19,8 @@ powervr-y := \
pvr_gem.o \
pvr_hwrt.o \
pvr_power.o \
+ pvr_stream.o \
+ pvr_stream_defs.o \
pvr_vm.o \
pvr_vm_mips.o
diff --git a/drivers/gpu/drm/imagination/pvr_cccb.c
b/drivers/gpu/drm/imagination/pvr_cccb.c
new file mode 100644
index ..b15a7385e5cd
--- /dev/null
+++ b/drivers/gpu/drm/imagination/pvr_cccb.c
@@ -0,0 +1,230 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/* Copyright (c) 2022 Imagination Technologies Ltd. */
+
+#include "pvr_ccb.h"
+#include "pvr_cccb.h"
+#include "pvr_device.h"
+#include "pvr_gem.h"
+#include "pvr_hwrt.h"
+
+#include
+#include
+#include
+#include
+#include
+
+static __always_inline u32
+get_ccb_space(u32 w_off, u32 r_off, u32 ccb_size)
+{
+ return (((r_off) - (w_off)) + ((ccb_size) - 1)) & ((ccb_size) - 1);
+}
+
+/**
+ * pvr_cccb_init() - Initialise a Client CCB
+ * @pvr_dev: Device pointer.
+ * @pvr_cccb: Pointer to Client CCB structure to initialise.
+ * @size_log2: Log2 size of Client CCB in bytes.
+ * @name: Name of owner of Client CCB. Used for fence context.
+ *
+ * Return:
+ * * Zero on success, or
+ * * Any error code returned by pvr_fw_object_create_and_map().
+ */
+int
+pvr_cccb_init(struct pvr_device *pvr_dev, struct pvr_cccb *pvr_cccb,
+ u32 size_log2, const char *name)
+{
+ size_t size = 1 << size_log2;
+ int err;
+
+ /*
+* Map CCCB and control structure as uncached, so we don't have to flush
+* CPU cache repeatedly when polling for space.
+*/
+ pvr_cccb->ctrl = pvr_fw_object_create_and_map(pvr_dev,
sizeof(*pvr_cccb->ctrl),
+
PVR_BO_FW_FLAGS_DEVICE_UNCACHED,
+ _cccb->ctrl_obj);
+ if (IS_ERR(pvr_cccb->ctrl)) {
+ err = PTR_ERR(pvr_cccb->ctrl);
+ goto err_out;
+ }
+
+ pvr_cccb->cccb = pvr_fw_object_create_and_map(pvr_dev, size,
+
PVR_BO_FW_FLAGS_DEVICE_UNCACHED |
+ DRM_PVR_BO_CREATE_ZEROED,
+ _cccb->cccb_obj);
+ if (IS_ERR(pvr_cccb->cccb)) {
+ err = PTR_ERR(pvr_cccb->cccb);
+ goto err_free_ctrl;
+ }
+
+ pvr_fw_object_get_fw_addr(pvr_cccb->ctrl_obj, _cccb->ctrl_fw_addr);
+ pvr_fw_object_get_fw_addr(pvr_cccb->cccb_obj, _cccb->cccb_fw_addr);
+
+ WRITE_ONCE(pvr_cccb->ctrl->write_offset, 0);
+ WRITE_ONCE(pvr_cccb->ctrl->read_offset, 0);
+ WRITE_ONCE(pvr_cccb->ctrl->dep_offset, 0);
+ WRITE_ONCE(pvr_cccb->ctrl->wrap_mask, size - 1);
+ pvr_cccb->size = size;
+ pvr_cccb->write_offset = 0;
+ pvr_cccb->wrap_mask = size - 1;
+
+ return 0;
+
+err_free_ctrl:
+ pvr_fw_object_unmap_and_destroy(pvr_cccb->ctrl_obj);
+
+err_out:
+ return err;
+}
+
+/**
+ * pvr_cccb_fini() - Release Client CCB structure
+ * @pvr_cccb: Client CCB to release.
+ */
+void
+pvr_cccb_fini(struct pvr_cccb *pvr_cccb)
+{
+
[PATCH v3 15/17] drm/imagination: Add firmware trace to debugfs
Firmware trace is exposed at /sys/debug/dri//pvr_fw/trace_0.
Trace is enabled via the group mask at
/sys/debug/dri//pvr_params/fw_trace_mask.
Signed-off-by: Sarah Walker
---
drivers/gpu/drm/imagination/Makefile | 4 +
drivers/gpu/drm/imagination/pvr_debugfs.c | 53 +++
drivers/gpu/drm/imagination/pvr_debugfs.h | 29 ++
drivers/gpu/drm/imagination/pvr_device.c | 9 +
drivers/gpu/drm/imagination/pvr_device.h | 10 +
drivers/gpu/drm/imagination/pvr_drv.c | 4 +
drivers/gpu/drm/imagination/pvr_fw_trace.c | 393 -
drivers/gpu/drm/imagination/pvr_params.c | 147
drivers/gpu/drm/imagination/pvr_params.h | 72
9 files changed, 720 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/imagination/pvr_debugfs.c
create mode 100644 drivers/gpu/drm/imagination/pvr_debugfs.h
create mode 100644 drivers/gpu/drm/imagination/pvr_params.c
create mode 100644 drivers/gpu/drm/imagination/pvr_params.h
diff --git a/drivers/gpu/drm/imagination/Makefile
b/drivers/gpu/drm/imagination/Makefile
index 85cd0c0c70cd..89c47adf6b0d 100644
--- a/drivers/gpu/drm/imagination/Makefile
+++ b/drivers/gpu/drm/imagination/Makefile
@@ -19,6 +19,7 @@ powervr-y := \
pvr_gem.o \
pvr_hwrt.o \
pvr_job.o \
+ pvr_params.o \
pvr_power.o \
pvr_queue.o \
pvr_stream.o \
@@ -26,4 +27,7 @@ powervr-y := \
pvr_vm.o \
pvr_vm_mips.o
+powervr-$(CONFIG_DEBUG_FS) += \
+ pvr_debugfs.o
+
obj-$(CONFIG_DRM_POWERVR) += powervr.o
diff --git a/drivers/gpu/drm/imagination/pvr_debugfs.c
b/drivers/gpu/drm/imagination/pvr_debugfs.c
new file mode 100644
index ..02e44c070861
--- /dev/null
+++ b/drivers/gpu/drm/imagination/pvr_debugfs.c
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/* Copyright (c) 2022 Imagination Technologies Ltd. */
+
+#include "pvr_debugfs.h"
+
+#include "pvr_device.h"
+#include "pvr_fw_trace.h"
+#include "pvr_params.h"
+
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+
+static const struct pvr_debugfs_entry pvr_debugfs_entries[] = {
+ {"pvr_params", pvr_params_debugfs_init},
+ {"pvr_fw", pvr_fw_trace_debugfs_init},
+};
+
+void
+pvr_debugfs_init(struct drm_minor *minor)
+{
+ struct drm_device *drm_dev = minor->dev;
+ struct pvr_device *pvr_dev = to_pvr_device(drm_dev);
+ struct dentry *root = minor->debugfs_root;
+ size_t i;
+
+ for (i = 0; i < ARRAY_SIZE(pvr_debugfs_entries); ++i) {
+ const struct pvr_debugfs_entry *entry = _debugfs_entries[i];
+ struct dentry *dir;
+
+ dir = debugfs_create_dir(entry->name, root);
+ if (IS_ERR(dir)) {
+ drm_warn(drm_dev,
+"failed to create debugfs dir '%s' (err=%d)",
+entry->name, (int)PTR_ERR(dir));
+ continue;
+ }
+
+ entry->init(pvr_dev, dir);
+ }
+}
+
+/*
+ * Since all entries are created under _minor->debugfs_root, there's no
+ * need for a pvr_debugfs_fini() as DRM will clean up everything under its root
+ * automatically.
+ */
diff --git a/drivers/gpu/drm/imagination/pvr_debugfs.h
b/drivers/gpu/drm/imagination/pvr_debugfs.h
new file mode 100644
index ..b260a2b26ebd
--- /dev/null
+++ b/drivers/gpu/drm/imagination/pvr_debugfs.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
+/* Copyright (c) 2022 Imagination Technologies Ltd. */
+
+#ifndef PVR_DEBUGFS_H
+#define PVR_DEBUGFS_H
+
+/* Forward declaration from . */
+struct drm_minor;
+
+#if defined(CONFIG_DEBUG_FS)
+/* Forward declaration from "pvr_device.h". */
+struct pvr_device;
+
+/* Forward declaration from . */
+struct dentry;
+
+struct pvr_debugfs_entry {
+ const char *name;
+ void (*init)(struct pvr_device *pvr_dev, struct dentry *dir);
+};
+
+void pvr_debugfs_init(struct drm_minor *minor);
+#else /* defined(CONFIG_DEBUG_FS) */
+#include
+
+static __always_inline void pvr_debugfs_init(struct drm_minor *minor) {}
+#endif /* defined(CONFIG_DEBUG_FS) */
+
+#endif /* PVR_DEBUGFS_H */
diff --git a/drivers/gpu/drm/imagination/pvr_device.c
b/drivers/gpu/drm/imagination/pvr_device.c
index 209bc35450a9..d62f038c8840 100644
--- a/drivers/gpu/drm/imagination/pvr_device.c
+++ b/drivers/gpu/drm/imagination/pvr_device.c
@@ -5,6 +5,7 @@
#include "pvr_device_info.h"
#include "pvr_fw.h"
+#include "pvr_params.h"
#include "pvr_power.h"
#include "pvr_rogue_cr_defs.h"
#include "pvr_stream.h"
@@ -580,6 +581,14 @@ pvr_device_init(struct pvr_device *pvr_dev)
struct device *dev = drm_dev->dev;
int err;
+ /*
+* Setup device parameters. We do this first in case other steps
+* depend on them.
+*/
+ err = pvr_device_params_init(_dev->params);
+ if (err)
+ return err;
+
/* Enable and initialize
[PATCH v3 11/17] drm/imagination: Implement MIPS firmware processor and MMU support
Add support for the MIPS firmware processor, used in the Series AXE GPU.
The MIPS firmware processor uses a separate MMU to the rest of the GPU, so
this patch adds support for that as well.
Signed-off-by: Sarah Walker
---
drivers/gpu/drm/imagination/Makefile | 4 +-
drivers/gpu/drm/imagination/pvr_fw.c | 2 +
drivers/gpu/drm/imagination/pvr_fw_mips.c | 280 ++
drivers/gpu/drm/imagination/pvr_fw_mips.h | 38 +++
drivers/gpu/drm/imagination/pvr_vm_mips.c | 222 +
drivers/gpu/drm/imagination/pvr_vm_mips.h | 22 ++
6 files changed, 567 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/imagination/pvr_fw_mips.c
create mode 100644 drivers/gpu/drm/imagination/pvr_fw_mips.h
create mode 100644 drivers/gpu/drm/imagination/pvr_vm_mips.c
create mode 100644 drivers/gpu/drm/imagination/pvr_vm_mips.h
diff --git a/drivers/gpu/drm/imagination/Makefile
b/drivers/gpu/drm/imagination/Makefile
index f6fe9fbea094..89a101dfb7f3 100644
--- a/drivers/gpu/drm/imagination/Makefile
+++ b/drivers/gpu/drm/imagination/Makefile
@@ -10,10 +10,12 @@ powervr-y := \
pvr_drv.o \
pvr_fw.o \
pvr_fw_meta.o \
+ pvr_fw_mips.o \
pvr_fw_startstop.o \
pvr_fw_trace.o \
pvr_gem.o \
pvr_power.o \
- pvr_vm.o
+ pvr_vm.o \
+ pvr_vm_mips.o
obj-$(CONFIG_DRM_POWERVR) += powervr.o
diff --git a/drivers/gpu/drm/imagination/pvr_fw.c
b/drivers/gpu/drm/imagination/pvr_fw.c
index 304d9bdebfe3..97740733f2b0 100644
--- a/drivers/gpu/drm/imagination/pvr_fw.c
+++ b/drivers/gpu/drm/imagination/pvr_fw.c
@@ -842,6 +842,8 @@ pvr_fw_init(struct pvr_device *pvr_dev)
if (fw_dev->processor_type == PVR_FW_PROCESSOR_TYPE_META) {
fw_dev->funcs = _fw_funcs_meta;
+ } else if (fw_dev->processor_type == PVR_FW_PROCESSOR_TYPE_MIPS) {
+ fw_dev->funcs = _fw_funcs_mips;
} else {
err = -EINVAL;
goto err_out;
diff --git a/drivers/gpu/drm/imagination/pvr_fw_mips.c
b/drivers/gpu/drm/imagination/pvr_fw_mips.c
new file mode 100644
index ..36188e8a86ac
--- /dev/null
+++ b/drivers/gpu/drm/imagination/pvr_fw_mips.c
@@ -0,0 +1,280 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/* Copyright (c) 2022 Imagination Technologies Ltd. */
+
+#include "pvr_device.h"
+#include "pvr_fw.h"
+#include "pvr_fw_mips.h"
+#include "pvr_gem.h"
+#include "pvr_rogue_mips.h"
+#include "pvr_vm_mips.h"
+
+#include
+#include
+#include
+
+#define ROGUE_FW_HEAP_MIPS_BASE 0xC000
+#define ROGUE_FW_HEAP_MIPS_SHIFT 24 /* 16 MB */
+#define ROGUE_FW_HEAP_MIPS_RESERVED_SIZE SZ_1M
+
+/**
+ * process_elf_command_stream() - Process ELF firmware image and populate
+ *firmware sections
+ * @pvr_dev: Device pointer.
+ * @fw: Pointer to firmware image.
+ * @layout_entries: Pointer to layout table.
+ * @num_layout_entries: Number of entries in layout table.
+ * @fw_code_ptr: Pointer to FW code section.
+ * @fw_data_ptr: Pointer to FW data section.
+ * @fw_core_code_ptr: Pointer to FW coremem code section.
+ * @fw_core_data_ptr: Pointer to FW coremem data section.
+ *
+ * Returns :
+ * * 0 on success, or
+ * * -EINVAL on any error in ELF command stream.
+ */
+static int
+process_elf_command_stream(struct pvr_device *pvr_dev, const u8 *fw,
+ const struct pvr_fw_layout_entry *layout_entries,
+ u32 num_layout_entries, u8 *fw_code_ptr,
+ u8 *fw_data_ptr, u8 *fw_core_code_ptr,
+ u8 *fw_core_data_ptr)
+{
+ struct elf32_hdr *header = (struct elf32_hdr *)fw;
+ struct elf32_phdr *program_header = (struct elf32_phdr *)(fw +
header->e_phoff);
+ struct drm_device *drm_dev = from_pvr_device(pvr_dev);
+ u32 entry;
+ int err;
+
+ for (entry = 0; entry < header->e_phnum; entry++, program_header++) {
+ void *write_addr;
+
+ /* Only consider loadable entries in the ELF segment table */
+ if (program_header->p_type != PT_LOAD)
+ continue;
+
+ err = pvr_fw_find_mmu_segment(program_header->p_vaddr,
program_header->p_memsz,
+ layout_entries,
num_layout_entries, fw_code_ptr,
+ fw_data_ptr, fw_core_code_ptr,
fw_core_data_ptr,
+ _addr);
+ if (err) {
+ drm_err(drm_dev,
+ "Addr 0x%x (size: %d) not found in any firmware
segment",
+ program_header->p_vaddr,
program_header->p_memsz);
+ goto err_out;
+ }
+
+ /* Write to FW allocation only if available */
+ if (write_addr) {
+ memcpy(write_addr, fw + program_header->p_offset,
+
[PATCH v3 16/17] drm/imagination: Add driver documentation
Add documentation for the UAPI and for the virtual memory design. Signed-off-by: Sarah Walker --- Documentation/gpu/drivers.rst | 2 + Documentation/gpu/imagination/index.rst | 14 + Documentation/gpu/imagination/uapi.rst| 174 +++ .../gpu/imagination/virtual_memory.rst| 462 ++ MAINTAINERS | 1 + 5 files changed, 653 insertions(+) create mode 100644 Documentation/gpu/imagination/index.rst create mode 100644 Documentation/gpu/imagination/uapi.rst create mode 100644 Documentation/gpu/imagination/virtual_memory.rst diff --git a/Documentation/gpu/drivers.rst b/Documentation/gpu/drivers.rst index 3a52f48215a3..5487deb218a3 100644 --- a/Documentation/gpu/drivers.rst +++ b/Documentation/gpu/drivers.rst @@ -3,9 +3,11 @@ GPU Driver Documentation .. toctree:: + :maxdepth: 3 amdgpu/index i915 + imagination/index mcde meson pl111 diff --git a/Documentation/gpu/imagination/index.rst b/Documentation/gpu/imagination/index.rst new file mode 100644 index ..57f28e460a03 --- /dev/null +++ b/Documentation/gpu/imagination/index.rst @@ -0,0 +1,14 @@ +=== +drm/imagination PowerVR Graphics Driver +=== + +.. kernel-doc:: drivers/gpu/drm/imagination/pvr_drv.c + :doc: PowerVR Graphics Driver + +Contents + +.. toctree:: + :maxdepth: 2 + + uapi + virtual_memory diff --git a/Documentation/gpu/imagination/uapi.rst b/Documentation/gpu/imagination/uapi.rst new file mode 100644 index ..2227ea7e6222 --- /dev/null +++ b/Documentation/gpu/imagination/uapi.rst @@ -0,0 +1,174 @@ + +UAPI + +The sources associated with this section can be found in ``pvr_drm.h``. + +.. kernel-doc:: include/uapi/drm/pvr_drm.h + :doc: PowerVR UAPI + +OBJECT ARRAYS += +.. kernel-doc:: include/uapi/drm/pvr_drm.h + :identifiers: drm_pvr_obj_array + +.. kernel-doc:: include/uapi/drm/pvr_drm.h + :identifiers: DRM_PVR_OBJ_ARRAY + +IOCTLS +== +.. kernel-doc:: include/uapi/drm/pvr_drm.h + :doc: PowerVR IOCTL interface + +.. kernel-doc:: include/uapi/drm/pvr_drm.h + :identifiers: PVR_IOCTL + +DEV_QUERY +- +.. kernel-doc:: include/uapi/drm/pvr_drm.h + :doc: PowerVR IOCTL DEV_QUERY interface + +.. kernel-doc:: include/uapi/drm/pvr_drm.h + :identifiers: drm_pvr_dev_query + +.. kernel-doc:: include/uapi/drm/pvr_drm.h + :identifiers: drm_pvr_ioctl_dev_query_args + +.. kernel-doc:: include/uapi/drm/pvr_drm.h + :identifiers: drm_pvr_dev_query_gpu_info + drm_pvr_dev_query_runtime_info + drm_pvr_dev_query_hwrt_info + drm_pvr_dev_query_quirks + drm_pvr_dev_query_enhancements + +.. kernel-doc:: include/uapi/drm/pvr_drm.h + :identifiers: drm_pvr_heap_id + drm_pvr_heap + drm_pvr_dev_query_heap_info + +.. kernel-doc:: include/uapi/drm/pvr_drm.h + :doc: Flags for DRM_PVR_DEV_QUERY_HEAP_INFO_GET. + +.. kernel-doc:: include/uapi/drm/pvr_drm.h + :identifiers: drm_pvr_static_data_area_usage + drm_pvr_static_data_area + drm_pvr_dev_query_static_data_areas + +CREATE_BO +- +.. kernel-doc:: include/uapi/drm/pvr_drm.h + :doc: PowerVR IOCTL CREATE_BO interface + +.. kernel-doc:: include/uapi/drm/pvr_drm.h + :identifiers: drm_pvr_ioctl_create_bo_args + +.. kernel-doc:: include/uapi/drm/pvr_drm.h + :doc: Flags for CREATE_BO + +GET_BO_MMAP_OFFSET +-- +.. kernel-doc:: include/uapi/drm/pvr_drm.h + :doc: PowerVR IOCTL GET_BO_MMAP_OFFSET interface + +.. kernel-doc:: include/uapi/drm/pvr_drm.h + :identifiers: drm_pvr_ioctl_get_bo_mmap_offset_args + +CREATE_VM_CONTEXT and DESTROY_VM_CONTEXT + +.. kernel-doc:: include/uapi/drm/pvr_drm.h + :doc: PowerVR IOCTL CREATE_VM_CONTEXT and DESTROY_VM_CONTEXT interfaces + +.. kernel-doc:: include/uapi/drm/pvr_drm.h + :identifiers: drm_pvr_ioctl_create_vm_context_args + drm_pvr_ioctl_destroy_vm_context_args + +VM_MAP and VM_UNMAP +--- +.. kernel-doc:: include/uapi/drm/pvr_drm.h + :doc: PowerVR IOCTL VM_MAP and VM_UNMAP interfaces + +.. kernel-doc:: include/uapi/drm/pvr_drm.h + :identifiers: drm_pvr_ioctl_vm_map_args + drm_pvr_ioctl_vm_unmap_args + +CREATE_CONTEXT and DESTROY_CONTEXT +-- +.. kernel-doc:: include/uapi/drm/pvr_drm.h + :doc: PowerVR IOCTL CREATE_CONTEXT and DESTROY_CONTEXT interfaces + +.. kernel-doc:: include/uapi/drm/pvr_drm.h + :identifiers: drm_pvr_ioctl_create_context_args + +.. kernel-doc:: include/uapi/drm/pvr_drm.h + :identifiers: drm_pvr_ctx_priority + drm_pvr_ctx_type + drm_pvr_static_render_context_state + drm_pvr_static_render_context_state_format +
[PATCH v3 00/17] Imagination Technologies PowerVR DRM driver
This patch series adds the initial DRM driver for Imagination Technologies PowerVR GPUs, starting with those based on our Rogue architecture. It's worth pointing out that this is a new driver, written from the ground up, rather than a refactored version of our existing downstream driver (pvrsrvkm). This new DRM driver supports: - GEM shmem allocations - dma-buf / PRIME - Per-context userspace managed virtual address space - DRM sync objects (binary and timeline) - Power management suspend / resume - GPU job submission (geometry, fragment, compute, transfer) - META firmware processor - MIPS firmware processor - GPU hang detection Currently our main focus is on our GX6250, AXE-1-16M and BXS-4-64 GPUs. Testing so far has been done using an Acer Chromebook R13 (GX6250 GPU) and a TI SK-AM62 board (AXE-1-16M GPU). Firmware for the GX6250 and AXE-1-16M can be found here: https://gitlab.freedesktop.org/frankbinns/linux-firmware/-/tree/powervr A Vulkan driver that works with our downstream kernel driver has already been merged into Mesa [1][2]. Support for this new DRM driver is being maintained in a draft merge request [3], with the branch located here: https://gitlab.freedesktop.org/frankbinns/mesa/-/tree/powervr-winsys Job stream formats are documented at: https://gitlab.freedesktop.org/mesa/mesa/-/blob/73fe6db819d951c02ce57eefcbd9b31b85900f33/src/imagination/csbgen/rogue_kmd_stream.xml The Vulkan driver is progressing towards Vulkan 1.0. We're code complete, and are working towards passing conformance. The current combination of this kernel driver with the Mesa Vulkan driver achieves 71.8% conformance. The code in this patch series, along with some of its history, can also be found here: https://gitlab.freedesktop.org/frankbinns/powervr/-/tree/powervr-next This patch series has dependencies on a number of patches not yet merged. They are listed below : maple_tree: split up MA_STATE() macro:https://lists.freedesktop.org/archives/dri-devel/2023-June/407927.html drm: manager to keep track of GPUs VA mappings: https://lists.freedesktop.org/archives/dri-devel/2023-June/407928.html drm/sched: Convert drm scheduler to use a work queue rather than kthread: https://lists.freedesktop.org/archives/dri-devel/2023-April/398458.html drm/sched: Move schedule policy to scheduler / entity: https://lists.freedesktop.org/archives/dri-devel/2023-April/398461.html drm/sched: Add DRM_SCHED_POLICY_SINGLE_ENTITY scheduling policy: https://lists.freedesktop.org/archives/dri-devel/2023-April/398460.html drm/sched: Start run wq before TDR in drm_sched_start: https://lists.freedesktop.org/archives/dri-devel/2023-April/398462.html drm/sched: Submit job before starting TDR: https://lists.freedesktop.org/archives/dri-devel/2023-April/398466.html drm/sched: Add helper to set TDR timeout: https://lists.freedesktop.org/archives/dri-devel/2023-April/398464.html drm: fix drmm_mutex_init(): https://lists.freedesktop.org/archives/dri-devel/2023-May/404863.html drm/sched: Make sure we wait for all dependencies in kill_jobs_cb(): https://lists.freedesktop.org/archives/dri-devel/2023-June/408901.html drm/sched: Call drm_sched_fence_set_parent() from drm_sched_fence_scheduled(): https://lists.freedesktop.org/archives/dri-devel/2023-June/408904.html [1] https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15243 [2] https://gitlab.freedesktop.org/mesa/mesa/-/tree/main/src/imagination/vulkan [3] https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15507 v3: * Use drm_sched for scheduling * Use GPU VA manager * Use runtime PM * Use drm_gem_shmem * GPU watchdog and device loss handling v2: * Redesigned and simplified UAPI based on RFC feedback from XDC 2022 * Support for transfer and partial render jobs * Support for timeline sync objects RFC v1: https://lists.freedesktop.org/archives/dri-devel/2022-August/367814.html RFC v2: https://lists.freedesktop.org/archives/dri-devel/2023-April/400149.html Matt Coster (1): sizes.h: Add entries between 32G and 64T Sarah Walker (16): dt-bindings: gpu: Add Imagination Technologies PowerVR GPU drm/imagination/uapi: Add PowerVR driver UAPI drm/imagination: Add skeleton PowerVR driver drm/imagination: Get GPU resources drm/imagination: Add GPU register and FWIF headers drm/imagination: Add GPU ID parsing and firmware loading drm/imagination: Add GEM and VM related code drm/imagination: Implement power management drm/imagination: Implement firmware infrastructure and META FW support drm/imagination: Implement MIPS firmware processor and MMU support drm/imagination: Implement free list and HWRT create and destroy ioctls drm/imagination: Implement context creation/destruction ioctls drm/imagination: Implement job submission and scheduling drm/imagination: Add firmware trace to debugfs drm/imagination: Add driver documentation arm64: dts: ti: k3-am62-main: Add GPU device node [DO NOT MERGE] .../devicetree/bindings/gpu/img,powervr.yaml | 71 +
[PATCH v3 02/17] dt-bindings: gpu: Add Imagination Technologies PowerVR GPU
Add the device tree binding documentation for the Series AXE GPU used in
TI AM62 SoCs.
Signed-off-by: Sarah Walker
---
.../devicetree/bindings/gpu/img,powervr.yaml | 71 +++
MAINTAINERS | 7 ++
2 files changed, 78 insertions(+)
create mode 100644 Documentation/devicetree/bindings/gpu/img,powervr.yaml
diff --git a/Documentation/devicetree/bindings/gpu/img,powervr.yaml
b/Documentation/devicetree/bindings/gpu/img,powervr.yaml
new file mode 100644
index ..652343876d1c
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpu/img,powervr.yaml
@@ -0,0 +1,71 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (c) 2022 Imagination Technologies Ltd.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpu/img,powervr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Imagination Technologies PowerVR GPU
+
+maintainers:
+ - Sarah Walker
+
+properties:
+ compatible:
+oneOf:
+ - items:
+ - enum:
+ - ti,am62-gpu
+ - const: img,powervr-seriesaxe
+
+ reg:
+maxItems: 1
+
+ clocks:
+minItems: 1
+maxItems: 3
+
+ clock-names:
+items:
+ - const: core
+ - const: mem
+ - const: sys
+minItems: 1
+
+ interrupts:
+items:
+ - description: GPU interrupt
+
+ interrupt-names:
+items:
+ - const: gpu
+
+ power-domains:
+maxItems: 1
+
+ power-supply: true
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - interrupts
+ - interrupt-names
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+#include
+
+gpu: gpu@fd0 {
+compatible = "ti,am62-gpu", "img,powervr-seriesaxe";
+reg = <0x0fd0 0x2>;
+power-domains = <_pds 187>;
+clocks = <_clks 187 0>;
+clock-names = "core";
+interrupts = ;
+interrupt-names = "gpu";
+};
diff --git a/MAINTAINERS b/MAINTAINERS
index b344e1318ac3..a41517843a10 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -10084,6 +10084,13 @@ IMGTEC IR DECODER DRIVER
S: Orphan
F: drivers/media/rc/img-ir/
+IMGTEC POWERVR DRM DRIVER
+M: Frank Binns
+M: Sarah Walker
+M: Donald Robson
+S: Supported
+F: Documentation/devicetree/bindings/gpu/img,powervr.yaml
+
IMON SOUNDGRAPH USB IR RECEIVER
M: Sean Young
L: linux-me...@vger.kernel.org
--
2.40.1
[PATCH v3 09/17] drm/imagination: Implement power management
Add power management to the driver, using runtime pm. The power off
sequence depends on firmware commands which are not implemented in this
patch.
Signed-off-by: Sarah Walker
---
drivers/gpu/drm/imagination/Makefile | 1 +
drivers/gpu/drm/imagination/pvr_device.c | 20 +-
drivers/gpu/drm/imagination/pvr_device.h | 17 ++
drivers/gpu/drm/imagination/pvr_drv.c| 35 +++-
drivers/gpu/drm/imagination/pvr_power.c | 239 +++
drivers/gpu/drm/imagination/pvr_power.h | 41
6 files changed, 351 insertions(+), 2 deletions(-)
create mode 100644 drivers/gpu/drm/imagination/pvr_power.c
create mode 100644 drivers/gpu/drm/imagination/pvr_power.h
diff --git a/drivers/gpu/drm/imagination/Makefile
b/drivers/gpu/drm/imagination/Makefile
index 93d89909a8d7..00036b075505 100644
--- a/drivers/gpu/drm/imagination/Makefile
+++ b/drivers/gpu/drm/imagination/Makefile
@@ -8,6 +8,7 @@ powervr-y := \
pvr_device_info.o \
pvr_drv.o \
pvr_gem.o \
+ pvr_power.o \
pvr_vm.o
obj-$(CONFIG_DRM_POWERVR) += powervr.o
diff --git a/drivers/gpu/drm/imagination/pvr_device.c
b/drivers/gpu/drm/imagination/pvr_device.c
index 6f7ef3767e56..8428e1270a22 100644
--- a/drivers/gpu/drm/imagination/pvr_device.c
+++ b/drivers/gpu/drm/imagination/pvr_device.c
@@ -5,6 +5,7 @@
#include "pvr_device_info.h"
#include "pvr_fw.h"
+#include "pvr_power.h"
#include "pvr_rogue_cr_defs.h"
#include "pvr_vm.h"
@@ -492,6 +493,8 @@ pvr_device_gpu_fini(struct pvr_device *pvr_dev)
int
pvr_device_init(struct pvr_device *pvr_dev)
{
+ struct drm_device *drm_dev = from_pvr_device(pvr_dev);
+ struct device *dev = drm_dev->dev;
int err;
/* Enable and initialize clocks required for the device to operate. */
@@ -503,21 +506,31 @@ pvr_device_init(struct pvr_device *pvr_dev)
if (err)
goto err_device_clk_fini;
+ /* Explicitly power the GPU so we can access control registers before
the FW is booted. */
+ err = pm_runtime_resume_and_get(dev);
+ if (err)
+ goto err_device_clk_fini;
+
/* Map the control registers into memory. */
err = pvr_device_reg_init(pvr_dev);
if (err)
- goto err_device_clk_fini;
+ goto err_pm_runtime_put;
/* Perform GPU-specific initialization steps. */
err = pvr_device_gpu_init(pvr_dev);
if (err)
goto err_device_reg_fini;
+ pm_runtime_put_autosuspend(dev);
+
return 0;
err_device_reg_fini:
pvr_device_reg_fini(pvr_dev);
+err_pm_runtime_put:
+ pm_runtime_put_sync_suspend(dev);
+
err_device_clk_fini:
pvr_device_clk_fini(pvr_dev);
@@ -532,12 +545,17 @@ pvr_device_init(struct pvr_device *pvr_dev)
void
pvr_device_fini(struct pvr_device *pvr_dev)
{
+ struct drm_device *drm_dev = from_pvr_device(pvr_dev);
+ struct device *dev = drm_dev->dev;
+
/*
* Deinitialization stages are performed in reverse order compared to
* the initialization stages in pvr_device_init().
*/
+ pm_runtime_get_sync(dev);
pvr_device_gpu_fini(pvr_dev);
pvr_device_reg_fini(pvr_dev);
+ pm_runtime_put_sync_suspend(dev);
pvr_device_clk_fini(pvr_dev);
}
diff --git a/drivers/gpu/drm/imagination/pvr_device.h
b/drivers/gpu/drm/imagination/pvr_device.h
index ce10bca36eb1..e5c5e47bf573 100644
--- a/drivers/gpu/drm/imagination/pvr_device.h
+++ b/drivers/gpu/drm/imagination/pvr_device.h
@@ -118,6 +118,9 @@ struct pvr_device {
/** @regulator: Power regulator. */
struct regulator *regulator;
+ /** @irq_wq: Workqueue for actions triggered off the IRQ handler. */
+ struct workqueue_struct *irq_wq;
+
/**
* @kernel_vm_ctx: Virtual memory context used for kernel mappings.
*
@@ -130,6 +133,20 @@ struct pvr_device {
/** @fw_dev: Firmware related data. */
struct pvr_fw_device fw_dev;
+
+ struct {
+ /** @work: Work item for watchdog callback. */
+ struct delayed_work work;
+
+ /** @old_kccb_cmds_executed: KCCB command execution count at
last watchdog poll. */
+ u32 old_kccb_cmds_executed;
+
+ /** @kccb_stall_count: Number of watchdog polls KCCB has been
stalled for. */
+ u32 kccb_stall_count;
+ } watchdog;
+
+ /** @lost: %true if the device has been lost. */
+ bool lost;
};
/**
diff --git a/drivers/gpu/drm/imagination/pvr_drv.c
b/drivers/gpu/drm/imagination/pvr_drv.c
index 547b4fbe355c..9d26cfcc7a16 100644
--- a/drivers/gpu/drm/imagination/pvr_drv.c
+++ b/drivers/gpu/drm/imagination/pvr_drv.c
@@ -4,6 +4,7 @@
#include "pvr_device.h"
#include "pvr_drv.h"
#include "pvr_gem.h"
+#include "pvr_power.h"
#include "pvr_rogue_defs.h"
#include "pvr_rogue_fwif_client.h"
#include "pvr_rogue_fwif_shared.h"
@@ -73,6 +74,9 @@
[PATCH v3 05/17] drm/imagination: Get GPU resources
Acquire clock, regulator and register resources, and enable/map as
appropriate.
Signed-off-by: Sarah Walker
---
drivers/gpu/drm/imagination/Makefile | 1 +
drivers/gpu/drm/imagination/pvr_device.c | 271 +++
drivers/gpu/drm/imagination/pvr_device.h | 214 ++
drivers/gpu/drm/imagination/pvr_drv.c| 11 +-
4 files changed, 496 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/imagination/pvr_device.c
diff --git a/drivers/gpu/drm/imagination/Makefile
b/drivers/gpu/drm/imagination/Makefile
index 62ccf0ccbd51..186f920d615b 100644
--- a/drivers/gpu/drm/imagination/Makefile
+++ b/drivers/gpu/drm/imagination/Makefile
@@ -4,6 +4,7 @@
subdir-ccflags-y := -I$(srctree)/$(src)
powervr-y := \
+ pvr_device.o \
pvr_drv.o \
obj-$(CONFIG_DRM_POWERVR) += powervr.o
diff --git a/drivers/gpu/drm/imagination/pvr_device.c
b/drivers/gpu/drm/imagination/pvr_device.c
new file mode 100644
index ..790c36cebec1
--- /dev/null
+++ b/drivers/gpu/drm/imagination/pvr_device.c
@@ -0,0 +1,271 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/* Copyright (c) 2022 Imagination Technologies Ltd. */
+
+#include "pvr_device.h"
+
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/**
+ * pvr_device_reg_init() - Initialize kernel access to a PowerVR device's
+ * control registers.
+ * @pvr_dev: Target PowerVR device.
+ *
+ * Sets struct pvr_device->regs.
+ *
+ * This method of mapping the device control registers into memory ensures that
+ * they are unmapped when the driver is detached (i.e. no explicit cleanup is
+ * required).
+ *
+ * Return:
+ * * 0 on success, or
+ * * Any error returned by devm_platform_ioremap_resource().
+ */
+static int
+pvr_device_reg_init(struct pvr_device *pvr_dev)
+{
+ struct drm_device *drm_dev = from_pvr_device(pvr_dev);
+ struct platform_device *plat_dev = to_platform_device(drm_dev->dev);
+ struct resource *regs_resource;
+ void __iomem *regs;
+ int err;
+
+ pvr_dev->regs_resource = NULL;
+ pvr_dev->regs = NULL;
+
+ regs = devm_platform_get_and_ioremap_resource(plat_dev, 0,
_resource);
+ if (IS_ERR(regs)) {
+ err = PTR_ERR(regs);
+ drm_err(drm_dev, "failed to ioremap gpu registers (err=%d)\n",
+ err);
+ return err;
+ }
+
+ pvr_dev->regs = regs;
+ pvr_dev->regs_resource = regs_resource;
+
+ return 0;
+}
+
+/**
+ * pvr_device_reg_fini() - Deinitialize kernel access to a PowerVR device's
+ * control registers.
+ * @pvr_dev: Target PowerVR device.
+ *
+ * This is essentially a no-op, since pvr_device_reg_init() already ensures
that
+ * struct pvr_device->regs is unmapped when the device is detached. This
+ * function just sets struct pvr_device->regs to %NULL.
+ */
+static __always_inline void
+pvr_device_reg_fini(struct pvr_device *pvr_dev)
+{
+ pvr_dev->regs = NULL;
+}
+
+/**
+ * pvr_device_clk_init() - Initialize clocks required by a PowerVR device
+ * @pvr_dev: Target PowerVR device.
+ *
+ * Sets struct pvr_device->core_clk, struct pvr_device->sys_clk and
+ * struct pvr_device->mem_clk.
+ *
+ * Three clocks are required by the PowerVR device: core, sys and mem. On
+ * return, this function guarantees that the clocks are in one of the following
+ * states:
+ *
+ * * All successfully initialized,
+ * * Core errored, sys and mem uninitialized,
+ * * Core deinitialized, sys errored, mem uninitialized, or
+ * * Core and sys deinitialized, mem errored.
+ *
+ * Return:
+ * * 0 on success,
+ * * Any error returned by devm_clk_get(), or
+ * * Any error returned by clk_prepare_enable().
+ */
+static int pvr_device_clk_init(struct pvr_device *pvr_dev)
+{
+ struct drm_device *drm_dev = from_pvr_device(pvr_dev);
+ struct clk *core_clk;
+ struct clk *sys_clk;
+ struct clk *mem_clk;
+ int err;
+
+ pvr_dev->core_clk = NULL;
+ pvr_dev->sys_clk = NULL;
+ pvr_dev->mem_clk = NULL;
+
+ core_clk = devm_clk_get(drm_dev->dev, "core");
+ if (IS_ERR(core_clk)) {
+ err = PTR_ERR(core_clk);
+ drm_err(drm_dev, "failed to get core clock (err=%d)\n", err);
+ goto err_out;
+ }
+
+ sys_clk = devm_clk_get(drm_dev->dev, "sys");
+ if (IS_ERR(sys_clk))
+ sys_clk = NULL;
+
+ mem_clk = devm_clk_get(drm_dev->dev, "mem");
+ if (IS_ERR(mem_clk))
+ mem_clk = NULL;
+
+ err = clk_prepare(core_clk);
+ if (err)
+ goto err_out;
+
+ if (sys_clk) {
+ err = clk_prepare(sys_clk);
+ if (err)
+ goto err_deinit_core_clk;
+ }
+
+ if (mem_clk) {
+ err = clk_prepare(mem_clk);
+ if (err)
+ goto err_deinit_sys_clk;
+ }
+
+
[PATCH 2/2] drm: Remove struct drm_driver.gem_prime_mmap
All drivers initialize this field with drm_gem_prime_mmap(). Call
the function directly and remove the field. Simplifies the code and
resolves a long-standing TODO item.
Signed-off-by: Thomas Zimmermann
---
Documentation/gpu/todo.rst | 9 -
drivers/accel/ivpu/ivpu_drv.c | 1 -
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 1 -
drivers/gpu/drm/drm_fbdev_dma.c | 6 +-
drivers/gpu/drm/drm_prime.c | 14 ++
drivers/gpu/drm/etnaviv/etnaviv_drv.c | 1 -
drivers/gpu/drm/exynos/exynos_drm_drv.c | 1 -
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c | 1 -
drivers/gpu/drm/lima/lima_drv.c | 1 -
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 1 -
drivers/gpu/drm/msm/msm_drv.c | 1 -
drivers/gpu/drm/msm/msm_drv.h | 1 -
drivers/gpu/drm/msm/msm_gem_prime.c | 5 -
drivers/gpu/drm/nouveau/nouveau_drm.c | 1 -
drivers/gpu/drm/panfrost/panfrost_drv.c | 1 -
drivers/gpu/drm/pl111/pl111_drv.c | 1 -
drivers/gpu/drm/radeon/radeon_drv.c | 1 -
drivers/gpu/drm/renesas/rcar-du/rcar_du_drv.c | 1 -
drivers/gpu/drm/rockchip/rockchip_drm_drv.c | 1 -
drivers/gpu/drm/v3d/v3d_drv.c | 1 -
drivers/gpu/drm/virtio/virtgpu_drv.c| 1 -
drivers/gpu/drm/xen/xen_drm_front.c | 1 -
include/drm/drm_drv.h | 14 --
include/drm/drm_gem_dma_helper.h| 6 ++
include/drm/drm_gem_shmem_helper.h | 1 -
include/drm/drm_gem_vram_helper.h | 1 -
26 files changed, 5 insertions(+), 69 deletions(-)
diff --git a/Documentation/gpu/todo.rst b/Documentation/gpu/todo.rst
index 68bdafa0284f5..ca1efad8c89c3 100644
--- a/Documentation/gpu/todo.rst
+++ b/Documentation/gpu/todo.rst
@@ -319,15 +319,6 @@ Contact: Daniel Vetter, Noralf Tronnes
Level: Advanced
-struct drm_gem_object_funcs
-
-GEM objects can now have a function table instead of having the callbacks on
the
-DRM driver struct. This is now the preferred way. Callbacks in drivers have
been
-converted, except for struct drm_driver.gem_prime_mmap.
-
-Level: Intermediate
-
connector register/unregister fixes
---
diff --git a/drivers/accel/ivpu/ivpu_drv.c b/drivers/accel/ivpu/ivpu_drv.c
index 2df7643b843d5..9f2b9fdcc5498 100644
--- a/drivers/accel/ivpu/ivpu_drv.c
+++ b/drivers/accel/ivpu/ivpu_drv.c
@@ -376,7 +376,6 @@ static const struct drm_driver driver = {
.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
.gem_prime_import = ivpu_gem_prime_import,
- .gem_prime_mmap = drm_gem_prime_mmap,
.ioctls = ivpu_drm_ioctls,
.num_ioctls = ARRAY_SIZE(ivpu_drm_ioctls),
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index c9a41c997c6c7..7681f79f462eb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -2809,7 +2809,6 @@ static const struct drm_driver amdgpu_kms_driver = {
.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
.gem_prime_import = amdgpu_gem_prime_import,
- .gem_prime_mmap = drm_gem_prime_mmap,
.name = DRIVER_NAME,
.desc = DRIVER_DESC,
diff --git a/drivers/gpu/drm/drm_fbdev_dma.c b/drivers/gpu/drm/drm_fbdev_dma.c
index d86773fa8ab00..8217f1ddc0075 100644
--- a/drivers/gpu/drm/drm_fbdev_dma.c
+++ b/drivers/gpu/drm/drm_fbdev_dma.c
@@ -54,12 +54,8 @@ static void drm_fbdev_dma_fb_destroy(struct fb_info *info)
static int drm_fbdev_dma_fb_mmap(struct fb_info *info, struct vm_area_struct
*vma)
{
struct drm_fb_helper *fb_helper = info->par;
- struct drm_device *dev = fb_helper->dev;
-
- if (drm_WARN_ON_ONCE(dev, !fb_helper->dev->driver->gem_prime_mmap))
- return -ENODEV;
- return fb_helper->dev->driver->gem_prime_mmap(fb_helper->buffer->gem,
vma);
+ return drm_gem_prime_mmap(fb_helper->buffer->gem, vma);
}
static const struct fb_ops drm_fbdev_dma_fb_ops = {
diff --git a/drivers/gpu/drm/drm_prime.c b/drivers/gpu/drm/drm_prime.c
index d29dafce9bb0a..6bcf324ef81c9 100644
--- a/drivers/gpu/drm/drm_prime.c
+++ b/drivers/gpu/drm/drm_prime.c
@@ -715,8 +715,6 @@ EXPORT_SYMBOL(drm_gem_dmabuf_vunmap);
* the same codepath that is used for regular GEM buffer mapping on the DRM fd.
* The fake GEM offset is added to vma->vm_pgoff and _driver->fops->mmap is
* called to set up the mapping.
- *
- * Drivers can use this as their _driver.gem_prime_mmap callback.
*/
int drm_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma)
{
@@ -772,25 +770,17 @@ EXPORT_SYMBOL(drm_gem_prime_mmap);
* @vma: virtual address
[PATCH 1/2] drm/msm: Initialize mmap offset after constructing the buffer object
Only the msm driver provides its own implementation of gem_prime_mmap
from struct drm_driver. All other drivers use the drm_gem_prime_mmap()
helper.
Initialize the mmap offset when constructing the buffer object in msm
and reduce the gem_prime_mmap code to the generic helper. Prepares
msm for the removal of struct drm_driver.gem_prime_mmap.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/msm/msm_gem.c | 8
drivers/gpu/drm/msm/msm_gem_prime.c | 10 --
2 files changed, 8 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_gem.c b/drivers/gpu/drm/msm/msm_gem.c
index 20cfd86d2b324..635744bc4765f 100644
--- a/drivers/gpu/drm/msm/msm_gem.c
+++ b/drivers/gpu/drm/msm/msm_gem.c
@@ -1234,6 +1234,10 @@ struct drm_gem_object *msm_gem_new(struct drm_device
*dev, uint32_t size, uint32
list_add_tail(_obj->node, >objects);
mutex_unlock(>obj_lock);
+ ret = drm_gem_create_mmap_offset(obj);
+ if (ret)
+ goto fail;
+
return obj;
fail:
@@ -1290,6 +1294,10 @@ struct drm_gem_object *msm_gem_import(struct drm_device
*dev,
list_add_tail(_obj->node, >objects);
mutex_unlock(>obj_lock);
+ ret = drm_gem_create_mmap_offset(obj);
+ if (ret)
+ goto fail;
+
return obj;
fail:
diff --git a/drivers/gpu/drm/msm/msm_gem_prime.c
b/drivers/gpu/drm/msm/msm_gem_prime.c
index c1d91863df055..2c846afe049e4 100644
--- a/drivers/gpu/drm/msm/msm_gem_prime.c
+++ b/drivers/gpu/drm/msm/msm_gem_prime.c
@@ -13,16 +13,6 @@
int msm_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma)
{
- int ret;
-
- /* Ensure the mmap offset is initialized. We lazily initialize it,
-* so if it has not been first mmap'd directly as a GEM object, the
-* mmap offset will not be already initialized.
-*/
- ret = drm_gem_create_mmap_offset(obj);
- if (ret)
- return ret;
-
return drm_gem_prime_mmap(obj, vma);
}
--
2.41.0
