[Patch v2 13/13] ACPI, nouveau: replace open-coded _DSM specific code with helper functions
Use helper functions to simplify _DSM related code in nouveau driver.
After analyzing the ACPI _DSM related code, I changed nouveau_optimus_dsm()
to expect a buffer and nouveau_dsm() to expect an integer only.
Signed-off-by: Jiang Liu
---
drivers/gpu/drm/nouveau/core/subdev/mxm/base.c | 48 +++-
drivers/gpu/drm/nouveau/nouveau_acpi.c | 139 +++-
2 files changed, 54 insertions(+), 133 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/core/subdev/mxm/base.c
b/drivers/gpu/drm/nouveau/core/subdev/mxm/base.c
index 1291204..13c5af8 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/mxm/base.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/mxm/base.c
@@ -87,55 +87,39 @@ mxm_shadow_dsm(struct nouveau_mxm *mxm, u8 version)
0xB8, 0x9C, 0x79, 0xB6, 0x2F, 0xD5, 0x56, 0x65
};
u32 mxms_args[] = { 0x };
- union acpi_object args[4] = {
- /* _DSM MUID */
- { .buffer.type = 3,
- .buffer.length = sizeof(muid),
- .buffer.pointer = muid,
- },
- /* spec says this can be zero to mean "highest revision", but
-* of course there's at least one bios out there which fails
-* unless you pass in exactly the version it supports..
-*/
- { .integer.type = ACPI_TYPE_INTEGER,
- .integer.value = (version & 0xf0) << 4 | (version & 0x0f),
- },
- /* MXMS function */
- { .integer.type = ACPI_TYPE_INTEGER,
- .integer.value = 0x0010,
- },
- /* Pointer to MXMS arguments */
- { .buffer.type = ACPI_TYPE_BUFFER,
- .buffer.length = sizeof(mxms_args),
- .buffer.pointer = (char *)mxms_args,
- },
+ union acpi_object argv4 = {
+ .buffer.type = ACPI_TYPE_BUFFER,
+ .buffer.length = sizeof(mxms_args),
+ .buffer.pointer = (char *)mxms_args,
};
- struct acpi_object_list list = { ARRAY_SIZE(args), args };
- struct acpi_buffer retn = { ACPI_ALLOCATE_BUFFER, NULL };
union acpi_object *obj;
acpi_handle handle;
- int ret;
+ int rev;
handle = ACPI_HANDLE(>pdev->dev);
if (!handle)
return false;
- ret = acpi_evaluate_object(handle, "_DSM", , );
- if (ret) {
- nv_debug(mxm, "DSM MXMS failed: %d\n", ret);
+ /*
+* spec says this can be zero to mean "highest revision", but
+* of course there's at least one bios out there which fails
+* unless you pass in exactly the version it supports..
+*/
+ rev = (version & 0xf0) << 4 | (version & 0x0f);
+ obj = acpi_evaluate_dsm(handle, muid, rev, 0x0010, );
+ if (!obj) {
+ nv_debug(mxm, "DSM MXMS failed\n");
return false;
}
- obj = retn.pointer;
if (obj->type == ACPI_TYPE_BUFFER) {
mxm->mxms = kmemdup(obj->buffer.pointer,
obj->buffer.length, GFP_KERNEL);
- } else
- if (obj->type == ACPI_TYPE_INTEGER) {
+ } else if (obj->type == ACPI_TYPE_INTEGER) {
nv_debug(mxm, "DSM MXMS returned 0x%llx\n", obj->integer.value);
}
- kfree(obj);
+ ACPI_FREE(obj);
return mxm->mxms != NULL;
}
#endif
diff --git a/drivers/gpu/drm/nouveau/nouveau_acpi.c
b/drivers/gpu/drm/nouveau/nouveau_acpi.c
index 03d4911..db64f25 100644
--- a/drivers/gpu/drm/nouveau/nouveau_acpi.c
+++ b/drivers/gpu/drm/nouveau/nouveau_acpi.c
@@ -77,127 +77,66 @@ static const char nouveau_op_dsm_muid[] = {
static int nouveau_optimus_dsm(acpi_handle handle, int func, int arg, uint32_t
*result)
{
- struct acpi_buffer output = { ACPI_ALLOCATE_BUFFER, NULL };
- struct acpi_object_list input;
- union acpi_object params[4];
+ int i;
union acpi_object *obj;
- int i, err;
char args_buff[4];
+ union acpi_object argv4 = {
+ .buffer.type = ACPI_TYPE_BUFFER,
+ .buffer.length = 4,
+ .buffer.pointer = args_buff
+ };
- input.count = 4;
- input.pointer = params;
- params[0].type = ACPI_TYPE_BUFFER;
- params[0].buffer.length = sizeof(nouveau_op_dsm_muid);
- params[0].buffer.pointer = (char *)nouveau_op_dsm_muid;
- params[1].type = ACPI_TYPE_INTEGER;
- params[1].integer.value = 0x0100;
- params[2].type = ACPI_TYPE_INTEGER;
- params[2].integer.value = func;
- params[3].type = ACPI_TYPE_BUFFER;
- params[3].buffer.length = 4;
/* ACPI is little endian, AABBCCDD becomes {DD,CC,BB,AA} */
for (i = 0; i < 4; i++)
args_buff[i] = (arg >> i * 8) & 0xFF;
- params[3].buffer.pointer = args_buff;
- err = acpi_evaluate_object(handle,
[Patch v2 12/13] nouveau: fix memory leak in ACPI _DSM related code
Fix memory leak in function nouveau_optimus_dsm() and nouveau_dsm().
Signed-off-by: Jiang Liu
---
drivers/gpu/drm/nouveau/nouveau_acpi.c |5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/nouveau/nouveau_acpi.c
b/drivers/gpu/drm/nouveau/nouveau_acpi.c
index 95c7404..03d4911 100644
--- a/drivers/gpu/drm/nouveau/nouveau_acpi.c
+++ b/drivers/gpu/drm/nouveau/nouveau_acpi.c
@@ -110,6 +110,7 @@ static int nouveau_optimus_dsm(acpi_handle handle, int
func, int arg, uint32_t *
if (obj->type == ACPI_TYPE_INTEGER)
if (obj->integer.value == 0x8002) {
+ kfree(output.pointer);
return -ENODEV;
}
@@ -156,8 +157,10 @@ static int nouveau_dsm(acpi_handle handle, int func, int
arg, uint32_t *result)
obj = (union acpi_object *)output.pointer;
if (obj->type == ACPI_TYPE_INTEGER)
- if (obj->integer.value == 0x8002)
+ if (obj->integer.value == 0x8002) {
+ kfree(output.pointer);
return -ENODEV;
+ }
if (obj->type == ACPI_TYPE_BUFFER) {
if (obj->buffer.length == 4 && result) {
--
1.7.10.4
[Patch v2 11/13] ACPI, i915: replace open-coded _DSM specific code with helper functions
Use helper functions to simplify _DSM related code in i915 driver.
Function intel_dsm() is used to check functions supported by ACPI _DSM
method, but it has strange check for special value 0x8002. After
digging into nouveau driver, I think the check is copied from nouveau
driver and is useless for i915 driver, so remove it.
Acked-by: Daniel Vetter
Signed-off-by: Jiang Liu
---
drivers/gpu/drm/i915/intel_acpi.c | 144 -
1 file changed, 30 insertions(+), 114 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_acpi.c
b/drivers/gpu/drm/i915/intel_acpi.c
index dfff090..1bfac94 100644
--- a/drivers/gpu/drm/i915/intel_acpi.c
+++ b/drivers/gpu/drm/i915/intel_acpi.c
@@ -12,8 +12,6 @@
#include "i915_drv.h"
#define INTEL_DSM_REVISION_ID 1 /* For Calpella anyway... */
-
-#define INTEL_DSM_FN_SUPPORTED_FUNCTIONS 0 /* No args */
#define INTEL_DSM_FN_PLATFORM_MUX_INFO 1 /* No args */
static struct intel_dsm_priv {
@@ -28,61 +26,6 @@ static const u8 intel_dsm_guid[] = {
0x0f, 0x13, 0x17, 0xb0, 0x1c, 0x2c
};
-static int intel_dsm(acpi_handle handle, int func)
-{
- struct acpi_buffer output = { ACPI_ALLOCATE_BUFFER, NULL };
- struct acpi_object_list input;
- union acpi_object params[4];
- union acpi_object *obj;
- u32 result;
- int ret = 0;
-
- input.count = 4;
- input.pointer = params;
- params[0].type = ACPI_TYPE_BUFFER;
- params[0].buffer.length = sizeof(intel_dsm_guid);
- params[0].buffer.pointer = (char *)intel_dsm_guid;
- params[1].type = ACPI_TYPE_INTEGER;
- params[1].integer.value = INTEL_DSM_REVISION_ID;
- params[2].type = ACPI_TYPE_INTEGER;
- params[2].integer.value = func;
- params[3].type = ACPI_TYPE_PACKAGE;
- params[3].package.count = 0;
- params[3].package.elements = NULL;
-
- ret = acpi_evaluate_object(handle, "_DSM", , );
- if (ret) {
- DRM_DEBUG_DRIVER("failed to evaluate _DSM: %d\n", ret);
- return ret;
- }
-
- obj = (union acpi_object *)output.pointer;
-
- result = 0;
- switch (obj->type) {
- case ACPI_TYPE_INTEGER:
- result = obj->integer.value;
- break;
-
- case ACPI_TYPE_BUFFER:
- if (obj->buffer.length == 4) {
- result = (obj->buffer.pointer[0] |
- (obj->buffer.pointer[1] << 8) |
- (obj->buffer.pointer[2] << 16) |
- (obj->buffer.pointer[3] << 24));
- break;
- }
- default:
- ret = -EINVAL;
- break;
- }
- if (result == 0x8002)
- ret = -ENODEV;
-
- kfree(output.pointer);
- return ret;
-}
-
static char *intel_dsm_port_name(u8 id)
{
switch (id) {
@@ -137,83 +80,56 @@ static char *intel_dsm_mux_type(u8 type)
static void intel_dsm_platform_mux_info(void)
{
- struct acpi_buffer output = { ACPI_ALLOCATE_BUFFER, NULL };
- struct acpi_object_list input;
- union acpi_object params[4];
- union acpi_object *pkg;
- int i, ret;
-
- input.count = 4;
- input.pointer = params;
- params[0].type = ACPI_TYPE_BUFFER;
- params[0].buffer.length = sizeof(intel_dsm_guid);
- params[0].buffer.pointer = (char *)intel_dsm_guid;
- params[1].type = ACPI_TYPE_INTEGER;
- params[1].integer.value = INTEL_DSM_REVISION_ID;
- params[2].type = ACPI_TYPE_INTEGER;
- params[2].integer.value = INTEL_DSM_FN_PLATFORM_MUX_INFO;
- params[3].type = ACPI_TYPE_PACKAGE;
- params[3].package.count = 0;
- params[3].package.elements = NULL;
-
- ret = acpi_evaluate_object(intel_dsm_priv.dhandle, "_DSM", ,
- );
- if (ret) {
- DRM_DEBUG_DRIVER("failed to evaluate _DSM: %d\n", ret);
- goto out;
+ int i;
+ union acpi_object *pkg, *connector_count;
+
+ pkg = acpi_evaluate_dsm_typed(intel_dsm_priv.dhandle, intel_dsm_guid,
+ INTEL_DSM_REVISION_ID, INTEL_DSM_FN_PLATFORM_MUX_INFO,
+ NULL, ACPI_TYPE_PACKAGE);
+ if (!pkg) {
+ DRM_DEBUG_DRIVER("failed to evaluate _DSM\n");
+ return;
}
- pkg = (union acpi_object *)output.pointer;
-
- if (pkg->type == ACPI_TYPE_PACKAGE) {
- union acpi_object *connector_count = >package.elements[0];
- DRM_DEBUG_DRIVER("MUX info connectors: %lld\n",
- (unsigned long long)connector_count->integer.value);
- for (i = 1; i < pkg->package.count; i++) {
- union acpi_object *obj = >package.elements[i];
- union acpi_object *connector_id =
- >package.elements[0];
- union acpi_object
[PATCH 18/18] drm/radeon: enable dpm by default on CI APUs
Dynamic power mangement works reliably now, so enable it by default. Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/radeon_pm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/radeon/radeon_pm.c b/drivers/gpu/drm/radeon/radeon_pm.c index 422afc1..c0ff200 100644 --- a/drivers/gpu/drm/radeon/radeon_pm.c +++ b/drivers/gpu/drm/radeon/radeon_pm.c @@ -1230,8 +1230,6 @@ int radeon_pm_init(struct radeon_device *rdev) case CHIP_RS780: case CHIP_RS880: case CHIP_CAYMAN: - case CHIP_KABINI: - case CHIP_KAVERI: /* DPM requires the RLC, RV770+ dGPU requires SMC */ if (!rdev->rlc_fw) rdev->pm.pm_method = PM_METHOD_PROFILE; @@ -1266,6 +1264,8 @@ int radeon_pm_init(struct radeon_device *rdev) case CHIP_OLAND: case CHIP_HAINAN: case CHIP_BONAIRE: + case CHIP_KABINI: + case CHIP_KAVERI: case CHIP_HAWAII: /* DPM requires the RLC, RV770+ dGPU requires SMC */ if (!rdev->rlc_fw) -- 1.8.3.1
[PATCH 17/18] drm/radeon: enable dpm by default on CI dGPUs
Dynamic power mangement works reliably now, so enable it by default. Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/radeon_pm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/radeon/radeon_pm.c b/drivers/gpu/drm/radeon/radeon_pm.c index 933ada0..422afc1 100644 --- a/drivers/gpu/drm/radeon/radeon_pm.c +++ b/drivers/gpu/drm/radeon/radeon_pm.c @@ -1230,10 +1230,8 @@ int radeon_pm_init(struct radeon_device *rdev) case CHIP_RS780: case CHIP_RS880: case CHIP_CAYMAN: - case CHIP_BONAIRE: case CHIP_KABINI: case CHIP_KAVERI: - case CHIP_HAWAII: /* DPM requires the RLC, RV770+ dGPU requires SMC */ if (!rdev->rlc_fw) rdev->pm.pm_method = PM_METHOD_PROFILE; @@ -1267,6 +1265,8 @@ int radeon_pm_init(struct radeon_device *rdev) case CHIP_VERDE: case CHIP_OLAND: case CHIP_HAINAN: + case CHIP_BONAIRE: + case CHIP_HAWAII: /* DPM requires the RLC, RV770+ dGPU requires SMC */ if (!rdev->rlc_fw) rdev->pm.pm_method = PM_METHOD_PROFILE; -- 1.8.3.1
[PATCH 16/18] drm/radeon: enable gfx cgcg on CIK APUs
Enable coarse grained clockgating. This works properly now that smc is initialized earlier than the rlc and cp. Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/radeon_asic.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c index e7ad54f..534aae0 100644 --- a/drivers/gpu/drm/radeon/radeon_asic.c +++ b/drivers/gpu/drm/radeon/radeon_asic.c @@ -2504,7 +2504,7 @@ int radeon_asic_init(struct radeon_device *rdev) rdev->cg_flags = RADEON_CG_SUPPORT_GFX_MGCG | RADEON_CG_SUPPORT_GFX_MGLS | - /*RADEON_CG_SUPPORT_GFX_CGCG |*/ + RADEON_CG_SUPPORT_GFX_CGCG | RADEON_CG_SUPPORT_GFX_CGLS | RADEON_CG_SUPPORT_GFX_CGTS | RADEON_CG_SUPPORT_GFX_CGTS_LS | @@ -2532,7 +2532,7 @@ int radeon_asic_init(struct radeon_device *rdev) rdev->cg_flags = RADEON_CG_SUPPORT_GFX_MGCG | RADEON_CG_SUPPORT_GFX_MGLS | - /*RADEON_CG_SUPPORT_GFX_CGCG |*/ + RADEON_CG_SUPPORT_GFX_CGCG | RADEON_CG_SUPPORT_GFX_CGLS | RADEON_CG_SUPPORT_GFX_CGTS | RADEON_CG_SUPPORT_GFX_CGTS_LS | -- 1.8.3.1
[PATCH 15/18] drm/radeon: enable gfx cgcg on CIK dGPUs
Enable coarse grained clockgating on CIK dGPUs. This works properly now that smc is initialized earlier than the rlc and cp. Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/radeon_asic.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c index b8ef84c..e7ad54f 100644 --- a/drivers/gpu/drm/radeon/radeon_asic.c +++ b/drivers/gpu/drm/radeon/radeon_asic.c @@ -2460,7 +2460,7 @@ int radeon_asic_init(struct radeon_device *rdev) rdev->cg_flags = RADEON_CG_SUPPORT_GFX_MGCG | RADEON_CG_SUPPORT_GFX_MGLS | - /*RADEON_CG_SUPPORT_GFX_CGCG |*/ + RADEON_CG_SUPPORT_GFX_CGCG | RADEON_CG_SUPPORT_GFX_CGLS | RADEON_CG_SUPPORT_GFX_CGTS | RADEON_CG_SUPPORT_GFX_CGTS_LS | @@ -2479,7 +2479,7 @@ int radeon_asic_init(struct radeon_device *rdev) rdev->cg_flags = RADEON_CG_SUPPORT_GFX_MGCG | RADEON_CG_SUPPORT_GFX_MGLS | - /*RADEON_CG_SUPPORT_GFX_CGCG |*/ + RADEON_CG_SUPPORT_GFX_CGCG | RADEON_CG_SUPPORT_GFX_CGLS | RADEON_CG_SUPPORT_GFX_CGTS | RADEON_CG_SUPPORT_GFX_CP_LS | -- 1.8.3.1
[PATCH 14/18] drm/radeon/pm: move pm handling into the asic specific code
We need more control over the ordering of dpm init with
respect to the rest of the asic. Specifically, the SMC
has to be initialized before the rlc and cg/pg. The pm
code currently initializes late in the driver, but we need
it to happen much earlier so move pm handling into the asic
specific callbacks.
This makes dpm more reliable and makes clockgating work
properly on CIK parts and should help on SI parts as well.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/btc_dpm.c| 5 +
drivers/gpu/drm/radeon/ci_dpm.c | 6 ++
drivers/gpu/drm/radeon/cik.c| 11 +--
drivers/gpu/drm/radeon/evergreen.c | 9 -
drivers/gpu/drm/radeon/ni.c | 9 -
drivers/gpu/drm/radeon/ni_dpm.c | 6 ++
drivers/gpu/drm/radeon/r100.c | 7 +++
drivers/gpu/drm/radeon/r300.c | 7 +++
drivers/gpu/drm/radeon/r420.c | 7 +++
drivers/gpu/drm/radeon/r520.c | 5 +
drivers/gpu/drm/radeon/r600.c | 7 +++
drivers/gpu/drm/radeon/radeon_device.c | 14 +++---
drivers/gpu/drm/radeon/radeon_display.c | 17 +
drivers/gpu/drm/radeon/radeon_pm.c | 11 +++
drivers/gpu/drm/radeon/rs400.c | 7 +++
drivers/gpu/drm/radeon/rs600.c | 7 +++
drivers/gpu/drm/radeon/rs690.c | 7 +++
drivers/gpu/drm/radeon/rv515.c | 7 +++
drivers/gpu/drm/radeon/rv770.c | 7 +++
drivers/gpu/drm/radeon/si.c | 19 ++-
drivers/gpu/drm/radeon/si_dpm.c | 7 +++
21 files changed, 158 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/radeon/btc_dpm.c b/drivers/gpu/drm/radeon/btc_dpm.c
index 2eb985a..0fbd36f 100644
--- a/drivers/gpu/drm/radeon/btc_dpm.c
+++ b/drivers/gpu/drm/radeon/btc_dpm.c
@@ -49,6 +49,7 @@ struct rv7xx_ps *rv770_get_ps(struct radeon_ps *rps);
struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev);
struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev);
+extern int ni_mc_load_microcode(struct radeon_device *rdev);
//* BARTS **//
static const u32 barts_cgcg_cgls_default[] =
@@ -2561,7 +2562,11 @@ void btc_dpm_disable(struct radeon_device *rdev)
void btc_dpm_setup_asic(struct radeon_device *rdev)
{
struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
+ int r;
+ r = ni_mc_load_microcode(rdev);
+ if (r)
+ DRM_ERROR("Failed to load MC firmware!\n");
rv770_get_memory_type(rdev);
rv740_read_clock_registers(rdev);
btc_read_arb_registers(rdev);
diff --git a/drivers/gpu/drm/radeon/ci_dpm.c b/drivers/gpu/drm/radeon/ci_dpm.c
index 6eab12d..a3c4711 100644
--- a/drivers/gpu/drm/radeon/ci_dpm.c
+++ b/drivers/gpu/drm/radeon/ci_dpm.c
@@ -171,6 +171,7 @@ extern void si_trim_voltage_table_to_fit_state_table(struct
radeon_device *rdev,
struct atom_voltage_table
*voltage_table);
extern void cik_enter_rlc_safe_mode(struct radeon_device *rdev);
extern void cik_exit_rlc_safe_mode(struct radeon_device *rdev);
+extern int ci_mc_load_microcode(struct radeon_device *rdev);
static int ci_get_std_voltage_value_sidd(struct radeon_device *rdev,
struct atom_voltage_table_entry
*voltage_table,
@@ -4547,6 +4548,11 @@ void ci_dpm_post_set_power_state(struct radeon_device
*rdev)
void ci_dpm_setup_asic(struct radeon_device *rdev)
{
+ int r;
+
+ r = ci_mc_load_microcode(rdev);
+ if (r)
+ DRM_ERROR("Failed to load MC firmware!\n");
ci_read_clock_registers(rdev);
ci_get_memory_type(rdev);
ci_enable_acpi_power_management(rdev);
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index 4ddc3e5..25a6ef6 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -1697,7 +1697,7 @@ static void cik_srbm_select(struct radeon_device *rdev,
* Load the GDDR MC ucode into the hw (CIK).
* Returns 0 on success, error on failure.
*/
-static int ci_mc_load_microcode(struct radeon_device *rdev)
+int ci_mc_load_microcode(struct radeon_device *rdev)
{
const __be32 *fw_data;
u32 running, blackout = 0;
@@ -7501,7 +7501,7 @@ static int cik_startup(struct radeon_device *rdev)
cik_mc_program(rdev);
- if (!(rdev->flags & RADEON_IS_IGP)) {
+ if (!(rdev->flags & RADEON_IS_IGP) && !rdev->pm.dpm_enabled) {
r = ci_mc_load_microcode(rdev);
if (r) {
DRM_ERROR("Failed to load MC firmware!\n");
@@ -7710,6 +7710,8 @@ int cik_resume(struct radeon_device *rdev)
/* init golden registers */
cik_init_golden_registers(rdev);
+ radeon_pm_resume(rdev);
+
rdev->accel_working = true;
r = cik_startup(rdev);
if (r) {
@@ -7733,6 +7735,7 @@ int
[PATCH 13/18] drm/radeon/dpm: switch on new late_enable callback
Right now it's called right after enable, but after
reworking the dpm init order, it will get called later
to accomodate loading the smc early, but enabling
thermal interrupts and block powergating later after
the ring tests are complete.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/btc_dpm.c | 15 ---
drivers/gpu/drm/radeon/ci_dpm.c | 21 -
drivers/gpu/drm/radeon/cypress_dpm.c | 15 ---
drivers/gpu/drm/radeon/kv_dpm.c | 17 ---
drivers/gpu/drm/radeon/ni_dpm.c | 15 ---
drivers/gpu/drm/radeon/r600_dpm.c| 4 +-
drivers/gpu/drm/radeon/r600_dpm.h| 2 -
drivers/gpu/drm/radeon/radeon_pm.c | 87
drivers/gpu/drm/radeon/rs780_dpm.c | 8
drivers/gpu/drm/radeon/rv6xx_dpm.c | 10 -
drivers/gpu/drm/radeon/rv770_dpm.c | 19 +---
drivers/gpu/drm/radeon/rv770_dpm.h | 4 --
drivers/gpu/drm/radeon/si_dpm.c | 15 ---
drivers/gpu/drm/radeon/sumo_dpm.c| 13 --
drivers/gpu/drm/radeon/trinity_dpm.c | 13 --
15 files changed, 53 insertions(+), 205 deletions(-)
diff --git a/drivers/gpu/drm/radeon/btc_dpm.c b/drivers/gpu/drm/radeon/btc_dpm.c
index 9b6950d..2eb985a 100644
--- a/drivers/gpu/drm/radeon/btc_dpm.c
+++ b/drivers/gpu/drm/radeon/btc_dpm.c
@@ -2510,21 +2510,6 @@ int btc_dpm_enable(struct radeon_device *rdev)
if (eg_pi->ls_clock_gating)
btc_ls_clock_gating_enable(rdev, true);
- if (rdev->irq.installed &&
- r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
- PPSMC_Result result;
-
- ret = rv770_set_thermal_temperature_range(rdev,
R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
- if (ret)
- return ret;
- rdev->irq.dpm_thermal = true;
- radeon_irq_set(rdev);
- result = rv770_send_msg_to_smc(rdev,
PPSMC_MSG_EnableThermalInterrupt);
-
- if (result != PPSMC_Result_OK)
- DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
- }
-
rv770_enable_auto_throttle_source(rdev,
RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
btc_init_stutter_mode(rdev);
diff --git a/drivers/gpu/drm/radeon/ci_dpm.c b/drivers/gpu/drm/radeon/ci_dpm.c
index 13ee5af..6eab12d 100644
--- a/drivers/gpu/drm/radeon/ci_dpm.c
+++ b/drivers/gpu/drm/radeon/ci_dpm.c
@@ -4656,30 +4656,9 @@ int ci_dpm_enable(struct radeon_device *rdev)
DRM_ERROR("ci_enable_power_containment failed\n");
return ret;
}
- if (rdev->irq.installed &&
- r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
-#if 0
- PPSMC_Result result;
-#endif
- ret = ci_set_thermal_temperature_range(rdev,
R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
- if (ret) {
- DRM_ERROR("ci_set_thermal_temperature_range failed\n");
- return ret;
- }
- rdev->irq.dpm_thermal = true;
- radeon_irq_set(rdev);
-#if 0
- result = ci_send_msg_to_smc(rdev,
PPSMC_MSG_EnableThermalInterrupt);
-
- if (result != PPSMC_Result_OK)
- DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
-#endif
- }
ci_enable_auto_throttle_source(rdev,
RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
- ci_dpm_powergate_uvd(rdev, true);
-
ci_update_current_ps(rdev, boot_ps);
return 0;
diff --git a/drivers/gpu/drm/radeon/cypress_dpm.c
b/drivers/gpu/drm/radeon/cypress_dpm.c
index 920e1e4..cf783fc 100644
--- a/drivers/gpu/drm/radeon/cypress_dpm.c
+++ b/drivers/gpu/drm/radeon/cypress_dpm.c
@@ -1905,21 +1905,6 @@ int cypress_dpm_enable(struct radeon_device *rdev)
if (pi->mg_clock_gating)
cypress_mg_clock_gating_enable(rdev, true);
- if (rdev->irq.installed &&
- r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
- PPSMC_Result result;
-
- ret = rv770_set_thermal_temperature_range(rdev,
R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
- if (ret)
- return ret;
- rdev->irq.dpm_thermal = true;
- radeon_irq_set(rdev);
- result = rv770_send_msg_to_smc(rdev,
PPSMC_MSG_EnableThermalInterrupt);
-
- if (result != PPSMC_Result_OK)
- DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
- }
-
rv770_enable_auto_throttle_source(rdev,
RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
return 0;
diff --git a/drivers/gpu/drm/radeon/kv_dpm.c b/drivers/gpu/drm/radeon/kv_dpm.c
index eced979..b6e01d5 100644
--- a/drivers/gpu/drm/radeon/kv_dpm.c
+++ b/drivers/gpu/drm/radeon/kv_dpm.c
@@ -1210,29 +1210,12 @@ int kv_dpm_enable(struct radeon_device *rdev)
kv_reset_acp_boot_level(rdev);
- if (rdev->irq.installed &&
-
[PATCH 12/18] drm/radeon/dpm: add late_enable for KB/KV
Make sure interrupts are enabled
before we enable thermal interrupts.
Also, don't powergate uvd, etc. until after
the ring tests.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/kv_dpm.c | 24
drivers/gpu/drm/radeon/radeon_asic.c | 1 +
drivers/gpu/drm/radeon/radeon_asic.h | 1 +
3 files changed, 26 insertions(+)
diff --git a/drivers/gpu/drm/radeon/kv_dpm.c b/drivers/gpu/drm/radeon/kv_dpm.c
index a0e20eb..eced979 100644
--- a/drivers/gpu/drm/radeon/kv_dpm.c
+++ b/drivers/gpu/drm/radeon/kv_dpm.c
@@ -1238,6 +1238,30 @@ int kv_dpm_enable(struct radeon_device *rdev)
return ret;
}
+int kv_dpm_late_enable(struct radeon_device *rdev)
+{
+ int ret;
+
+ if (rdev->irq.installed &&
+ r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
+ ret = kv_set_thermal_temperature_range(rdev,
R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
+ if (ret) {
+ DRM_ERROR("kv_set_thermal_temperature_range failed\n");
+ return ret;
+ }
+ rdev->irq.dpm_thermal = true;
+ radeon_irq_set(rdev);
+ }
+
+ /* powerdown unused blocks for now */
+ kv_dpm_powergate_acp(rdev, true);
+ kv_dpm_powergate_samu(rdev, true);
+ kv_dpm_powergate_vce(rdev, true);
+ kv_dpm_powergate_uvd(rdev, true);
+
+ return ret;
+}
+
void kv_dpm_disable(struct radeon_device *rdev)
{
kv_smc_bapm_enable(rdev, false);
diff --git a/drivers/gpu/drm/radeon/radeon_asic.c
b/drivers/gpu/drm/radeon/radeon_asic.c
index 9c9a407..b8ef84c 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.c
+++ b/drivers/gpu/drm/radeon/radeon_asic.c
@@ -2169,6 +2169,7 @@ static struct radeon_asic kv_asic = {
.init = _dpm_init,
.setup_asic = _dpm_setup_asic,
.enable = _dpm_enable,
+ .late_enable = _dpm_late_enable,
.disable = _dpm_disable,
.pre_set_power_state = _dpm_pre_set_power_state,
.set_power_state = _dpm_set_power_state,
diff --git a/drivers/gpu/drm/radeon/radeon_asic.h
b/drivers/gpu/drm/radeon/radeon_asic.h
index 095a4fa..cb5ca21 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.h
+++ b/drivers/gpu/drm/radeon/radeon_asic.h
@@ -776,6 +776,7 @@ void ci_dpm_powergate_uvd(struct radeon_device *rdev, bool
gate);
int kv_dpm_init(struct radeon_device *rdev);
int kv_dpm_enable(struct radeon_device *rdev);
+int kv_dpm_late_enable(struct radeon_device *rdev);
void kv_dpm_disable(struct radeon_device *rdev);
int kv_dpm_pre_set_power_state(struct radeon_device *rdev);
int kv_dpm_set_power_state(struct radeon_device *rdev);
--
1.8.3.1
[PATCH 11/18] drm/radeon/dpm: add late_enable for CI
Make sure interrupts are enabled
before we enable thermal interrupts.
Also, don't powergate uvd until after
the ring tests.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/ci_dpm.c | 29 +
drivers/gpu/drm/radeon/radeon_asic.c | 1 +
drivers/gpu/drm/radeon/radeon_asic.h | 1 +
3 files changed, 31 insertions(+)
diff --git a/drivers/gpu/drm/radeon/ci_dpm.c b/drivers/gpu/drm/radeon/ci_dpm.c
index f891fc0..13ee5af 100644
--- a/drivers/gpu/drm/radeon/ci_dpm.c
+++ b/drivers/gpu/drm/radeon/ci_dpm.c
@@ -4685,6 +4685,35 @@ int ci_dpm_enable(struct radeon_device *rdev)
return 0;
}
+int ci_dpm_late_enable(struct radeon_device *rdev)
+{
+ int ret;
+
+ if (rdev->irq.installed &&
+ r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
+#if 0
+ PPSMC_Result result;
+#endif
+ ret = ci_set_thermal_temperature_range(rdev,
R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
+ if (ret) {
+ DRM_ERROR("ci_set_thermal_temperature_range failed\n");
+ return ret;
+ }
+ rdev->irq.dpm_thermal = true;
+ radeon_irq_set(rdev);
+#if 0
+ result = ci_send_msg_to_smc(rdev,
PPSMC_MSG_EnableThermalInterrupt);
+
+ if (result != PPSMC_Result_OK)
+ DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
+#endif
+ }
+
+ ci_dpm_powergate_uvd(rdev, true);
+
+ return 0;
+}
+
void ci_dpm_disable(struct radeon_device *rdev)
{
struct ci_power_info *pi = ci_get_pi(rdev);
diff --git a/drivers/gpu/drm/radeon/radeon_asic.c
b/drivers/gpu/drm/radeon/radeon_asic.c
index 23df62f..9c9a407 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.c
+++ b/drivers/gpu/drm/radeon/radeon_asic.c
@@ -2067,6 +2067,7 @@ static struct radeon_asic ci_asic = {
.init = _dpm_init,
.setup_asic = _dpm_setup_asic,
.enable = _dpm_enable,
+ .late_enable = _dpm_late_enable,
.disable = _dpm_disable,
.pre_set_power_state = _dpm_pre_set_power_state,
.set_power_state = _dpm_set_power_state,
diff --git a/drivers/gpu/drm/radeon/radeon_asic.h
b/drivers/gpu/drm/radeon/radeon_asic.h
index 9489ee3..095a4fa 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.h
+++ b/drivers/gpu/drm/radeon/radeon_asic.h
@@ -755,6 +755,7 @@ int kv_get_temp(struct radeon_device *rdev);
int ci_dpm_init(struct radeon_device *rdev);
int ci_dpm_enable(struct radeon_device *rdev);
+int ci_dpm_late_enable(struct radeon_device *rdev);
void ci_dpm_disable(struct radeon_device *rdev);
int ci_dpm_pre_set_power_state(struct radeon_device *rdev);
int ci_dpm_set_power_state(struct radeon_device *rdev);
--
1.8.3.1
[PATCH 10/18] drm/radeon/dpm: add late_enable for SI
Make sure interrupts are enabled
before we enable thermal interrupts.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/radeon_asic.c | 1 +
drivers/gpu/drm/radeon/radeon_asic.h | 1 +
drivers/gpu/drm/radeon/si_dpm.c | 22 ++
3 files changed, 24 insertions(+)
diff --git a/drivers/gpu/drm/radeon/radeon_asic.c
b/drivers/gpu/drm/radeon/radeon_asic.c
index 2011a7e..23df62f 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.c
+++ b/drivers/gpu/drm/radeon/radeon_asic.c
@@ -1921,6 +1921,7 @@ static struct radeon_asic si_asic = {
.init = _dpm_init,
.setup_asic = _dpm_setup_asic,
.enable = _dpm_enable,
+ .late_enable = _dpm_late_enable,
.disable = _dpm_disable,
.pre_set_power_state = _dpm_pre_set_power_state,
.set_power_state = _dpm_set_power_state,
diff --git a/drivers/gpu/drm/radeon/radeon_asic.h
b/drivers/gpu/drm/radeon/radeon_asic.h
index 597daec..9489ee3 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.h
+++ b/drivers/gpu/drm/radeon/radeon_asic.h
@@ -673,6 +673,7 @@ int si_get_temp(struct radeon_device *rdev);
int si_dpm_init(struct radeon_device *rdev);
void si_dpm_setup_asic(struct radeon_device *rdev);
int si_dpm_enable(struct radeon_device *rdev);
+int si_dpm_late_enable(struct radeon_device *rdev);
void si_dpm_disable(struct radeon_device *rdev);
int si_dpm_pre_set_power_state(struct radeon_device *rdev);
int si_dpm_set_power_state(struct radeon_device *rdev);
diff --git a/drivers/gpu/drm/radeon/si_dpm.c b/drivers/gpu/drm/radeon/si_dpm.c
index 2d0e94a..1c547b0 100644
--- a/drivers/gpu/drm/radeon/si_dpm.c
+++ b/drivers/gpu/drm/radeon/si_dpm.c
@@ -5912,6 +5912,28 @@ int si_dpm_enable(struct radeon_device *rdev)
return 0;
}
+int si_dpm_late_enable(struct radeon_device *rdev)
+{
+ int ret;
+
+ if (rdev->irq.installed &&
+ r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
+ PPSMC_Result result;
+
+ ret = si_set_thermal_temperature_range(rdev,
R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
+ if (ret)
+ return ret;
+ rdev->irq.dpm_thermal = true;
+ radeon_irq_set(rdev);
+ result = si_send_msg_to_smc(rdev,
PPSMC_MSG_EnableThermalInterrupt);
+
+ if (result != PPSMC_Result_OK)
+ DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
+ }
+
+ return 0;
+}
+
void si_dpm_disable(struct radeon_device *rdev)
{
struct rv7xx_power_info *pi = rv770_get_pi(rdev);
--
1.8.3.1
[PATCH 09/18] drm/radeon/dpm: add late_enable for trinity
Need to wait to enable cg and pg until after
ring tests. Also make sure interrupts are enabled
before we enable thermal interrupts.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/radeon_asic.c | 1 +
drivers/gpu/drm/radeon/radeon_asic.h | 1 +
drivers/gpu/drm/radeon/trinity_dpm.c | 22 ++
3 files changed, 24 insertions(+)
diff --git a/drivers/gpu/drm/radeon/radeon_asic.c
b/drivers/gpu/drm/radeon/radeon_asic.c
index 236afdd..2011a7e 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.c
+++ b/drivers/gpu/drm/radeon/radeon_asic.c
@@ -1790,6 +1790,7 @@ static struct radeon_asic trinity_asic = {
.init = _dpm_init,
.setup_asic = _dpm_setup_asic,
.enable = _dpm_enable,
+ .late_enable = _dpm_late_enable,
.disable = _dpm_disable,
.pre_set_power_state = _dpm_pre_set_power_state,
.set_power_state = _dpm_set_power_state,
diff --git a/drivers/gpu/drm/radeon/radeon_asic.h
b/drivers/gpu/drm/radeon/radeon_asic.h
index 1e7d669..597daec 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.h
+++ b/drivers/gpu/drm/radeon/radeon_asic.h
@@ -613,6 +613,7 @@ int ni_dpm_force_performance_level(struct radeon_device
*rdev,
bool ni_dpm_vblank_too_short(struct radeon_device *rdev);
int trinity_dpm_init(struct radeon_device *rdev);
int trinity_dpm_enable(struct radeon_device *rdev);
+int trinity_dpm_late_enable(struct radeon_device *rdev);
void trinity_dpm_disable(struct radeon_device *rdev);
int trinity_dpm_pre_set_power_state(struct radeon_device *rdev);
int trinity_dpm_set_power_state(struct radeon_device *rdev);
diff --git a/drivers/gpu/drm/radeon/trinity_dpm.c
b/drivers/gpu/drm/radeon/trinity_dpm.c
index d700698..ee0ce0a 100644
--- a/drivers/gpu/drm/radeon/trinity_dpm.c
+++ b/drivers/gpu/drm/radeon/trinity_dpm.c
@@ -1121,6 +1121,28 @@ int trinity_dpm_enable(struct radeon_device *rdev)
return 0;
}
+int trinity_dpm_late_enable(struct radeon_device *rdev)
+{
+ int ret;
+
+ trinity_acquire_mutex(rdev);
+ trinity_enable_clock_power_gating(rdev);
+
+ if (rdev->irq.installed &&
+ r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
+ ret = trinity_set_thermal_temperature_range(rdev,
R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
+ if (ret) {
+ trinity_release_mutex(rdev);
+ return ret;
+ }
+ rdev->irq.dpm_thermal = true;
+ radeon_irq_set(rdev);
+ }
+ trinity_release_mutex(rdev);
+
+ return 0;
+}
+
void trinity_dpm_disable(struct radeon_device *rdev)
{
trinity_acquire_mutex(rdev);
--
1.8.3.1
[PATCH 08/18] drm/radeon/dpm: add late_enable for sumo
Need to wait to enable cg and pg until after
ring tests. Also make sure interrupts are enabled
before we enable thermal interrupts.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/radeon_asic.c | 1 +
drivers/gpu/drm/radeon/radeon_asic.h | 1 +
drivers/gpu/drm/radeon/sumo_dpm.c| 20
3 files changed, 22 insertions(+)
diff --git a/drivers/gpu/drm/radeon/radeon_asic.c
b/drivers/gpu/drm/radeon/radeon_asic.c
index 9c047b8..236afdd 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.c
+++ b/drivers/gpu/drm/radeon/radeon_asic.c
@@ -1453,6 +1453,7 @@ static struct radeon_asic sumo_asic = {
.init = _dpm_init,
.setup_asic = _dpm_setup_asic,
.enable = _dpm_enable,
+ .late_enable = _dpm_late_enable,
.disable = _dpm_disable,
.pre_set_power_state = _dpm_pre_set_power_state,
.set_power_state = _dpm_set_power_state,
diff --git a/drivers/gpu/drm/radeon/radeon_asic.h
b/drivers/gpu/drm/radeon/radeon_asic.h
index 85e55c1..1e7d669 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.h
+++ b/drivers/gpu/drm/radeon/radeon_asic.h
@@ -547,6 +547,7 @@ u32 btc_dpm_get_mclk(struct radeon_device *rdev, bool low);
bool btc_dpm_vblank_too_short(struct radeon_device *rdev);
int sumo_dpm_init(struct radeon_device *rdev);
int sumo_dpm_enable(struct radeon_device *rdev);
+int sumo_dpm_late_enable(struct radeon_device *rdev);
void sumo_dpm_disable(struct radeon_device *rdev);
int sumo_dpm_pre_set_power_state(struct radeon_device *rdev);
int sumo_dpm_set_power_state(struct radeon_device *rdev);
diff --git a/drivers/gpu/drm/radeon/sumo_dpm.c
b/drivers/gpu/drm/radeon/sumo_dpm.c
index 96ea6db8..b63640f 100644
--- a/drivers/gpu/drm/radeon/sumo_dpm.c
+++ b/drivers/gpu/drm/radeon/sumo_dpm.c
@@ -1247,6 +1247,26 @@ int sumo_dpm_enable(struct radeon_device *rdev)
return 0;
}
+int sumo_dpm_late_enable(struct radeon_device *rdev)
+{
+ int ret;
+
+ ret = sumo_enable_clock_power_gating(rdev);
+ if (ret)
+ return ret;
+
+ if (rdev->irq.installed &&
+ r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
+ ret = sumo_set_thermal_temperature_range(rdev,
R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
+ if (ret)
+ return ret;
+ rdev->irq.dpm_thermal = true;
+ radeon_irq_set(rdev);
+ }
+
+ return 0;
+}
+
void sumo_dpm_disable(struct radeon_device *rdev)
{
struct sumo_power_info *pi = sumo_get_pi(rdev);
--
1.8.3.1
[PATCH 07/18] drm/radeon/dpm: add late_enable for rv7xx-NI
Make sure interrupts are enabled
before we enable thermal interrupts.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/radeon_asic.c | 4
drivers/gpu/drm/radeon/radeon_asic.h | 1 +
drivers/gpu/drm/radeon/rv770_dpm.c | 22 ++
3 files changed, 27 insertions(+)
diff --git a/drivers/gpu/drm/radeon/radeon_asic.c
b/drivers/gpu/drm/radeon/radeon_asic.c
index a38ce4c..9c047b8 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.c
+++ b/drivers/gpu/drm/radeon/radeon_asic.c
@@ -1241,6 +1241,7 @@ static struct radeon_asic rv770_asic = {
.init = _dpm_init,
.setup_asic = _dpm_setup_asic,
.enable = _dpm_enable,
+ .late_enable = _dpm_late_enable,
.disable = _dpm_disable,
.pre_set_power_state = _dpm_pre_set_power_state,
.set_power_state = _dpm_set_power_state,
@@ -1359,6 +1360,7 @@ static struct radeon_asic evergreen_asic = {
.init = _dpm_init,
.setup_asic = _dpm_setup_asic,
.enable = _dpm_enable,
+ .late_enable = _dpm_late_enable,
.disable = _dpm_disable,
.pre_set_power_state = _dpm_pre_set_power_state,
.set_power_state = _dpm_set_power_state,
@@ -1542,6 +1544,7 @@ static struct radeon_asic btc_asic = {
.init = _dpm_init,
.setup_asic = _dpm_setup_asic,
.enable = _dpm_enable,
+ .late_enable = _dpm_late_enable,
.disable = _dpm_disable,
.pre_set_power_state = _dpm_pre_set_power_state,
.set_power_state = _dpm_set_power_state,
@@ -1685,6 +1688,7 @@ static struct radeon_asic cayman_asic = {
.init = _dpm_init,
.setup_asic = _dpm_setup_asic,
.enable = _dpm_enable,
+ .late_enable = _dpm_late_enable,
.disable = _dpm_disable,
.pre_set_power_state = _dpm_pre_set_power_state,
.set_power_state = _dpm_set_power_state,
diff --git a/drivers/gpu/drm/radeon/radeon_asic.h
b/drivers/gpu/drm/radeon/radeon_asic.h
index 438839f..85e55c1 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.h
+++ b/drivers/gpu/drm/radeon/radeon_asic.h
@@ -455,6 +455,7 @@ int rv770_get_temp(struct radeon_device *rdev);
/* rv7xx pm */
int rv770_dpm_init(struct radeon_device *rdev);
int rv770_dpm_enable(struct radeon_device *rdev);
+int rv770_dpm_late_enable(struct radeon_device *rdev);
void rv770_dpm_disable(struct radeon_device *rdev);
int rv770_dpm_set_power_state(struct radeon_device *rdev);
void rv770_dpm_setup_asic(struct radeon_device *rdev);
diff --git a/drivers/gpu/drm/radeon/rv770_dpm.c
b/drivers/gpu/drm/radeon/rv770_dpm.c
index 374499d..5d6188f 100644
--- a/drivers/gpu/drm/radeon/rv770_dpm.c
+++ b/drivers/gpu/drm/radeon/rv770_dpm.c
@@ -1986,6 +1986,28 @@ int rv770_dpm_enable(struct radeon_device *rdev)
return 0;
}
+int rv770_dpm_late_enable(struct radeon_device *rdev)
+{
+ int ret;
+
+ if (rdev->irq.installed &&
+ r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
+ PPSMC_Result result;
+
+ ret = rv770_set_thermal_temperature_range(rdev,
R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
+ if (ret)
+ return ret;
+ rdev->irq.dpm_thermal = true;
+ radeon_irq_set(rdev);
+ result = rv770_send_msg_to_smc(rdev,
PPSMC_MSG_EnableThermalInterrupt);
+
+ if (result != PPSMC_Result_OK)
+ DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
+ }
+
+ return 0;
+}
+
void rv770_dpm_disable(struct radeon_device *rdev)
{
struct rv7xx_power_info *pi = rv770_get_pi(rdev);
--
1.8.3.1
[PATCH 06/18] drm/radeon/dpm: add late_enable for rs780/rs880/rv6xx
Make sure interrupts are enabled before we enable
thermal interrupts.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/r600_dpm.c| 16
drivers/gpu/drm/radeon/radeon_asic.c | 2 ++
drivers/gpu/drm/radeon/radeon_asic.h | 1 +
3 files changed, 19 insertions(+)
diff --git a/drivers/gpu/drm/radeon/r600_dpm.c
b/drivers/gpu/drm/radeon/r600_dpm.c
index 5513d8f..12e35dd 100644
--- a/drivers/gpu/drm/radeon/r600_dpm.c
+++ b/drivers/gpu/drm/radeon/r600_dpm.c
@@ -777,6 +777,22 @@ bool r600_is_internal_thermal_sensor(enum
radeon_int_thermal_type sensor)
}
}
+int r600_dpm_late_enable(struct radeon_device *rdev)
+{
+ int ret;
+
+ if (rdev->irq.installed &&
+ r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
+ ret = r600_set_thermal_temperature_range(rdev,
R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
+ if (ret)
+ return ret;
+ rdev->irq.dpm_thermal = true;
+ radeon_irq_set(rdev);
+ }
+
+ return 0;
+}
+
union power_info {
struct _ATOM_POWERPLAY_INFO info;
struct _ATOM_POWERPLAY_INFO_V2 info_2;
diff --git a/drivers/gpu/drm/radeon/radeon_asic.c
b/drivers/gpu/drm/radeon/radeon_asic.c
index c0425bb..a38ce4c 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.c
+++ b/drivers/gpu/drm/radeon/radeon_asic.c
@@ -1045,6 +1045,7 @@ static struct radeon_asic rv6xx_asic = {
.init = _dpm_init,
.setup_asic = _setup_asic,
.enable = _dpm_enable,
+ .late_enable = _dpm_late_enable,
.disable = _dpm_disable,
.pre_set_power_state = _dpm_pre_set_power_state,
.set_power_state = _dpm_set_power_state,
@@ -1135,6 +1136,7 @@ static struct radeon_asic rs780_asic = {
.init = _dpm_init,
.setup_asic = _dpm_setup_asic,
.enable = _dpm_enable,
+ .late_enable = _dpm_late_enable,
.disable = _dpm_disable,
.pre_set_power_state = _dpm_pre_set_power_state,
.set_power_state = _dpm_set_power_state,
diff --git a/drivers/gpu/drm/radeon/radeon_asic.h
b/drivers/gpu/drm/radeon/radeon_asic.h
index c9fd97b..438839f 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.h
+++ b/drivers/gpu/drm/radeon/radeon_asic.h
@@ -392,6 +392,7 @@ int rv6xx_get_temp(struct radeon_device *rdev);
int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
int r600_dpm_pre_set_power_state(struct radeon_device *rdev);
void r600_dpm_post_set_power_state(struct radeon_device *rdev);
+int r600_dpm_late_enable(struct radeon_device *rdev);
/* r600 dma */
uint32_t r600_dma_get_rptr(struct radeon_device *rdev,
struct radeon_ring *ring);
--
1.8.3.1
[PATCH 05/18] drm/radeon/dpm: add a late enable callback
Certain features need to be enabled after ring tests
(e.g., powergating, etc.). Add a function pointer
to split out late enable features.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/radeon.h| 3 +++
drivers/gpu/drm/radeon/radeon_pm.c | 12
2 files changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index b1f990d..1900917 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -252,6 +252,7 @@ struct radeon_clock {
* Power management
*/
int radeon_pm_init(struct radeon_device *rdev);
+int radeon_pm_late_init(struct radeon_device *rdev);
void radeon_pm_fini(struct radeon_device *rdev);
void radeon_pm_compute_clocks(struct radeon_device *rdev);
void radeon_pm_suspend(struct radeon_device *rdev);
@@ -1775,6 +1776,7 @@ struct radeon_asic {
int (*init)(struct radeon_device *rdev);
void (*setup_asic)(struct radeon_device *rdev);
int (*enable)(struct radeon_device *rdev);
+ int (*late_enable)(struct radeon_device *rdev);
void (*disable)(struct radeon_device *rdev);
int (*pre_set_power_state)(struct radeon_device *rdev);
int (*set_power_state)(struct radeon_device *rdev);
@@ -2650,6 +2652,7 @@ void radeon_ring_write(struct radeon_ring *ring, uint32_t
v);
#define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
#define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
#define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
+#define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev))
#define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
#define radeon_dpm_pre_set_power_state(rdev)
rdev->asic->dpm.pre_set_power_state((rdev))
#define radeon_dpm_set_power_state(rdev)
rdev->asic->dpm.set_power_state((rdev))
diff --git a/drivers/gpu/drm/radeon/radeon_pm.c
b/drivers/gpu/drm/radeon/radeon_pm.c
index 384758d..d4e5bcf 100644
--- a/drivers/gpu/drm/radeon/radeon_pm.c
+++ b/drivers/gpu/drm/radeon/radeon_pm.c
@@ -1288,6 +1288,18 @@ int radeon_pm_init(struct radeon_device *rdev)
return radeon_pm_init_old(rdev);
}
+int radeon_pm_late_init(struct radeon_device *rdev)
+{
+ int ret = 0;
+
+ if (rdev->pm.pm_method == PM_METHOD_DPM) {
+ mutex_lock(>pm.mutex);
+ ret = radeon_dpm_late_enable(rdev);
+ mutex_unlock(>pm.mutex);
+ }
+ return ret;
+}
+
static void radeon_pm_fini_old(struct radeon_device *rdev)
{
if (rdev->pm.num_power_states > 1) {
--
1.8.3.1
[PATCH 04/18] drm/radeon: re-order firmware loading in preparation for dpm rework
We need to reorder the driver init sequence to better accomodate
dpm which needs to be loaded earlier in the init sequence. Move
fw init up so that it's available for dpm init.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/cik.c | 42 --
drivers/gpu/drm/radeon/evergreen.c | 33 --
drivers/gpu/drm/radeon/ni.c| 36 +---
drivers/gpu/drm/radeon/r600.c | 16 +++
drivers/gpu/drm/radeon/rv770.c | 16 +++
drivers/gpu/drm/radeon/si.c| 18
6 files changed, 84 insertions(+), 77 deletions(-)
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index b43a3a3..4ddc3e5 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -7501,26 +7501,7 @@ static int cik_startup(struct radeon_device *rdev)
cik_mc_program(rdev);
- if (rdev->flags & RADEON_IS_IGP) {
- if (!rdev->me_fw || !rdev->pfp_fw || !rdev->ce_fw ||
- !rdev->mec_fw || !rdev->sdma_fw || !rdev->rlc_fw) {
- r = cik_init_microcode(rdev);
- if (r) {
- DRM_ERROR("Failed to load firmware!\n");
- return r;
- }
- }
- } else {
- if (!rdev->me_fw || !rdev->pfp_fw || !rdev->ce_fw ||
- !rdev->mec_fw || !rdev->sdma_fw || !rdev->rlc_fw ||
- !rdev->mc_fw) {
- r = cik_init_microcode(rdev);
- if (r) {
- DRM_ERROR("Failed to load firmware!\n");
- return r;
- }
- }
-
+ if (!(rdev->flags & RADEON_IS_IGP)) {
r = ci_mc_load_microcode(rdev);
if (r) {
DRM_ERROR("Failed to load MC firmware!\n");
@@ -7833,6 +7814,27 @@ int cik_init(struct radeon_device *rdev)
if (r)
return r;
+ if (rdev->flags & RADEON_IS_IGP) {
+ if (!rdev->me_fw || !rdev->pfp_fw || !rdev->ce_fw ||
+ !rdev->mec_fw || !rdev->sdma_fw || !rdev->rlc_fw) {
+ r = cik_init_microcode(rdev);
+ if (r) {
+ DRM_ERROR("Failed to load firmware!\n");
+ return r;
+ }
+ }
+ } else {
+ if (!rdev->me_fw || !rdev->pfp_fw || !rdev->ce_fw ||
+ !rdev->mec_fw || !rdev->sdma_fw || !rdev->rlc_fw ||
+ !rdev->mc_fw) {
+ r = cik_init_microcode(rdev);
+ if (r) {
+ DRM_ERROR("Failed to load firmware!\n");
+ return r;
+ }
+ }
+ }
+
ring = >ring[RADEON_RING_TYPE_GFX_INDEX];
ring->ring_obj = NULL;
r600_ring_init(rdev, ring, 1024 * 1024);
diff --git a/drivers/gpu/drm/radeon/evergreen.c
b/drivers/gpu/drm/radeon/evergreen.c
index 9702e55..4abf8b6 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -5110,26 +5110,11 @@ static int evergreen_startup(struct radeon_device *rdev)
evergreen_mc_program(rdev);
if (ASIC_IS_DCE5(rdev)) {
- if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw ||
!rdev->mc_fw) {
- r = ni_init_microcode(rdev);
- if (r) {
- DRM_ERROR("Failed to load firmware!\n");
- return r;
- }
- }
r = ni_mc_load_microcode(rdev);
if (r) {
DRM_ERROR("Failed to load MC firmware!\n");
return r;
}
- } else {
- if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
- r = r600_init_microcode(rdev);
- if (r) {
- DRM_ERROR("Failed to load firmware!\n");
- return r;
- }
- }
}
if (rdev->flags & RADEON_IS_AGP) {
@@ -5357,6 +5342,24 @@ int evergreen_init(struct radeon_device *rdev)
if (r)
return r;
+ if (ASIC_IS_DCE5(rdev)) {
+ if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw ||
!rdev->mc_fw) {
+ r = ni_init_microcode(rdev);
+ if (r) {
+ DRM_ERROR("Failed to load firmware!\n");
+ return r;
+ }
+ }
+ } else {
+ if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
+ r =
[PATCH 03/18] drm/radeon/cik: drop cg_update from dpm code
I'm not entirely sure this is required and it won't work
with the dpm restructing anyway.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/ci_dpm.c | 36
drivers/gpu/drm/radeon/kv_dpm.c | 25 -
2 files changed, 61 deletions(-)
diff --git a/drivers/gpu/drm/radeon/ci_dpm.c b/drivers/gpu/drm/radeon/ci_dpm.c
index 1ed4799..f891fc0 100644
--- a/drivers/gpu/drm/radeon/ci_dpm.c
+++ b/drivers/gpu/drm/radeon/ci_dpm.c
@@ -171,8 +171,6 @@ extern void si_trim_voltage_table_to_fit_state_table(struct
radeon_device *rdev,
struct atom_voltage_table
*voltage_table);
extern void cik_enter_rlc_safe_mode(struct radeon_device *rdev);
extern void cik_exit_rlc_safe_mode(struct radeon_device *rdev);
-extern void cik_update_cg(struct radeon_device *rdev,
- u32 block, bool enable);
static int ci_get_std_voltage_value_sidd(struct radeon_device *rdev,
struct atom_voltage_table_entry
*voltage_table,
@@ -4561,13 +4559,6 @@ int ci_dpm_enable(struct radeon_device *rdev)
struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
int ret;
- cik_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
-RADEON_CG_BLOCK_MC |
-RADEON_CG_BLOCK_SDMA |
-RADEON_CG_BLOCK_BIF |
-RADEON_CG_BLOCK_UVD |
-RADEON_CG_BLOCK_HDP), false);
-
if (ci_is_smc_running(rdev))
return -EINVAL;
if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
@@ -4689,13 +4680,6 @@ int ci_dpm_enable(struct radeon_device *rdev)
ci_dpm_powergate_uvd(rdev, true);
- cik_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
-RADEON_CG_BLOCK_MC |
-RADEON_CG_BLOCK_SDMA |
-RADEON_CG_BLOCK_BIF |
-RADEON_CG_BLOCK_UVD |
-RADEON_CG_BLOCK_HDP), true);
-
ci_update_current_ps(rdev, boot_ps);
return 0;
@@ -4706,12 +4690,6 @@ void ci_dpm_disable(struct radeon_device *rdev)
struct ci_power_info *pi = ci_get_pi(rdev);
struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
- cik_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
-RADEON_CG_BLOCK_MC |
-RADEON_CG_BLOCK_SDMA |
-RADEON_CG_BLOCK_UVD |
-RADEON_CG_BLOCK_HDP), false);
-
ci_dpm_powergate_uvd(rdev, false);
if (!ci_is_smc_running(rdev))
@@ -4742,13 +4720,6 @@ int ci_dpm_set_power_state(struct radeon_device *rdev)
struct radeon_ps *old_ps = >current_rps;
int ret;
- cik_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
-RADEON_CG_BLOCK_MC |
-RADEON_CG_BLOCK_SDMA |
-RADEON_CG_BLOCK_BIF |
-RADEON_CG_BLOCK_UVD |
-RADEON_CG_BLOCK_HDP), false);
-
ci_find_dpm_states_clocks_in_dpm_table(rdev, new_ps);
if (pi->pcie_performance_request)
ci_request_link_speed_change_before_state_change(rdev, new_ps,
old_ps);
@@ -4804,13 +4775,6 @@ int ci_dpm_set_power_state(struct radeon_device *rdev)
if (pi->pcie_performance_request)
ci_notify_link_speed_change_after_state_change(rdev, new_ps,
old_ps);
- cik_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
-RADEON_CG_BLOCK_MC |
-RADEON_CG_BLOCK_SDMA |
-RADEON_CG_BLOCK_BIF |
-RADEON_CG_BLOCK_UVD |
-RADEON_CG_BLOCK_HDP), true);
-
return 0;
}
diff --git a/drivers/gpu/drm/radeon/kv_dpm.c b/drivers/gpu/drm/radeon/kv_dpm.c
index b419055..a0e20eb 100644
--- a/drivers/gpu/drm/radeon/kv_dpm.c
+++ b/drivers/gpu/drm/radeon/kv_dpm.c
@@ -1126,11 +1126,6 @@ int kv_dpm_enable(struct radeon_device *rdev)
struct kv_power_info *pi = kv_get_pi(rdev);
int ret;
- cik_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
-RADEON_CG_BLOCK_SDMA |
-RADEON_CG_BLOCK_BIF |
-RADEON_CG_BLOCK_HDP), false);
-
ret = kv_process_firmware_header(rdev);
if (ret) {
DRM_ERROR("kv_process_firmware_header failed\n");
@@ -1238,11 +1233,6 @@ int kv_dpm_enable(struct radeon_device *rdev)
kv_dpm_powergate_vce(rdev, true);
kv_dpm_powergate_uvd(rdev, true);
- cik_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
-RADEON_CG_BLOCK_SDMA |
-RADEON_CG_BLOCK_BIF |
-RADEON_CG_BLOCK_HDP), true);
-
kv_update_current_ps(rdev, rdev->pm.dpm.boot_ps);
[PATCH 02/18] drm/radeon/si: drop cg_update from dpm code
I'm not entirely sure this is required and it won't work
with the dpm restructing anyway.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/si.c | 4 ++--
drivers/gpu/drm/radeon/si_dpm.c | 38 --
2 files changed, 2 insertions(+), 40 deletions(-)
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index a36736d..e3a9fc7 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -5210,8 +5210,8 @@ static void si_enable_hdp_ls(struct radeon_device *rdev,
WREG32(HDP_MEM_POWER_LS, data);
}
-void si_update_cg(struct radeon_device *rdev,
- u32 block, bool enable)
+static void si_update_cg(struct radeon_device *rdev,
+u32 block, bool enable)
{
if (block & RADEON_CG_BLOCK_GFX) {
si_enable_gui_idle_interrupt(rdev, false);
diff --git a/drivers/gpu/drm/radeon/si_dpm.c b/drivers/gpu/drm/radeon/si_dpm.c
index 0b00c79..2d0e94a 100644
--- a/drivers/gpu/drm/radeon/si_dpm.c
+++ b/drivers/gpu/drm/radeon/si_dpm.c
@@ -1753,9 +1753,6 @@ static int si_calculate_sclk_params(struct radeon_device
*rdev,
u32 engine_clock,
SISLANDS_SMC_SCLK_VALUE *sclk);
-extern void si_update_cg(struct radeon_device *rdev,
-u32 block, bool enable);
-
static struct si_power_info *si_get_pi(struct radeon_device *rdev)
{
struct si_power_info *pi = rdev->pm.dpm.priv;
@@ -5791,13 +5788,6 @@ int si_dpm_enable(struct radeon_device *rdev)
struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
int ret;
- si_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
- RADEON_CG_BLOCK_MC |
- RADEON_CG_BLOCK_SDMA |
- RADEON_CG_BLOCK_BIF |
- RADEON_CG_BLOCK_UVD |
- RADEON_CG_BLOCK_HDP), false);
-
if (si_is_smc_running(rdev))
return -EINVAL;
if (pi->voltage_control)
@@ -5917,13 +5907,6 @@ int si_dpm_enable(struct radeon_device *rdev)
si_enable_auto_throttle_source(rdev,
RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
- si_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
- RADEON_CG_BLOCK_MC |
- RADEON_CG_BLOCK_SDMA |
- RADEON_CG_BLOCK_BIF |
- RADEON_CG_BLOCK_UVD |
- RADEON_CG_BLOCK_HDP), true);
-
ni_update_current_ps(rdev, boot_ps);
return 0;
@@ -5934,13 +5917,6 @@ void si_dpm_disable(struct radeon_device *rdev)
struct rv7xx_power_info *pi = rv770_get_pi(rdev);
struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
- si_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
- RADEON_CG_BLOCK_MC |
- RADEON_CG_BLOCK_SDMA |
- RADEON_CG_BLOCK_BIF |
- RADEON_CG_BLOCK_UVD |
- RADEON_CG_BLOCK_HDP), false);
-
if (!si_is_smc_running(rdev))
return;
si_disable_ulv(rdev);
@@ -6005,13 +5981,6 @@ int si_dpm_set_power_state(struct radeon_device *rdev)
struct radeon_ps *old_ps = _pi->current_rps;
int ret;
- si_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
- RADEON_CG_BLOCK_MC |
- RADEON_CG_BLOCK_SDMA |
- RADEON_CG_BLOCK_BIF |
- RADEON_CG_BLOCK_UVD |
- RADEON_CG_BLOCK_HDP), false);
-
ret = si_disable_ulv(rdev);
if (ret) {
DRM_ERROR("si_disable_ulv failed\n");
@@ -6104,13 +6073,6 @@ int si_dpm_set_power_state(struct radeon_device *rdev)
return ret;
}
- si_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
- RADEON_CG_BLOCK_MC |
- RADEON_CG_BLOCK_SDMA |
- RADEON_CG_BLOCK_BIF |
- RADEON_CG_BLOCK_UVD |
- RADEON_CG_BLOCK_HDP), true);
-
return 0;
}
--
1.8.3.1
[PATCH 01/18] drm/radeon/dpm: remove unnecessary checks in dpm_init
No need to check rdev->pm.num_power_states; this is a vestige
of the old pm code.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/radeon_pm.c | 36 +---
1 file changed, 17 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon_pm.c
b/drivers/gpu/drm/radeon/radeon_pm.c
index 984097b..384758d 100644
--- a/drivers/gpu/drm/radeon/radeon_pm.c
+++ b/drivers/gpu/drm/radeon/radeon_pm.c
@@ -1192,28 +1192,26 @@ static int radeon_pm_init_dpm(struct radeon_device
*rdev)
rdev->pm.dpm_enabled = true;
radeon_pm_compute_clocks(rdev);
- if (rdev->pm.num_power_states > 1) {
- ret = device_create_file(rdev->dev, _attr_power_dpm_state);
- if (ret)
- DRM_ERROR("failed to create device file for dpm
state\n");
- ret = device_create_file(rdev->dev,
_attr_power_dpm_force_performance_level);
- if (ret)
- DRM_ERROR("failed to create device file for dpm
state\n");
- /* XXX: these are noops for dpm but are here for backwards
compat */
- ret = device_create_file(rdev->dev, _attr_power_profile);
- if (ret)
- DRM_ERROR("failed to create device file for power
profile\n");
- ret = device_create_file(rdev->dev, _attr_power_method);
- if (ret)
- DRM_ERROR("failed to create device file for power
method\n");
-
- if (radeon_debugfs_pm_init(rdev)) {
- DRM_ERROR("Failed to register debugfs file for dpm!\n");
- }
+ ret = device_create_file(rdev->dev, _attr_power_dpm_state);
+ if (ret)
+ DRM_ERROR("failed to create device file for dpm state\n");
+ ret = device_create_file(rdev->dev,
_attr_power_dpm_force_performance_level);
+ if (ret)
+ DRM_ERROR("failed to create device file for dpm state\n");
+ /* XXX: these are noops for dpm but are here for backwards compat */
+ ret = device_create_file(rdev->dev, _attr_power_profile);
+ if (ret)
+ DRM_ERROR("failed to create device file for power profile\n");
+ ret = device_create_file(rdev->dev, _attr_power_method);
+ if (ret)
+ DRM_ERROR("failed to create device file for power method\n");
- DRM_INFO("radeon: dpm initialized\n");
+ if (radeon_debugfs_pm_init(rdev)) {
+ DRM_ERROR("Failed to register debugfs file for dpm!\n");
}
+ DRM_INFO("radeon: dpm initialized\n");
+
return 0;
}
--
1.8.3.1
[PATCH 00/18] Rework PM init order
Newer asics require that the dpm be initialized prior to the other engines in order for clockgating to work properly. The tricky part is that other aspects of dpm are required at later stages (e.g., after displays are enumerated). This patch set reworks the power management init flow to accomodate the requirements of newer hardware. Most of the pm init/fini/suspend/resume flow has now moved into the asic specific functions. As a result, dpm now initializes reliably on CIK parts and clockgating on these parts now works and is enabled by default. Powergating support for CIK parts is also improved, but is not yet ready to be enabled by default. I think it's now safe to enable dpm by default on CIK parts. Alex Deucher (18): drm/radeon/dpm: remove unnecessary checks in dpm_init drm/radeon/si: drop cg_update from dpm code drm/radeon/cik: drop cg_update from dpm code drm/radeon: re-order firmware loading in preparation for dpm rework drm/radeon/dpm: add a late enable callback drm/radeon/dpm: add late_enable for rs780/rs880/rv6xx drm/radeon/dpm: add late_enable for rv7xx-NI drm/radeon/dpm: add late_enable for sumo drm/radeon/dpm: add late_enable for trinity drm/radeon/dpm: add late_enable for SI drm/radeon/dpm: add late_enable for CI drm/radeon/dpm: add late_enable for KB/KV drm/radeon/dpm: switch on new late_enable callback drm/radeon/pm: move pm handling into the asic specific code drm/radeon: enable gfx cgcg on CIK dGPUs drm/radeon: enable gfx cgcg on CIK APUs drm/radeon: enable dpm by default on CI dGPUs drm/radeon: enable dpm by default on CI APUs drivers/gpu/drm/radeon/btc_dpm.c| 20 ++--- drivers/gpu/drm/radeon/ci_dpm.c | 58 - drivers/gpu/drm/radeon/cik.c| 51 +++- drivers/gpu/drm/radeon/cypress_dpm.c| 15 drivers/gpu/drm/radeon/evergreen.c | 42 ++ drivers/gpu/drm/radeon/kv_dpm.c | 48 --- drivers/gpu/drm/radeon/ni.c | 43 ++ drivers/gpu/drm/radeon/ni_dpm.c | 21 ++--- drivers/gpu/drm/radeon/r100.c | 7 ++ drivers/gpu/drm/radeon/r300.c | 7 ++ drivers/gpu/drm/radeon/r420.c | 7 ++ drivers/gpu/drm/radeon/r520.c | 5 ++ drivers/gpu/drm/radeon/r600.c | 23 -- drivers/gpu/drm/radeon/r600_dpm.c | 20 - drivers/gpu/drm/radeon/r600_dpm.h | 2 - drivers/gpu/drm/radeon/radeon.h | 3 + drivers/gpu/drm/radeon/radeon_asic.c| 19 - drivers/gpu/drm/radeon/radeon_asic.h| 7 ++ drivers/gpu/drm/radeon/radeon_device.c | 14 +++- drivers/gpu/drm/radeon/radeon_display.c | 17 +++- drivers/gpu/drm/radeon/radeon_pm.c | 140 ++-- drivers/gpu/drm/radeon/rs400.c | 7 ++ drivers/gpu/drm/radeon/rs600.c | 7 ++ drivers/gpu/drm/radeon/rs690.c | 7 ++ drivers/gpu/drm/radeon/rs780_dpm.c | 8 -- drivers/gpu/drm/radeon/rv515.c | 7 ++ drivers/gpu/drm/radeon/rv6xx_dpm.c | 10 --- drivers/gpu/drm/radeon/rv770.c | 23 -- drivers/gpu/drm/radeon/rv770_dpm.c | 15 +++- drivers/gpu/drm/radeon/rv770_dpm.h | 4 - drivers/gpu/drm/radeon/si.c | 35 +--- drivers/gpu/drm/radeon/si_dpm.c | 60 -- drivers/gpu/drm/radeon/sumo_dpm.c | 19 +++-- drivers/gpu/drm/radeon/trinity_dpm.c| 17 +++- 34 files changed, 432 insertions(+), 356 deletions(-) -- 1.8.3.1
[pull] radeon fixes 3.13
Hi Dave, One more fix for a long standing corruption bug on some Trinity/Richland parts. The following changes since commit b67ce39a30976171e7b96b30a94a0216ab89df97: drm/radeon: check for 0 count in speaker allocation and SAD code (2013-12-17 09:23:16 -0500) are available in the git repository at: git://people.freedesktop.org/~agd5f/linux drm-fixes-3.13 for you to fetch changes up to e2f6c88fb903e123edfd1106b0b8310d5117f774: drm/radeon: fix asic gfx values for scrapper asics (2013-12-19 19:41:46 -0500) Alex Deucher (1): drm/radeon: fix asic gfx values for scrapper asics drivers/gpu/drm/radeon/ni.c | 20 1 file changed, 16 insertions(+), 4 deletions(-)
[PATCH] drm/radeon: fix asic gfx values for scrapper asics
Fixes gfx corruption on certain TN/RL parts.
bug:
https://bugs.freedesktop.org/show_bug.cgi?id=60389
Signed-off-by: Alex Deucher
Cc: stable at vger.kernel.org
---
drivers/gpu/drm/radeon/ni.c | 20
1 file changed, 16 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index 11aab2a..f59a9e9 100644
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -895,6 +895,10 @@ static void cayman_gpu_init(struct radeon_device *rdev)
(rdev->pdev->device == 0x999C)) {
rdev->config.cayman.max_simds_per_se = 6;
rdev->config.cayman.max_backends_per_se = 2;
+ rdev->config.cayman.max_hw_contexts = 8;
+ rdev->config.cayman.sx_max_export_size = 256;
+ rdev->config.cayman.sx_max_export_pos_size = 64;
+ rdev->config.cayman.sx_max_export_smx_size = 192;
} else if ((rdev->pdev->device == 0x9903) ||
(rdev->pdev->device == 0x9904) ||
(rdev->pdev->device == 0x990A) ||
@@ -905,6 +909,10 @@ static void cayman_gpu_init(struct radeon_device *rdev)
(rdev->pdev->device == 0x999D)) {
rdev->config.cayman.max_simds_per_se = 4;
rdev->config.cayman.max_backends_per_se = 2;
+ rdev->config.cayman.max_hw_contexts = 8;
+ rdev->config.cayman.sx_max_export_size = 256;
+ rdev->config.cayman.sx_max_export_pos_size = 64;
+ rdev->config.cayman.sx_max_export_smx_size = 192;
} else if ((rdev->pdev->device == 0x9919) ||
(rdev->pdev->device == 0x9990) ||
(rdev->pdev->device == 0x9991) ||
@@ -915,9 +923,17 @@ static void cayman_gpu_init(struct radeon_device *rdev)
(rdev->pdev->device == 0x99A0)) {
rdev->config.cayman.max_simds_per_se = 3;
rdev->config.cayman.max_backends_per_se = 1;
+ rdev->config.cayman.max_hw_contexts = 4;
+ rdev->config.cayman.sx_max_export_size = 128;
+ rdev->config.cayman.sx_max_export_pos_size = 32;
+ rdev->config.cayman.sx_max_export_smx_size = 96;
} else {
rdev->config.cayman.max_simds_per_se = 2;
rdev->config.cayman.max_backends_per_se = 1;
+ rdev->config.cayman.max_hw_contexts = 4;
+ rdev->config.cayman.sx_max_export_size = 128;
+ rdev->config.cayman.sx_max_export_pos_size = 32;
+ rdev->config.cayman.sx_max_export_smx_size = 96;
}
rdev->config.cayman.max_texture_channel_caches = 2;
rdev->config.cayman.max_gprs = 256;
@@ -925,10 +941,6 @@ static void cayman_gpu_init(struct radeon_device *rdev)
rdev->config.cayman.max_gs_threads = 32;
rdev->config.cayman.max_stack_entries = 512;
rdev->config.cayman.sx_num_of_sets = 8;
- rdev->config.cayman.sx_max_export_size = 256;
- rdev->config.cayman.sx_max_export_pos_size = 64;
- rdev->config.cayman.sx_max_export_smx_size = 192;
- rdev->config.cayman.max_hw_contexts = 8;
rdev->config.cayman.sq_num_cf_insts = 2;
rdev->config.cayman.sc_prim_fifo_size = 0x40;
--
1.8.3.1
[Bug 66981] radeon 7970M, skyrim with mesa git: "GPU fault detected: 146"
https://bugzilla.kernel.org/show_bug.cgi?id=66981 Christoph Haag changed: What|Removed |Added Status|NEW |RESOLVED Resolution|--- |CODE_FIX --- Comment #5 from Christoph Haag --- Ok, I'll close this since I have seen nothing like that anymore so I assume it is fixed by mesa. -- You are receiving this mail because: You are watching the assignee of the bug.
[PATCH 4/4] drm: exynos: hdmi: Add dt support for hdmiphy settings
This patch adds dt support to hdmiphy config settings
as it is board specific and depends on the signal pattern
of board.
Signed-off-by: Shirish S
---
.../devicetree/bindings/video/exynos_hdmi.txt | 34
drivers/gpu/drm/exynos/exynos_hdmi.c | 89
2 files changed, 105 insertions(+), 18 deletions(-)
diff --git a/Documentation/devicetree/bindings/video/exynos_hdmi.txt
b/Documentation/devicetree/bindings/video/exynos_hdmi.txt
index 323983b..0766e6e 100644
--- a/Documentation/devicetree/bindings/video/exynos_hdmi.txt
+++ b/Documentation/devicetree/bindings/video/exynos_hdmi.txt
@@ -13,6 +13,31 @@ Required properties:
b) pin number within the gpio controller.
c) optional flags and pull up/down.
+Optional-but-recommended properties:
+- hdmiphy-configs: following information about the hdmiphy config settings.
+ a) "config: config" specifies the phy configuration settings,
+ where 'N' denotes the number of configuration, since every
+ pixel clock can have its unique configuration.
+ "samsung,pixel-clock" specifies the pixel clock
+ "samsung,de-emphasis-level" provides fine control of TMDS data
+pre emphasis, below shown is example for
+ data de-emphasis register at address 0x145D0040.
+ hdmiphy at 38[16] for bits[3:0] permitted values are in
+ the range of 760 mVdiff to 1400 mVdiff at 20mVdiff
+ increments for every LSB
+ hdmiphy at 38[16] for bits[7:4] permitted values are in
+ the range of 0dB to -7.45dB at increments of -0.45dB
+ for every LSB.
+ "samsung,clock-level" provides fine control of TMDS data
+ amplitude for each channel,
+ for example if 0x145D005C is the address of clock level
+ register then,
+ hdmiphy at 38[23] for bits [1:0] permitted values are in
+ the range of 0 mVdiff & 60 mVdiff for each channel at
+ increments 20 mVdiff of amplitude levels for every LSB,
+ hdmiphy at 38[23] for bits [7:3] permitted values are in
+ the range of 790 and 1430 mV at 20mV increments for
+ every LSB.
Example:
hdmi {
@@ -20,4 +45,13 @@ Example:
reg = <0x1453 0x10>;
interrupts = <0 95 0>;
hpd-gpio = < 7 1>;
+ hdmiphy-configs {
+ config0: config0 {
+ samsung,pixel-clock = <2520>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+
+ /* ... */
+ }
};
diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c
b/drivers/gpu/drm/exynos/exynos_hdmi.c
index a0e10ae..2fa0074 100644
--- a/drivers/gpu/drm/exynos/exynos_hdmi.c
+++ b/drivers/gpu/drm/exynos/exynos_hdmi.c
@@ -200,6 +200,9 @@ struct hdmi_context {
struct hdmi_resources res;
+ struct hdmiphy_config *confs;
+ int nr_confs;
+
int hpd_gpio;
enum hdmi_type type;
@@ -259,7 +262,7 @@ static const struct hdmiphy_config hdmiphy_v13_configs[] = {
},
};
-static const struct hdmiphy_config hdmiphy_v14_configs[] = {
+static struct hdmiphy_config hdmiphy_v14_configs[] = {
{
.pixel_clock = 2520,
.conf = {
@@ -771,20 +774,10 @@ static struct edid *hdmi_get_edid(void *ctx, struct
drm_connector *connector)
static int hdmi_find_phy_conf(struct hdmi_context *hdata, u32 pixel_clock)
{
- const struct hdmiphy_config *confs;
- int count, i;
-
- if (hdata->type == HDMI_TYPE13) {
- confs = hdmiphy_v13_configs;
- count = ARRAY_SIZE(hdmiphy_v13_configs);
- } else if (hdata->type == HDMI_TYPE14) {
- confs = hdmiphy_v14_configs;
- count = ARRAY_SIZE(hdmiphy_v14_configs);
- } else
- return -EINVAL;
+ int i;
- for (i = 0; i < count; i++)
- if (confs[i].pixel_clock == pixel_clock)
+ for (i = 0; i < hdata->nr_confs; i++)
+ if (hdata->confs[i].pixel_clock == pixel_clock)
return i;
DRM_DEBUG_KMS("Could not find phy config for %d\n", pixel_clock);
@@ -1363,10 +1356,7 @@ static void hdmiphy_conf_apply(struct hdmi_context
*hdata)
return;
}
- if (hdata->type == HDMI_TYPE13)
- hdmiphy_data = hdmiphy_v13_configs[i].conf;
- else
- hdmiphy_data = hdmiphy_v14_configs[i].conf;
+ hdmiphy_data =
[PATCH 3/4] ARM: exynos: dts: cros5250: Add hdmi phy settings
This patch moves the hdmi phy setting to arndale dts,
as its more of a per board configuration and also
shall be easier for supporting future chipsets.
Signed-off-by: Shirish S
---
arch/arm/boot/dts/cros5250-common.dtsi | 74
1 file changed, 74 insertions(+)
diff --git a/arch/arm/boot/dts/cros5250-common.dtsi
b/arch/arm/boot/dts/cros5250-common.dtsi
index dc259e8b..45c8583 100644
--- a/arch/arm/boot/dts/cros5250-common.dtsi
+++ b/arch/arm/boot/dts/cros5250-common.dtsi
@@ -301,6 +301,80 @@
hdmi {
hpd-gpio = < 7 0>;
+ hdmiphy-configs {
+ /*
+ * Eye diagram test passed for:
+ * Data de-emphasis: -0.7dB & Data Level: 880mV
+ * i.e., 0010 0110 = 0x26
+ * and Clock level of 515mV and diff 1030mV
+ * i.e., 0x66
+ */
+ config0: config0 {
+ samsung,pixel-clock = <2520>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config1: config1 {
+ samsung,pixel-clock = <2700>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config2: config2 {
+ samsung,pixel-clock = <27027000>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config3: config3 {
+ samsung,pixel-clock = <3600>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config4: config4 {
+ samsung,pixel-clock = <4000>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config5: config5 {
+ samsung,pixel-clock = <6500>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config6: config6 {
+ samsung,pixel-clock = <74176000>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config7: config7 {
+ samsung,pixel-clock = <7425>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config8: config8 {
+ samsung,pixel-clock = <8350>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config9: config9 {
+ samsung,pixel-clock = <10650>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config10: config10 {
+ samsung,pixel-clock = <10800>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config11: config11 {
+ samsung,pixel-clock = <14625>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config12: config12 {
+ samsung,pixel-clock = <14850>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ };
};
gpio-keys {
--
1.7.9.5
[PATCH 2/4] ARM: dts: arndale: Add hdmi phy settings
This patch moves the hdmi phy setting to arndale dts,
as its more of a per board configuration and also
shall be easier for supporting future chipsets.
Signed-off-by: Shirish S
---
arch/arm/boot/dts/exynos5250-arndale.dts | 74 ++
1 file changed, 74 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts
b/arch/arm/boot/dts/exynos5250-arndale.dts
index cee55fa..6bc562c 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -475,6 +475,80 @@
vdd_osc-supply = <_reg>;
vdd_pll-supply = <_reg>;
vdd-supply = <_reg>;
+ hdmiphy-configs {
+ /*
+ * Eye diagram test passed for:
+ * Data de-emphasis: -0.7dB & Data Level: 880mV
+ * i.e., 0010 0110 = 0x26
+ * and Clock level of 515mV and diff 1030mV
+ * i.e., 0x66
+ */
+ config0: config0 {
+ samsung,pixel-clock = <2520>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config1: config1 {
+ samsung,pixel-clock = <2700>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config2: config2 {
+ samsung,pixel-clock = <27027000>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config3: config3 {
+ samsung,pixel-clock = <3600>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config4: config4 {
+ samsung,pixel-clock = <4000>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config5: config5 {
+ samsung,pixel-clock = <6500>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config6: config6 {
+ samsung,pixel-clock = <74176000>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config7: config7 {
+ samsung,pixel-clock = <7425>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config8: config8 {
+ samsung,pixel-clock = <8350>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config9: config9 {
+ samsung,pixel-clock = <10650>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config10: config10 {
+ samsung,pixel-clock = <10800>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config11: config11 {
+ samsung,pixel-clock = <14625>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config12: config12 {
+ samsung,pixel-clock = <14850>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ };
};
regulators {
--
1.7.9.5
[PATCH 1/4] ARM: dts: smdk5250: Add hdmi phy settings
This patch moves the hdmi phy setting to smdk5250
dts,as its more of a per board configuration and
also shall be easier for supporting future chipsets.
Signed-off-by: Shirish S
---
arch/arm/boot/dts/exynos5250-smdk5250.dts | 74 +
1 file changed, 74 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts
b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 2538b32..10da02f 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -220,6 +220,80 @@
hdmi {
hpd-gpio = < 7 0>;
+ hdmiphy-configs {
+ /*
+ * Eye diagram test passed for:
+ * Data de-emphasis: -0.7dB & Data Level: 880mV
+ * i.e., 0010 0110 = 0x26
+ * and Clock level of 515mV and diff 1030mV
+ * i.e., 0x66
+ */
+ config0: config0 {
+ samsung,pixel-clock = <2520>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config1: config1 {
+ samsung,pixel-clock = <2700>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config2: config2 {
+ samsung,pixel-clock = <27027000>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config3: config3 {
+ samsung,pixel-clock = <3600>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config4: config4 {
+ samsung,pixel-clock = <4000>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config5: config5 {
+ samsung,pixel-clock = <6500>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config6: config6 {
+ samsung,pixel-clock = <74176000>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config7: config7 {
+ samsung,pixel-clock = <7425>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config8: config8 {
+ samsung,pixel-clock = <8350>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config9: config9 {
+ samsung,pixel-clock = <10650>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config10: config10 {
+ samsung,pixel-clock = <10800>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config11: config11 {
+ samsung,pixel-clock = <14625>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config12: config12 {
+ samsung,pixel-clock = <14850>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ };
};
codec at 1100 {
--
1.7.9.5
[PATCH 0/4] Add dt support for exynos hdmiphy settings
For various revisions of a chipset if the signal pattern is changed for every revision, then the phy setting need to be updated correspondingly by measuring the signal. For getting correct signals the clock level and data de-emphasis levels needs to be adjusted. Since only these 2 values matter,we can move the same to dt, wherein we can have different dt files for every revision. This is an initial patchset towards achieving the same for exynos 5250 and can be later extended to future chipsets. V2: replaced moving of entire phy config structure with only required and justifiable conf registers. V3: Incorporated Mark Rutland's comments. V4: Rebased and included cros5250-common.dtsi. V5: removed nr-configs feild and also the constraint of having the exact number of configs in the dt file as in the driver, the programmer can add only the pixel clock that needs to be updated. V6: V7: removed nr-configs form the dtsi files. V8: Fixed build error V9: rebased and incorporated Tomasz comments. Shirish S (4): ARM: dts: smdk5250: Add hdmi phy settings ARM: dts: arndale: Add hdmi phy settings ARM: exynos: dts: cros5250: Add hdmi phy settings drm: exynos: hdmi: Add dt support for hdmiphy settings .../devicetree/bindings/video/exynos_hdmi.txt | 34 arch/arm/boot/dts/cros5250-common.dtsi | 74 arch/arm/boot/dts/exynos5250-arndale.dts | 74 arch/arm/boot/dts/exynos5250-smdk5250.dts | 74 drivers/gpu/drm/exynos/exynos_hdmi.c | 89 5 files changed, 327 insertions(+), 18 deletions(-) -- 1.7.9.5
[PATCH 4/4] drm: exynos: hdmi: Add dt support for hdmiphy settings
+ linux-samsung-soc mailing list.
On Wed, Dec 4, 2013 at 10:05 AM, Shirish S wrote:
> Hi Tomasz,
> Thanks for the reivew, please see my replies inline.
>
> On Fri, Nov 29, 2013 at 10:56 PM, Tomasz Figa wrote:
>> Hi Shirish,
>>
>> Please see my comments inline.
>>
>> On Monday 25 of November 2013 14:24:39 Shirish S wrote:
>>> This patch adds dt support to hdmiphy config settings
>>> as it is board specific and depends on the signal pattern
>>> of board.
>>>
>>> Signed-off-by: Shirish S
>>> ---
>>> .../devicetree/bindings/video/exynos_hdmi.txt | 31
>>> drivers/gpu/drm/exynos/exynos_hdmi.c | 77
>>> +++-
>>> 2 files changed, 104 insertions(+), 4 deletions(-)
>>>
>>> diff --git a/Documentation/devicetree/bindings/video/exynos_hdmi.txt
>>> b/Documentation/devicetree/bindings/video/exynos_hdmi.txt
>>> index 323983b..6eeb333 100644
>>> --- a/Documentation/devicetree/bindings/video/exynos_hdmi.txt
>>> +++ b/Documentation/devicetree/bindings/video/exynos_hdmi.txt
>>> @@ -13,6 +13,30 @@ Required properties:
>>> b) pin number within the gpio controller.
>>> c) optional flags and pull up/down.
>>>
>>> +- hdmiphy-configs: following information about the hdmiphy config settings.
>>
>> Is this node required or optional? If it's required, then it breaks
>> compatibility with already existing DTBs, which is not desirable.
>>
> Yes its an Optional-but-recommended node, and i have mentioned the same
> in this document in next patch set(v9).
>>> + a) "config: config" specifies the phy configuration settings,
>>> + where 'N' denotes the number of configuration, since every
>>> + pixel clock can have its unique configuration.
>>
>> Node names should not have any semantic meaning for parsing code. I know
>> that there are already existing bindings which rely on presence of
>> particularly named nodes, but that's not right and new bindings should
>> not follow that.
>>
> I referred Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
> for the implementation, am not clear with what you want me to do here, however
> the requirement seems similar as pinctrl, can u kindly suggest any
> existing newer
> implementations to refer.
>> Also what do you need the label of each config node for?
>>
> Each label here is a different pixel clock and corresponding phy setting, and
> it may vary from one pixel clock to other hence i need one for each config
> node.
>> Generally from parsing perspective you shouldn't really care about node
>> names. All you seem to do in the driver is iterating over all specified
>> nodes and matching them with internal driver data using pixel clock
>> frequency.
>>
> True, that is what i intended to do.I think for the requirement
> at hand, this should be fine.
>>> + "pixel-clock" specifies the pixel clock
>>
>> Vendor-specific properties should have vendor prefix, so this one should
>> be called "samsung,pixel-clock".
>>
> Agreed, updated in the next patch set(v9).
>>> + "conifig-de-emphasis-level" provides fine control of TMDS data
>>
>> Typo: s/conifig/config
>>
>> Also it should be called "samsung,de-emphasis-level".
>>
> Agreed, updated in the next patch set(v9).
>>> + pre emphasis, below shown is example for
>>> + data de-emphasis register at address 0x145D0040.
>>> + hdmiphy at 38[16] for bits[3:0] permitted values are
>>> in
>>> + the range of 760 mVdiff to 1400 mVdiff at 20mVdiff
>>> + increments for every LSB
>>> + hdmiphy at 38[16] for bits[7:4] permitted values are
>>> in
>>> + the range of 0dB to -7.45dB at increments of -0.45dB
>>> + for every LSB.
>>> + "config-clock-level" provides fine control of TMDS data
>>
>> "samsung,clock-level"
>>
> Agreed, updated in the next patch set(v9).
>>> + amplitude for each channel,
>>> + for example if 0x145D005C is the address of clock level
>> [snip]
>>> diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c
>>> b/drivers/gpu/drm/exynos/exynos_hdmi.c
>>> index 32ce9a6..5f599e3 100644
>>> --- a/drivers/gpu/drm/exynos/exynos_hdmi.c
>>> +++ b/drivers/gpu/drm/exynos/exynos_hdmi.c
>> [snip]
>>> +static int drm_hdmi_dt_parse_phy_conf(struct platform_device *pdev,
>>> + struct hdmi_context *hdata)
>>> +{
>>> + struct device *dev = >dev;
>>> + struct device_node *dev_np = dev->of_node;
>>> + struct device_node *phy_conf, *cfg_np;
>>> + int i, pixel_clock = 0;
>>> +
>>> + /* Initialize with default config */
>>> + hdata->confs = hdmiphy_v14_configs;
>>> + hdata->nr_confs = ARRAY_SIZE(hdmiphy_v14_configs);
>>> +
>>> + phy_conf = of_find_node_by_name(dev_np, "hdmiphy-configs");
>>
>> of_find_node_by_name() does not do what you need here. Please refer to
>> its implementation to learn why.
>>
>>
[Bug 68451] Texture flicker in native Dota2 in mesa 9.2.0rc1
https://bugs.freedesktop.org/show_bug.cgi?id=68451 --- Comment #45 from Alexandre Demers --- (In reply to comment #44) > Got flickering increasing in time here too. Radeon HD 5750 (Juniper PRO, > evergreen). > (that on a up-to-date fedora 19 x86-64, yes I did install that for all the > gaming c++ kludge bloody hell) Do you mean the flickering increases in time even if you stay where you are in DOTA 2? If so, it may be a different bug. The patch fixed the flickering I was seeing (and I think it was the same for Peter) in some specific areas (always the same flickering intensity in a given area, it could be related to some elements in the are like the river or towers for example). Peter reopened this bug because the patch was not backported to mesa 9.2 but it had been fixed for him too when applied manually. -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL: <http://lists.freedesktop.org/archives/dri-devel/attachments/20131219/c0f237d8/attachment.html>
[Bug 68451] Texture flicker in native Dota2 in mesa 9.2.0rc1
https://bugs.freedesktop.org/show_bug.cgi?id=68451 --- Comment #44 from Sylvain BERTRAND --- Got flickering increasing in time here too. Radeon HD 5750 (Juniper PRO, evergreen). (that on a up-to-date fedora 19 x86-64, yes I did install that for all the gaming c++ kludge bloody hell) -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL: <http://lists.freedesktop.org/archives/dri-devel/attachments/20131219/1e0315e2/attachment.html>
[Bug 68451] Texture flicker in native Dota2 in mesa 9.2.0rc1
https://bugs.freedesktop.org/show_bug.cgi?id=68451 --- Comment #43 from Alexandre Demers --- (In reply to comment #42) > (In reply to comment #41) > > (In reply to comment #40) > > > I am also seeing the corruption on Mesa 10.0.1. > > > > What GPU are you using? > > Radeon 4850. Does it work with others? Was fixed on 6950 (I'll test it again later today to be sure things are still OK). Patches point to evergreen code and above. Marek could tell if it applies (or if a similar solution should be made) to R700 (HD4XXX). -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL: <http://lists.freedesktop.org/archives/dri-devel/attachments/20131219/843a4e53/attachment-0001.html>
[Bug 68451] Texture flicker in native Dota2 in mesa 9.2.0rc1
https://bugs.freedesktop.org/show_bug.cgi?id=68451 --- Comment #42 from Marko Srebre --- (In reply to comment #41) > (In reply to comment #40) > > I am also seeing the corruption on Mesa 10.0.1. > > What GPU are you using? Radeon 4850. Does it work with others? -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL: <http://lists.freedesktop.org/archives/dri-devel/attachments/20131219/322a8a14/attachment-0001.html>
[PATCH] drm/dp: Use AUX constants from specification
On Mon, Dec 16, 2013 at 5:01 PM, Thierry Reding
wrote:
> The current values seem to be defined in a format that's specific to the
> i915, gma500 and radeon drivers. To make this more generally useful, use
> the values as defined in the specification.
>
> While at it, prefix the constants with DP_ for improved namespacing.
>
> Signed-off-by: Thierry Reding
Sorry if I'm late to the party. Seems good to me.
Perhaps all that shifting is a little unintuitive but I don't wanna
nitpick this.
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/gma500/cdv_intel_dp.c | 37
> ++-
> drivers/gpu/drm/i915/intel_dp.c | 37
> ++-
> drivers/gpu/drm/radeon/atombios_dp.c | 36 ++
> include/drm/drm_dp_helper.h | 32 +++---
> 4 files changed, 73 insertions(+), 69 deletions(-)
>
> diff --git a/drivers/gpu/drm/gma500/cdv_intel_dp.c
> b/drivers/gpu/drm/gma500/cdv_intel_dp.c
> index f88a1815d87c..6a7c2481d4ab 100644
> --- a/drivers/gpu/drm/gma500/cdv_intel_dp.c
> +++ b/drivers/gpu/drm/gma500/cdv_intel_dp.c
> @@ -483,7 +483,7 @@ cdv_intel_dp_aux_native_write(struct gma_encoder *encoder,
>
> if (send_bytes > 16)
> return -1;
> - msg[0] = AUX_NATIVE_WRITE << 4;
> + msg[0] = DP_AUX_NATIVE_WRITE << 4;
> msg[1] = address >> 8;
> msg[2] = address & 0xff;
> msg[3] = send_bytes - 1;
> @@ -493,9 +493,10 @@ cdv_intel_dp_aux_native_write(struct gma_encoder
> *encoder,
> ret = cdv_intel_dp_aux_ch(encoder, msg, msg_bytes, , 1);
> if (ret < 0)
> return ret;
> - if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
> + ack >>= 4;
> + if ((ack & DP_AUX_NATIVE_REPLY_MASK) ==
> DP_AUX_NATIVE_REPLY_ACK)
> break;
> - else if ((ack & AUX_NATIVE_REPLY_MASK) ==
> AUX_NATIVE_REPLY_DEFER)
> + else if ((ack & DP_AUX_NATIVE_REPLY_MASK) ==
> DP_AUX_NATIVE_REPLY_DEFER)
> udelay(100);
> else
> return -EIO;
> @@ -523,7 +524,7 @@ cdv_intel_dp_aux_native_read(struct gma_encoder *encoder,
> uint8_t ack;
> int ret;
>
> - msg[0] = AUX_NATIVE_READ << 4;
> + msg[0] = DP_AUX_NATIVE_READ << 4;
> msg[1] = address >> 8;
> msg[2] = address & 0xff;
> msg[3] = recv_bytes - 1;
> @@ -538,12 +539,12 @@ cdv_intel_dp_aux_native_read(struct gma_encoder
> *encoder,
> return -EPROTO;
> if (ret < 0)
> return ret;
> - ack = reply[0];
> - if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
> + ack = reply[0] >> 4;
> + if ((ack & DP_AUX_NATIVE_REPLY_MASK) ==
> DP_AUX_NATIVE_REPLY_ACK) {
> memcpy(recv, reply + 1, ret - 1);
> return ret - 1;
> }
> - else if ((ack & AUX_NATIVE_REPLY_MASK) ==
> AUX_NATIVE_REPLY_DEFER)
> + else if ((ack & DP_AUX_NATIVE_REPLY_MASK) ==
> DP_AUX_NATIVE_REPLY_DEFER)
> udelay(100);
> else
> return -EIO;
> @@ -569,12 +570,12 @@ cdv_intel_dp_i2c_aux_ch(struct i2c_adapter *adapter,
> int mode,
>
> /* Set up the command byte */
> if (mode & MODE_I2C_READ)
> - msg[0] = AUX_I2C_READ << 4;
> + msg[0] = DP_AUX_I2C_READ << 4;
> else
> - msg[0] = AUX_I2C_WRITE << 4;
> + msg[0] = DP_AUX_I2C_WRITE << 4;
>
> if (!(mode & MODE_I2C_STOP))
> - msg[0] |= AUX_I2C_MOT << 4;
> + msg[0] |= DP_AUX_I2C_MOT << 4;
>
> msg[1] = address >> 8;
> msg[2] = address;
> @@ -606,16 +607,16 @@ cdv_intel_dp_i2c_aux_ch(struct i2c_adapter *adapter,
> int mode,
> return ret;
> }
>
> - switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
> - case AUX_NATIVE_REPLY_ACK:
> + switch ((reply[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK) {
> + case DP_AUX_NATIVE_REPLY_ACK:
> /* I2C-over-AUX Reply field is only valid
> * when paired with AUX ACK.
> */
> break;
> - case AUX_NATIVE_REPLY_NACK:
> + case DP_AUX_NATIVE_REPLY_NACK:
> DRM_DEBUG_KMS("aux_ch native nack\n");
> return -EREMOTEIO;
> - case AUX_NATIVE_REPLY_DEFER:
> + case DP_AUX_NATIVE_REPLY_DEFER:
> udelay(100);
> continue;
> default:
> @@ -624,16 +625,16 @@ cdv_intel_dp_i2c_aux_ch(struct i2c_adapter *adapter,
> int mode,
>
[Bug 68451] Texture flicker in native Dota2 in mesa 9.2.0rc1
https://bugs.freedesktop.org/show_bug.cgi?id=68451 --- Comment #41 from Alexandre Demers --- (In reply to comment #40) > I am also seeing the corruption on Mesa 10.0.1. What GPU are you using? -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL: <http://lists.freedesktop.org/archives/dri-devel/attachments/20131219/8b679a11/attachment.html>
[GIT PULL FOR v3.14] Renesas R-Car DU patches
Hi Dave, It's been two weeks and a half already, is there anything holding this back ? On Monday 02 December 2013 01:30:56 Laurent Pinchart wrote: > Hi Dave, > > The following changes since commit a3483353ca4e6dbeef2ed62ebed01af109b5b27a: > > drm: check for !kdev in drm_unplug_minor() (2013-11-15 20:49:02 +1000) > > are available in the git repository at: > > git://linuxtv.org/pinchartl/fbdev.git drm/next/du > > for you to fetch changes up to 29ee6469e6138115420236a71c6b89bf8af1788a: > > drm/rcar-du: Add support for the r8a7791 DU (2013-12-02 01:27:29 +0100) > > > Laurent Pinchart (5): > drm/rcar-du: Don't cast crtc to rcrtc twice in the same function > drm/rcar-du: Update plane pitch in .mode_set_base() operation > drm/rcar-du: Split features and quirks > drm/rcar-du: Add LVDS_LANES quirk > drm/rcar-du: Add support for the r8a7791 DU > > Wei Yongjun (1): > drm/rcar-du: fix return value check in rcar_du_lvdsenc_get_resources() > > drivers/gpu/drm/rcar-du/rcar_du_crtc.c| 3 +-- > drivers/gpu/drm/rcar-du/rcar_du_drv.c | 24 ++-- > drivers/gpu/drm/rcar-du/rcar_du_drv.h | 14 -- > drivers/gpu/drm/rcar-du/rcar_du_kms.c | 4 ++-- > drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c | 28 > drivers/gpu/drm/rcar-du/rcar_du_plane.c | 21 +++-- 6 > files changed, 60 insertions(+), 34 deletions(-) -- Regards, Laurent Pinchart
[PATCH] [Intel-gfx] drm/edid: Populate picture aspect ratio for CEA modes
Adding picture aspect ratio for CEA modes based on CEA-861D Table 3 or
CEA-861E Table 4. This is useful for filling up the detail in AVI
infoframe.
v2: Ville's review comments incorporated
Added picture aspect ratio as part of edid_cea_modes instead of DRM_MODE
Signed-off-by: Vandana Kannan
Reviewed-by: Ville Syrjala
---
drivers/gpu/drm/drm_edid.c | 128 ++--
include/drm/drm_crtc.h |2 +
2 files changed, 66 insertions(+), 64 deletions(-)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index fb7cf0e..20e3784 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -600,347 +600,347 @@ static const struct drm_display_mode edid_cea_modes[] =
{
{ DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
752, 800, 0, 480, 490, 492, 525, 0,
DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
- .vrefresh = 60, },
+ .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
/* 2 - 720x480 at 60Hz */
{ DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
798, 858, 0, 480, 489, 495, 525, 0,
DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
- .vrefresh = 60, },
+ .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
/* 3 - 720x480 at 60Hz */
{ DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
798, 858, 0, 480, 489, 495, 525, 0,
DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
- .vrefresh = 60, },
+ .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
/* 4 - 1280x720 at 60Hz */
{ DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
1430, 1650, 0, 720, 725, 730, 750, 0,
DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
- .vrefresh = 60, },
+ .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
/* 5 - 1920x1080i at 60Hz */
{ DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
DRM_MODE_FLAG_INTERLACE),
- .vrefresh = 60, },
+ .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
/* 6 - 1440x480i at 60Hz */
{ DRM_MODE("1440x480i", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1478,
1602, 1716, 0, 480, 488, 494, 525, 0,
DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
- .vrefresh = 60, },
+ .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
/* 7 - 1440x480i at 60Hz */
{ DRM_MODE("1440x480i", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1478,
1602, 1716, 0, 480, 488, 494, 525, 0,
DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
- .vrefresh = 60, },
+ .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
/* 8 - 1440x240 at 60Hz */
{ DRM_MODE("1440x240", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1478,
1602, 1716, 0, 240, 244, 247, 262, 0,
DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
DRM_MODE_FLAG_DBLCLK),
- .vrefresh = 60, },
+ .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
/* 9 - 1440x240 at 60Hz */
{ DRM_MODE("1440x240", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1478,
1602, 1716, 0, 240, 244, 247, 262, 0,
DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
DRM_MODE_FLAG_DBLCLK),
- .vrefresh = 60, },
+ .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
/* 10 - 2880x480i at 60Hz */
{ DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
3204, 3432, 0, 480, 488, 494, 525, 0,
DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
DRM_MODE_FLAG_INTERLACE),
- .vrefresh = 60, },
+ .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
/* 11 - 2880x480i at 60Hz */
{ DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
3204, 3432, 0, 480, 488, 494, 525, 0,
DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
DRM_MODE_FLAG_INTERLACE),
- .vrefresh = 60, },
+ .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
/* 12 - 2880x240 at 60Hz */
{ DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
3204, 3432, 0, 240, 244, 247, 262, 0,
[Bug 68451] Texture flicker in native Dota2 in mesa 9.2.0rc1
https://bugs.freedesktop.org/show_bug.cgi?id=68451 --- Comment #40 from Marko Srebre --- I am also seeing the corruption on Mesa 10.0.1. -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL: <http://lists.freedesktop.org/archives/dri-devel/attachments/20131219/33ba19fa/attachment.html>
[PATCH 4/4] drm: exynos: hdmi: Add dt support for hdmiphy settings
On Thursday 19 of December 2013 17:42:28 Shirish S wrote:
> This patch adds dt support to hdmiphy config settings
> as it is board specific and depends on the signal pattern
> of board.
>
> Signed-off-by: Shirish S
> ---
> .../devicetree/bindings/video/exynos_hdmi.txt | 34
> drivers/gpu/drm/exynos/exynos_hdmi.c | 89
>
> 2 files changed, 105 insertions(+), 18 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/video/exynos_hdmi.txt
> b/Documentation/devicetree/bindings/video/exynos_hdmi.txt
> index 323983b..0766e6e 100644
> --- a/Documentation/devicetree/bindings/video/exynos_hdmi.txt
> +++ b/Documentation/devicetree/bindings/video/exynos_hdmi.txt
> @@ -13,6 +13,31 @@ Required properties:
> b) pin number within the gpio controller.
> c) optional flags and pull up/down.
>
> +Optional-but-recommended properties:
> +- hdmiphy-configs: following information about the hdmiphy config settings.
> + a) "config: config" specifies the phy configuration settings,
Why do you need this "config: " part? (This is called "label" in DT
terminology by the way and can be used to reference the node from
properties of other nodes, by so called "phandle".)
> + where 'N' denotes the number of configuration, since every
> + pixel clock can have its unique configuration.
> + "samsung,pixel-clock" specifies the pixel clock
> + "samsung,de-emphasis-level" provides fine control of TMDS data
> + pre emphasis, below shown is example for
> + data de-emphasis register at address 0x145D0040.
> + hdmiphy at 38[16] for bits[3:0] permitted values are in
> + the range of 760 mVdiff to 1400 mVdiff at 20mVdiff
> + increments for every LSB
> + hdmiphy at 38[16] for bits[7:4] permitted values are in
> + the range of 0dB to -7.45dB at increments of -0.45dB
> + for every LSB.
> + "samsung,clock-level" provides fine control of TMDS data
> + amplitude for each channel,
> + for example if 0x145D005C is the address of clock level
> + register then,
> + hdmiphy at 38[23] for bits [1:0] permitted values are in
> + the range of 0 mVdiff & 60 mVdiff for each channel at
> + increments 20 mVdiff of amplitude levels for every LSB,
> + hdmiphy at 38[23] for bits [7:3] permitted values are in
> + the range of 790 and 1430 mV at 20mV increments for
> + every LSB.
> Example:
>
> hdmi {
> @@ -20,4 +45,13 @@ Example:
> reg = <0x1453 0x10>;
> interrupts = <0 95 0>;
> hpd-gpio = < 7 1>;
> + hdmiphy-configs {
> + config0: config0 {
> + samsung,pixel-clock = <2520>;
> + samsung,de-emphasis-level = /bits/ 8 <0x26>;
nit: Two spaces before "/bits/".
> + samsung,clock-level = /bits/ 8 < 0x66>;
nit: Two spaces before "/bits/" and incorrect space after "<".
Generally the list of configurations should look like below:
phy-configs {
#address-cells = <1>;
#size-cells = <0>;
config at 0 {
reg = <0>;
/* other properties... */
};
config at 1 {
reg = <1>;
/* other properties... */
};
/* ... */
};
This is how bus-like structures should be represented in device tree.
Also, since this is HDMI node, maybe it's enough to call the node simply
phy-configs. Please rework the patches to use this correct representation.
> +
> + /* ... */
> + }
> };
[snip]
> + for_each_child_of_node(phy_conf, cfg_np) {
> + if (of_property_read_u32(cfg_np, "samsung,pixel-clock",
> + _clock))
> + continue;
> +
> + for (i = 0; i < ARRAY_SIZE(hdata->nr_confs); i++) {
> + if (hdata->confs[i].pixel_clock == pixel_clock)
Can you have more than one config with the same pixel clock?
Even if not, the code could be made more readable if the code
below is moved outside the if and continue keyword is used instead.
Best regards,
Tomasz
Opps while using omapdrm_pvr.ko!
824 0005 0002 0668 [ 52.013092] b840 0006 0001 0002 0003 0004 0005 [ 52.021728] b860 [ 52.030364] Process hmi-player (pid: 1351, stack limit = 0xe7b0a2f8) [ 52.037078] Stack: (0xe7b0bd10 to 0xe7b0c000) [ 52.041656] bd00: 00df 7f033310 7f03a740 [ 52.050292] bd20: 00dc e7b0bd64 e7b0bd54 f00e900c f00e9004 e79de040 e79de180 [ 52.058929] bd40: e23d2658 00dc e7b0bd94 e7b0bd58 7f027c68 7f0275e8 f00e9008 [ 52.067565] bd60: 1000 e23d2658 0528 f00e9000 e79de040 000b f00e8000 f00e9000 [ 52.076202] bd80: 7f029588 8075106c e7b0bdb4 e7b0bd98 7f03c2e0 7f027b98 f00e900c f00e9010 [ 52.084808] bda0: e7b0be38 e7b0be38 e7b0bddc e7b0bdb8 7f03ddf0 7f03c2ac c01c6716 ee51b800 [ 52.093444] bdc0: e7b0be38 e7a7af00 c01c670b 0547 e7b0be0c e7b0bde0 7f029754 7f03dcf8 [ 52.102081] bde0: e79de040 8006b000 00400140 ee51b800 e7b0be38 401c6447 001c e7a7af00 [ 52.110717] be00: e7b0bee4 e7b0be10 802d6850 7f029594 0547 401c6447 0047 e200 [ 52.119323] be20: 0001 e7b0be30 8006b2a0 8007b5a8 7e805ea4 ee51b834 000b 001c [ 52.127960] be40: 7e805ee0 0008 7e805ee8 0014 0005 892158a0 80080db8 [ 52.136596] be60: e7b0be9c e7b0be70 80080db8 800153c0 e4591df9 000b e45fb9eb 000b [ 52.145202] be80: e45fb9eb 000b 89215800 892158d8 e7b0bebc e7b0bea0 80082384 80080cb4 [ 52.153839] bea0: 7fff 800b e7b0bf24 e7b0bec0 8006335c c01c670b [ 52.162475] bec0: e7a7ae40 401c6447 7e805ea4 ef1e7608 e7b0a000 7e805ea4 e7b0bef4 e7b0bee8 [ 52.171112] bee0: 80129d68 802d6594 e7b0bf74 e7b0bef8 8012a908 80129d3c e7b0bfac e7b0a000 [ 52.179748] bf00: 806e9840 ef000c00 80710d6c 001e 8921a718 e7b0bf34 800a5940 [ 52.188385] bf20: e7b0a000 8004241c e7b0bf5c e7b0bf38 800a5940 e7b0a000 8011b948 [ 52.197021] bf40: 0001 e7a7ae40 e7b0bf74 c01c670b 0009 401c6447 7e805ea4 e7a7ae40 [ 52.205657] bf60: e7b0a000 e7b0bfa4 e7b0bf78 8012a9f4 8012a3d0 e7b0bfb0 0001 [ 52.214294] bf80: e7b0bfac c01c670b 7e805ea4 401c6447 0036 8000e6e8 e7b0bfa8 [ 52.222900] bfa0: 8000e480 8012a968 c01c670b 7e805ea4 0009 401c6447 7e805ea4 001c [ 52.231536] bfc0: c01c670b 7e805ea4 401c6447 0036 73299748 0131f11c 8003 [ 52.240173] bfe0: 72c13718 7e805e74 72c07d93 4bffa1bc 000d0010 0009 b23010a0 54124c10 [ 52.248809] Backtrace: [ 52.251434] [<7f0275dc>] (create_gem_wrapper+0x0/0x208 [omapdrm_pvr]) from [<7f027c68>] (PVRMMapOSMemHandleToMMapData+0xdc/0x248 [omapdrm_pvr]) [ 52.265075] [<7f027b8c>] (PVRMMapOSMemHandleToMMapData+0x0/0x248 [omapdrm_pvr]) from [<7f03c2e0>] (PVRMMapOSMemHandleToMMapDataBW+0x40/0x50 [omapdrm_pvr]) [ 52.279693] [<7f03c2a0>] (PVRMMapOSMemHandleToMMapDataBW+0x0/0x50 [omapdrm_pvr]) from [<7f03ddf0>] (BridgedDispatchKM+0x104/0x15c [omapdrm_pvr]) [ 52.293334] r4:e7b0be38 [ 52.296051] [<7f03dcec>] (BridgedDispatchKM+0x0/0x15c [omapdrm_pvr]) from [<7f029754>] (PVRSRV_BridgeDispatchKM+0x1cc/0x380 [omapdrm_pvr]) [ 52.309173] r8:0547 r7:c01c670b r6:e7a7af00 r5:e7b0be38 r4:ee51b800 [ 52.316070] r3:c01c6716 [ 52.318878] [<7f029588>] (PVRSRV_BridgeDispatchKM+0x0/0x380 [omapdrm_pvr]) from [<802d6850>] (drm_ioctl+0x2c8/0x3dc) [ 52.329956] r8:e7a7af00 r7:001c r6:401c6447 r5:e7b0be38 r4:ee51b800 [ 52.337036] [<802d6588>] (drm_ioctl+0x0/0x3dc) from [<80129d68>] (vfs_ioctl+0x38/0x4c) [ 52.345397] [<80129d30>] (vfs_ioctl+0x0/0x4c) from [<8012a908>] (do_vfs_ioctl+0x544/0x598) [ 52.354125] [<8012a3c4>] (do_vfs_ioctl+0x0/0x598) from [<8012a9f4>] (sys_ioctl+0x98/0xfc) [ 52.362762] [<8012a95c>] (sys_ioctl+0x0/0xfc) from [<8000e480>] (ret_fast_syscall+0x0/0x30) [ 52.371582] r8:8000e6e8 r7:0036 r6:401c6447 r5:7e805ea4 r4:c01c670b [ 52.378662] Code: e3a02000 ea04 e5941004 e2822001 (e7911003) [ 52.385131] [sched_delayed] sched: RT throttling activated [ 52.391510] ---[ end trace 85cbb443b20a087f ]--- [ 52.885620] gps_init, Receiver reset failed Regards & Thanks, Vikas -- next part -- An HTML attachment was scrubbed... URL: <http://lists.freedesktop.org/archives/dri-devel/attachments/20131219/a0792814/attachment-0001.html>
[Bug 72716] SIGBUS in EVERGREENUploadToScreen after hibernation (Linux 3.12.4-tuxonice)
https://bugs.freedesktop.org/show_bug.cgi?id=72716 txtoxtox285 at googlemail.com changed: What|Removed |Added Assignee|dri-devel at lists.freedesktop |xorg-driver-ati at lists.x.org |.org| -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL: <http://lists.freedesktop.org/archives/dri-devel/attachments/20131219/446d3ce0/attachment.html>
[PATCH] drm/tegra: fix compile w/ CONFIG_DYNAMIC_DEBUG
On Wed, Dec 18, 2013 at 01:53:33PM -0700, Stephen Warren wrote:
> From: Stephen Warren
>
> With CONFIG_DYNAMIC_DEBUG=y, the followin compile error occurs:
>
> drivers/gpu/drm/tegra/mipi-phy.c: In function ?mipi_dphy_timing_validate?:
> drivers/gpu/drm/tegra/mipi-phy.c:69:11: error: ?EINVAL? undeclared (first use
> in this function)
> drivers/gpu/drm/tegra/mipi-phy.c:69:11: note: each undeclared identifier is
> reported only once for each function it appears in
>
> Fix this by directly including the header that defines EINVAL.
>
> Fixes: 39aa0a4f3be5 ("drm/tegra: Add DSI support")
> Signed-off-by: Stephen Warren
> ---
> drivers/gpu/drm/tegra/mipi-phy.c | 1 +
> 1 file changed, 1 insertion(+)
Applied, thanks. I've fixed up the "Fixes:" tag since the commit hash
was no longer valid.
Thierry
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Problems with vgaswitcheroo and prime systems possibly due to ACPI
Hi Rafael Ever since git commit bbd34fcdd1b201e996235731a7c98fd5197d9e51 I've been having issues with vgaswitcheroo and the new runpm code on my laptop I bisected it in bug https://bugs.freedesktop.org/show_bug.cgi?id=71930 and with it being a regression I was hoping you could take a look Thanks Mike -- next part -- An HTML attachment was scrubbed... URL: <http://lists.freedesktop.org/archives/dri-devel/attachments/20131219/71e4e047/attachment-0001.html>
[PATCH] [Intel-gfx] drm/edid: Populate picture aspect ratio for CEA modes
On Thu, Dec 19, 2013 at 5:04 AM, Vandana Kannan
wrote:
> Adding picture aspect ratio for CEA modes based on CEA-861D Table 3 or
> CEA-861E Table 4. This is useful for filling up the detail in AVI
> infoframe.
>
> v2: Ville's review comments incorporated
> Added picture aspect ratio as part of edid_cea_modes instead of DRM_MODE
>
> Signed-off-by: Vandana Kannan
> Reviewed-by: Ville Syrjala
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/drm_edid.c | 128
> ++--
> include/drm/drm_crtc.h |2 +
> 2 files changed, 66 insertions(+), 64 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> index fb7cf0e..20e3784 100644
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c
> @@ -600,347 +600,347 @@ static const struct drm_display_mode edid_cea_modes[]
> = {
> { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
>752, 800, 0, 480, 490, 492, 525, 0,
>DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
> - .vrefresh = 60, },
> + .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
> /* 2 - 720x480 at 60Hz */
> { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
>798, 858, 0, 480, 489, 495, 525, 0,
>DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
> - .vrefresh = 60, },
> + .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
> /* 3 - 720x480 at 60Hz */
> { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
>798, 858, 0, 480, 489, 495, 525, 0,
>DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
> - .vrefresh = 60, },
> + .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
> /* 4 - 1280x720 at 60Hz */
> { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
>1430, 1650, 0, 720, 725, 730, 750, 0,
>DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
> - .vrefresh = 60, },
> + .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
> /* 5 - 1920x1080i at 60Hz */
> { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
>2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
>DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
> DRM_MODE_FLAG_INTERLACE),
> - .vrefresh = 60, },
> + .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
> /* 6 - 1440x480i at 60Hz */
> { DRM_MODE("1440x480i", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1478,
>1602, 1716, 0, 480, 488, 494, 525, 0,
>DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
> DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
> - .vrefresh = 60, },
> + .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
> /* 7 - 1440x480i at 60Hz */
> { DRM_MODE("1440x480i", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1478,
>1602, 1716, 0, 480, 488, 494, 525, 0,
>DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
> DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
> - .vrefresh = 60, },
> + .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
> /* 8 - 1440x240 at 60Hz */
> { DRM_MODE("1440x240", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1478,
>1602, 1716, 0, 240, 244, 247, 262, 0,
>DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
> DRM_MODE_FLAG_DBLCLK),
> - .vrefresh = 60, },
> + .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
> /* 9 - 1440x240 at 60Hz */
> { DRM_MODE("1440x240", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1478,
>1602, 1716, 0, 240, 244, 247, 262, 0,
>DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
> DRM_MODE_FLAG_DBLCLK),
> - .vrefresh = 60, },
> + .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
> /* 10 - 2880x480i at 60Hz */
> { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
>3204, 3432, 0, 480, 488, 494, 525, 0,
>DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
> DRM_MODE_FLAG_INTERLACE),
> - .vrefresh = 60, },
> + .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
> /* 11 - 2880x480i at 60Hz */
> { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
>3204, 3432, 0, 480, 488, 494, 525, 0,
>DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
> DRM_MODE_FLAG_INTERLACE),
> - .vrefresh = 60, },
> +
drm_do_probe_ddc_edid ENXIO check too aggressive?
On Tue, Dec 17, 2013 at 11:12 PM, Daniel Drake wrote: > > On Mon, Dec 16, 2013 at 5:40 PM, Daniel Vetter wrote: > > Have a bit of logic in the exynos ->detect function to re-try a 2nd > > round of edid probing after each hdp interrupt if the first one > > returns an -ENXIO. Only tricky part is to be careful with edge > > detection so that userspace gets all the hotplug events still. > > Presuming you don't have any funkiness with reprobing causing yet > > another hpd interrupt and stuff like that (seen it all), as long as > > you're using the helpers in drm_crtc_helper.c it should all be working > > correctly. So you want a work item which just grabs all modeset locks > > and then calls drm_helper_probe_single_connector_modes or something on > > the right connector. > > Thanks for the tips. Having trouble sticking to those details though. > exynos_drm_connector_detect() is actually a long way away from EDID > probing so it is hard to detect the ENXIO case there. > > What happens here is: > exynos hdmi_irq_thread() calls drm_helper_hpd_irq_event() > That then calls exynos_drm_connector_detect(), which returns a simple > "yes, hpd detection says we are connected" > Then it calls drm_kms_helper_hotplug_event() for which the call chain is: > > drm_kms_helper_hotplug_event > exynos_drm_output_poll_changed > drm_fb_helper_hotplug_event > drm_fb_helper_probe_connector_mode > exynos_drm_connector_fill_modes > drm_helper_probe_single_connector_modes > exynos_drm_connector_get_modes > drm_get_edid > drm_do_get_edid > drm_do_probe_ddc_edid <-- ENXIO in here > > drm_do_probe_ddc_edid actually swallows the ENXIO code and just > returns -1, so that particular error is indistinguishable from others. > > Trying to follow your suggestions, the closest would seem to be something > like: > > 1. Modify exynos_drm_connector_detect to read and cache the EDID right > away. If EDID read fails for any reason, report "no connection" and > schedule a work item to retry the EDID read. If the later EDID read > succeeds, call drm_kms_helper_hotplug_event() > > 2. Modify exynos_drm_connector_get_modes to return cached EDID > > Does that sound sensible? +seanpaul I think the problem is that the hdmi irq is really just an undebounced gpio interrupt, and thus, it is firing way too soon. The chromium kernel adds an excplicit 1.1 second timer to debounce hpd between the hdmi hpd-gpio irq and taking any action (ie reading the edid). I believe this will eventually make its way upstream, but is still pending some other patches: http://git.chromium.org/gitweb/?p=chromiumos/third_party/kernel-next.git;a=blob;f=drivers/gpu/drm/exynos/exynos_hdmi.c;h=1258c67e87f360c846c64bb3f04436a68018b4fe;hb=refs/heads/chromeos-3.8#l2647 -Dan > > Thanks > Daniel > ___ > dri-devel mailing list > dri-devel at lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/dri-devel
[Bug 72685] [radeonsi hyperz] Artifacts in Unigine Sanctuary
https://bugs.freedesktop.org/show_bug.cgi?id=72685 Michel D?nzer changed: What|Removed |Added Attachment #90959|text/plain |image/png mime type|| -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL: <http://lists.freedesktop.org/archives/dri-devel/attachments/20131219/cb6cf06c/attachment.html>
