Hi Javier,
On 10/08/2015 08:40 AM, Yakir Yang wrote:
> On 10/07/2015 07:25 PM, Javier Martinez Canillas wrote:
>> On 10/07/2015 01:05 PM, Yakir Yang wrote:
>>> On 10/07/2015 05:26 PM, Javier Martinez Canillas wrote:
On 10/07/2015 11:02 AM, Yakir Yang wrote:
> On 10/07/2015 04:46 PM,
this mail because:
You are the assignee for the bug.
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Le 10/10/2015 20:41, Ilia Mirkin a écrit :
> Hi Laurent,
>
> On Sat, Oct 10, 2015 at 9:27 AM, Laurent Vivier wrote:
>> On PowerMac G5 (and I think on all OpenFirmware platforms), nvbios_pcirTp()
>> returns NULL. But in fact the OpenFirmware has given us the size
>> we can store in
structureOpen Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
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On Sat, Oct 10, 2015 at 7:45 PM, Laurent Vivier wrote:
>
>
> Le 10/10/2015 21:56, Ilia Mirkin a écrit :
>> On Sat, Oct 10, 2015 at 3:29 PM, Laurent Vivier wrote:
>>>
>>>
>>> Le 10/10/2015 20:41, Ilia Mirkin a écrit :
Hi Laurent,
On Sat, Oct 10, 2015 at 9:27 AM, Laurent Vivier
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This adds support for the BOE TV080WUM-NL0 1200x1920 mipi panel to the
DRM simple panel driver.
Signed-off-by: Chris Zhong
---
drivers/gpu/drm/panel/panel-simple.c | 33 +
1 file changed, 33 insertions(+)
diff --git a/drivers/gpu/drm/panel/panel-simple.c
Add support for Synopsys DesignWare MIPI DSI host controller which is
embedded in the rk3288 SoCs.
Signed-off-by: Chris Zhong
---
drivers/gpu/drm/rockchip/Kconfig| 10 +
drivers/gpu/drm/rockchip/Makefile | 1 +
drivers/gpu/drm/rockchip/dw_mipi_dsi_rockchip.c |
add Synopsys DesignWare MIPI DSI host controller driver support.
Signed-off-by: Chris Zhong
---
drivers/gpu/drm/bridge/Kconfig | 10 +
drivers/gpu/drm/bridge/Makefile |1 +
drivers/gpu/drm/bridge/dw_mipi_dsi.c | 1055 ++
From: Liu Ying
Signed-off-by: Liu Ying
Acked-by: Thierry Reding
Signed-off-by: Chris Zhong
---
include/drm/drm_mipi_dsi.h | 14 ++
1 file changed, 14 insertions(+)
diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h
index
Sometimes the clock driver can not set a accurate clock_rate for vop,
get the true rate of vop_dclk and set it back to adjusted_mode, since
the mipi dsi driver need to use the clock to make the calculation of
Blanking.
Signed-off-by: Chris Zhong
---
drivers/gpu/drm/rockchip/rockchip_drm_vop.c
The rk3288 MIPI DSI is a Synopsys DesignWare MIPI DSI host controller
IP. This series adds support for a Synopsys DesignWare MIPI DSI host
controller DRM bridge driver and a rockchip MIPI DSI specific DRM
driver.
This series also includes a DRM panel driver for BOE TV080WUM-NL0 panel.
This panel
The Nvidia blob allows a pixel clock up to 225 MHz in version 346.59,
but only allowed 165MHz in version 295 for HDMI connections. This was
tested with a GF114 (Nvidia GTX 560 TI) and a HDMI monitor which used
225 MHz pixel clock and a signal link DVI monitor with a pixel clock of
less than 165
Without this patch a pixel clock rate above 165 MHz on a TMDS link is
assumed to be dual link. This is true for DVI, but not for HDMI. HDMI
supports no dual link, but it supports pixel clock rates above 165 MHz.
Only activate Dual Link mode when it is actual possible.
Signed-off-by: Hauke
These patches are adding support for outputting 2560x1440 at 56 over HDMI.
This needs a pixel clock of 225 MHz which was not supported before.
This was tested in a dual monitor setup with a GF114 (GTX 560 TI) and
one HDMI monitor running with 2560x1440 at 56 and one DVI monitor running
with
On Sat, Oct 10, 2015 at 3:29 PM, Laurent Vivier wrote:
>
>
> Le 10/10/2015 20:41, Ilia Mirkin a écrit :
>> Hi Laurent,
>>
>> On Sat, Oct 10, 2015 at 9:27 AM, Laurent Vivier wrote:
>>> On PowerMac G5 (and I think on all OpenFirmware platforms), nvbios_pcirTp()
>>> returns NULL. But in fact the
On PowerMac G5 (and I think on all OpenFirmware platforms), nvbios_pcirTp()
returns NULL. But in fact the OpenFirmware has given us the size
we can store in image->size.
This size is stored in bios->size by of_init() as there is no way
to retrieve it otherwise. And as we know the size, copy all
bug.
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Hi Laurent,
On Sat, Oct 10, 2015 at 9:27 AM, Laurent Vivier wrote:
> On PowerMac G5 (and I think on all OpenFirmware platforms), nvbios_pcirTp()
> returns NULL. But in fact the OpenFirmware has given us the size
> we can store in image->size.
>
> This size is stored in bios->size by of_init() as
The Debian 3.16.0 kernel does not emit the error, but I have not attempted a
bisection.
The warning was added by:
38cc46d drm/i915/bdw: Ack interrupts before handling them (GEN8)
2014-06-18 (1 year, 4 months ago), Oscar Mateo
Follows: v3.15-rc8
Preceedes: 3.17-rc1
This is not present in
Hi,
I noticed that a HSW laptop gets a few new warnings since 4.2-rc
kernels. One error messages pops at each boot time:
Console: switching to colour dummy device 80x25
[drm] Replacing VGA console driver
[drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
[drm] Driver supports
Regards
Shashank
On 10/10/2015 5:24 AM, Emil Velikov wrote:
> Hi Shashank,
>
> On 9 October 2015 at 20:29, Shashank Sharma
> wrote:
>> BDW/SKL/BXT support Color Space Conversion (CSC) using a 3x3 matrix
>> that needs to be programmed into respective CSC registers.
>>
>> This patch does the
Regards
Shashank
On 10/10/2015 5:19 AM, Emil Velikov wrote:
> Hi Shashank,
>
> On 9 October 2015 at 20:29, Shashank Sharma
> wrote:
>> BDW/SKL/BXT supports Degamma color correction feature, which
>> linearizes the non-linearity due to gamma encoded color values.
>> This will be applied before
Regards
Shashank
On 10/10/2015 5:15 AM, Emil Velikov wrote:
> On 9 October 2015 at 20:29, Shashank Sharma
> wrote:
>> Function intel_attach_color_properties_to_crtc attaches a
>> color property to its CRTC object. This patch calls this
>> function from crtc initialization sequence.
>>
>>
Regards
Shashank
On 10/10/2015 5:13 AM, Emil Velikov wrote:
> On 9 October 2015 at 20:29, Shashank Sharma
> wrote:
>> CHV/BSW supports Color Space Conversion (CSC) using a 3x3 matrix
>> that needs to be programmed into CGM (Color Gamut Mapping) registers.
>>
>> This patch does the following:
>>
Regards
Shashank
On 10/10/2015 5:09 AM, Emil Velikov wrote:
> Hi Shashank,
>
> On 9 October 2015 at 20:29, Shashank Sharma
> wrote:
> [snip]
>> diff --git a/drivers/gpu/drm/i915/intel_color_manager.c
>> b/drivers/gpu/drm/i915/intel_color_manager.c
>> index d5315b2..74f8fc3 100644
>> ---
Regards
Shashank
On 10/10/2015 4:54 AM, Emil Velikov wrote:
> Hi Shashank,
>
> On 9 October 2015 at 20:29, Shashank Sharma
> wrote:
>> The color correction blob values are loaded during set_property
>> calls. This patch adds a function to find the blob and apply the
>> correction values to the
Regards
Shashank
On 10/10/2015 4:41 AM, Emil Velikov wrote:
> Hi Shashank,
>
> On 9 October 2015 at 20:29, Shashank Sharma
> wrote:
>> CHV/BSW supports Degamma color correction, which linearizes all
>> the non-linear color values. This will be applied before Color
>> Transformation.
>>
>> This
Regards
Shashank
On 10/10/2015 4:37 AM, Emil Velikov wrote:
> Hi Shashank,
>
> On 9 October 2015 at 20:29, Shashank Sharma
> wrote:
>> CHV/BSW platform supports two different pipe level gamma
>> correction modes, which are:
>> 1. Legacy 8-bit mode
>> 2. 10-bit CGM (Color Gamut Mapping) mode
>>
looks like there's something in the scheduler that either makes it not
happen as often, or not at all (will need to confirm this).
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Regards
Shashank
On 10/10/2015 3:51 AM, Emil Velikov wrote:
> Hi Shashank,
>
> On 9 October 2015 at 20:29, Shashank Sharma
> wrote:
>> From DRM color management:
>>
>> DRM color manager supports these color properties:
>> 1. "ctm": Color transformation matrix
Regards
Shashank
On 10/10/2015 4:17 AM, Emil Velikov wrote:
> Hi Shashank,
>
> On 9 October 2015 at 20:28, Shashank Sharma
> wrote:
> [snip]
>> +
>> +/* Color management bit utilities */
>> +#define GET_BIT_MASK(n) ((1 << n) - 1)
>> +
>> +/* Read bits of a word from bit no. 'start'(lsb) till
Necessary for Daniel's rename commit to apply cleanly.
Signed-off-by: Lukas Wunner
---
Documentation/DocBook/drm.tmpl | 2 --
1 file changed, 2 deletions(-)
diff --git a/Documentation/DocBook/drm.tmpl b/Documentation/DocBook/drm.tmpl
index 308b141..da1060c 100644
---
Regards
Shashank
On 10/10/2015 3:55 AM, Emil Velikov wrote:
> Hi Shashank,
>
> On 9 October 2015 at 20:28, Shashank Sharma
> wrote:
>> As per DRM color manager design, if a userspace wants to set a correction
>> blob, it prepares it and sends the blob_id to kernel via set_property
>> call. DRM
Thanks for the review comments, Emil.
Regards
Shashank
On 10/10/2015 3:53 AM, Emil Velikov wrote:
> Hi Shashank,
>
> On 9 October 2015 at 20:28, Shashank Sharma
> wrote:
>> This patch adds new variables in CRTC state, to hold respective color
>> correction blobs. These blobs will be required
time.
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nology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
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Intel Corporation
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BDW/SKL/BXT support Color Space Conversion (CSC) using a 3x3 matrix
that needs to be programmed into respective CSC registers.
This patch does the following:
1. Adds the core function to program CSC correction values for
BDW/SKL/BXT platform
2. Adds CSC correction macros/defines
BDW/SKL/BXT supports Degamma color correction feature, which
linearizes the non-linearity due to gamma encoded color values.
This will be applied before Color Transformation.
This patch does the following:
1. Adds the core function to program DeGamma correction values for
BDW/SKL/BXT platform
I915 color manager registers pipe degamma correction as palette
correction before CTM, DRM property.
This patch adds the no of coefficients(65) for degamma correction
as "num_samples_before_ctm" parameter in device info structures,
for BDW and higher platforms.
Signed-off-by: Shashank Sharma
BDW/SKL/BXT platforms support various Gamma correction modes
which are:
1. Legacy 8-bit mode
2. 10-bit Split Gamma mode
3. 12-bit mode
This patch does the following:
1. Adds the core function to program Gamma correction values
for BDW/SKL/BXT platforms
2. Adds Gamma correction macros/defines
I915 color manager registers pipe gamma correction as palette
correction after CTM property.
For BDW and higher platforms, split gamma correction is the best
gamma correction. This patch adds the no of coefficients(512) for
split gamma correction as "num_samples_after_ctm" parameter in device
Function intel_attach_color_properties_to_crtc attaches a
color property to its CRTC object. This patch calls this
function from crtc initialization sequence.
Signed-off-by: Shashank Sharma
Signed-off-by: Kausal Malladi
---
drivers/gpu/drm/i915/intel_display.c | 1 +
The color correction blob values are loaded during set_property
calls. This patch adds a function to find the blob and apply the
correction values to the display registers, during the atomic
commit call.
Signed-off-by: Shashank Sharma
Signed-off-by: Kausal Malladi
---
CHV/BSW supports Color Space Conversion (CSC) using a 3x3 matrix
that needs to be programmed into CGM (Color Gamut Mapping) registers.
This patch does the following:
1. Attaches CSC property to CRTC
2. Adds the core function to program CSC correction values
3. Adds CSC correction macros
CHV/BSW supports Degamma color correction, which linearizes all
the non-linear color values. This will be applied before Color
Transformation.
This patch does the following:
1. Attach deGamma property to CRTC
2. Add the core function to program DeGamma correction values for
CHV/BSW platform
2.
CHV/BSW platform supports two different pipe level gamma
correction modes, which are:
1. Legacy 8-bit mode
2. 10-bit CGM (Color Gamut Mapping) mode
This patch does the following:
1. Attaches Gamma property to CRTC
3. Adds the core Gamma correction function for CHV/BSW
4. Adds Gamma correction
DRM color manager allows the driver to showcase its best color
correction capabilities using the specific query property
cm_coeff_before_ctm_property. The driver must loads the no. of
coefficients for color correction as per the platform capability
during the init time.
This patch adds no of
DRM color manager allows the driver to showcase its best color
correction capabilities using the specific query property
cm_coeff_after_ctm_property. The driver must loads the no. of
coefficients for color correction as per the platform capability
during the init time.
This patch adds no of
>From DRM color management:
DRM color manager supports these color properties:
1. "ctm": Color transformation matrix property, where a
color transformation matrix of 9 correction values gets
applied as correction.
2. "palette_before_ctm": for corrections which
This patch create new files intel_color_manager.c which
will contain the core color correction code for I915 driver
and its header intel_color_manager.h
The per color property patches coming up in this patch series
will fill the appropriate functions in this file.
Signed-off-by: Shashank Sharma
This patch adds set property interface for intel CRTC. This
interface will be used for set operation on any DRM properties.
Signed-off-by: Shashank Sharma
Signed-off-by: Kausal Malladi
---
drivers/gpu/drm/i915/intel_display.c | 1 +
1 file changed, 1 insertion(+)
diff --git
Color Manager framework defines a DRM property for color
space transformation and Gamut mapping. This property is called
CTM (Color Transformation Matrix).
This patch adds a new structure in DRM layer for CTM.
This structure can be used by all user space agents to
configure CTM coefficients for
This patch adds new structures in DRM layer for Palette color
correction.These structures will be used by user space agents
to configure appropriate number of samples and Palette LUT for
a platform.
Signed-off-by: Shashank Sharma
Signed-off-by: Kausal Malladi
---
include/uapi/drm/drm.h | 26
As per the DRM get_property implementation for a blob, framework
is supposed to return the blob_id to the caller. All the color
management blobs are saved in CRTC state during the set call.
This patch adds get_property support for color management
properties, by referring to the existing blob for
As per DRM color manager design, if a userspace wants to set a correction
blob, it prepares it and sends the blob_id to kernel via set_property
call. DRM framework takes this blob_id, gets the blob, and saves it
in the CRTC state, so that, during the atomic_commit, the color correction
values from
This patch adds new variables in CRTC state, to hold respective color
correction blobs. These blobs will be required during the atomic commit
for writing the color correction values in correction registers.
Signed-off-by: Shashank Sharma
Signed-off-by: Kausal Malladi
---
DRM color management is written to extract the color correction
capabilities of various platforms, and every platform can showcase
its capabilities using the query properties.
Different hardwares can have different no of coefficients for palette
correction. Also the correction can be applied
Color Management is an extension to DRM framework. It allows
abstraction of hardware color correction and enhancement capabilities
by virtue of DRM properties.
There are two major types of color correction supported by DRM
color manager:
- CTM: color transformation matrix, properties where a
This patch set adds Color Manager implementation in DRM layer. Color Manager
is an extension in DRM framework to support color correction/enhancement.
Various Hardware platforms can support several color correction capabilities.
Color Manager provides abstraction of these capabilities and allows
Hi Shashank,
On 9 October 2015 at 20:29, Shashank Sharma
wrote:
> BDW/SKL/BXT support Color Space Conversion (CSC) using a 3x3 matrix
> that needs to be programmed into respective CSC registers.
>
> This patch does the following:
> 1. Adds the core function to program CSC correction values for
Hi Shashank,
On 9 October 2015 at 20:29, Shashank Sharma
wrote:
> BDW/SKL/BXT supports Degamma color correction feature, which
> linearizes the non-linearity due to gamma encoded color values.
> This will be applied before Color Transformation.
>
> This patch does the following:
> 1. Adds the
On 9 October 2015 at 20:29, Shashank Sharma
wrote:
> Function intel_attach_color_properties_to_crtc attaches a
> color property to its CRTC object. This patch calls this
> function from crtc initialization sequence.
>
> Signed-off-by: Shashank Sharma
> Signed-off-by: Kausal Malladi
Maybe
On 9 October 2015 at 20:29, Shashank Sharma
wrote:
> CHV/BSW supports Color Space Conversion (CSC) using a 3x3 matrix
> that needs to be programmed into CGM (Color Gamut Mapping) registers.
>
> This patch does the following:
> 1. Attaches CSC property to CRTC
> 2. Adds the core function to
Hi Shashank,
On 9 October 2015 at 20:29, Shashank Sharma
wrote:
[snip]
> diff --git a/drivers/gpu/drm/i915/intel_color_manager.c
> b/drivers/gpu/drm/i915/intel_color_manager.c
> index d5315b2..74f8fc3 100644
> --- a/drivers/gpu/drm/i915/intel_color_manager.c
> +++
Hi Shashank,
On 9 October 2015 at 20:29, Shashank Sharma
wrote:
> The color correction blob values are loaded during set_property
> calls. This patch adds a function to find the blob and apply the
> correction values to the display registers, during the atomic
> commit call.
>
> Signed-off-by:
Hi Shashank,
On 9 October 2015 at 20:29, Shashank Sharma
wrote:
> CHV/BSW supports Degamma color correction, which linearizes all
> the non-linear color values. This will be applied before Color
> Transformation.
>
> This patch does the following:
> 1. Attach deGamma property to CRTC
> 2. Add
Hi Shashank,
On 9 October 2015 at 20:29, Shashank Sharma
wrote:
> CHV/BSW platform supports two different pipe level gamma
> correction modes, which are:
> 1. Legacy 8-bit mode
> 2. 10-bit CGM (Color Gamut Mapping) mode
>
> This patch does the following:
> 1. Attaches Gamma property to CRTC
>
On 09/10/2015 at 22:37:33 +0200, Boris Brezillon wrote :
> Add myself as the maintainer of the atmel-hlcdc DRM driver.
>
> Signed-off-by: Boris Brezillon
> ---
> MAINTAINERS | 7 +++
> 1 file changed, 7 insertions(+)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 797236b..11173b5
Hi Shashank,
On 9 October 2015 at 20:28, Shashank Sharma
wrote:
[snip]
> +
> +/* Color management bit utilities */
> +#define GET_BIT_MASK(n) ((1 << n) - 1)
> +
> +/* Read bits of a word from bit no. 'start'(lsb) till 'n' bits */
> +#define GET_BITS(x, start, nbits) ((x >> start) &
Hi Shashank,
On 9 October 2015 at 20:28, Shashank Sharma
wrote:
> As per DRM color manager design, if a userspace wants to set a correction
> blob, it prepares it and sends the blob_id to kernel via set_property
> call. DRM framework takes this blob_id, gets the blob, and saves it
> in the CRTC
Hi Shashank,
On 9 October 2015 at 20:28, Shashank Sharma
wrote:
> This patch adds new variables in CRTC state, to hold respective color
> correction blobs. These blobs will be required during the atomic commit
> for writing the color correction values in correction registers.
>
> Signed-off-by:
Hi Shashank,
On 9 October 2015 at 20:29, Shashank Sharma
wrote:
> From DRM color management:
>
> DRM color manager supports these color properties:
> 1. "ctm": Color transformation matrix property, where a
>color transformation matrix of 9 correction values gets
Hi Eric,
On 9 October 2015 at 22:27, Eric Anholt wrote:
> Signed-off-by: Eric Anholt
> ---
>
> v2: Mark it Supported, not Maintained.
>
> MAINTAINERS | 6 ++
> 1 file changed, 6 insertions(+)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 7ba7ab7..e331e46 100644
> --- a/MAINTAINERS
>
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