hi,
I'm a new programmer, i just was wondering if i can get some docs to
start learning DRI. I googled a lot but i didn't find a starter
documentation. Some refs will be apreciated
thx
es/dri-devel/attachments/20161028/19698d05/attachment-0001.html>
https://bugzilla.kernel.org/show_bug.cgi?id=51381
--- Comment #50 from Alex Deucher ---
Your system does not appear to support powerdown of the dGPU. From your log:
[9.611183] ATPX version 1, functions 0x0181
Bit 1 of the functions should be set if it does.
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Am 28.10.2016 um 19:37 schrieb Mario Kleiner:
>
>
> On 10/28/2016 03:34 AM, Michel Dänzer wrote:
>> On 27/10/16 10:33 PM, Mike Lothian wrote:
>>>
>>> Just another gentle ping to see where you are with this?
>>
>> I haven't got a chance to look into this any further.
>>
>>
>
> Fwiw., as a proof of
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On Fri, 28 Oct 2016 00:03:16 +0200
Maxime Ripard wrote:
> On Tue, Oct 25, 2016 at 04:14:41PM +0200, Jean-Francois Moine wrote:
> > > > +Display controller
> > > > +==
> > > > +
> > > > +Required properties:
> > > > +
> > > > +- compatible: value should be one of the following
> >
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kernel:
https://cgit.freedesktop.org/~agd5f/linux/log/?h=drm-next-4.10-wip
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under Xorg.
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lipping
> without causing any obvious new problems.
>
> -mario
>
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A non-
This defines a helper function to set the property value.
This will be used to set the link status to Bad in case
of link training failures.
v2:
* Simplify the return value (Jani Nikula)
Cc: dri-devel at lists.freedesktop.org
Cc: Jani Nikula
Cc: Daniel Vetter
Cc: Ville Syrjala
Cc: Chris
A new default connector property is added for keeping
track of whether the link is good (link training passed) or
link is bad (link training failed). If the link status property
is not good, then userspace should fire off a new modeset at the current
mode even if there have not been any changes
Hi Meng,
On 2016-09-28 01:24, Meng Yi wrote:
> Gamma correction is optional and can be used to adjust the color
> output values to match the gamut of a particular TFT LCD panel
>
> Split the DCU regs into "regs", "palette", "gamma" and "cursor".
> Create a second regmap for gamma memory space
On 10/28/2016 05:11 PM, Shawn Lin wrote:
> On 2016/10/23 3:18, Randy Li wrote:
>> I found if eDP_AVDD_1V0 and eDP_AVDD_1V8 are not been power at
>> RK3288, once trying to enable the pclk clock, the kernel would dead.
>> This patch would try to enable them first. The eDP_AVDD_1V8 more
>> likely
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On 2016/10/23 3:18, Randy Li wrote:
> I found if eDP_AVDD_1V0 and eDP_AVDD_1V8 are not been power at
> RK3288, once trying to enable the pclk clock, the kernel would dead.
> This patch would try to enable them first. The eDP_AVDD_1V8 more
> likely to be applied to eDP phy, but I have no time to
Hi, Matthias:
Even though OVL HW would not be enabled before component_add() in
current design, your patch would be safe for any situation.
Acked-by CK Hu
Regards,
CK
On Wed, 2016-10-26 at 16:09 +0200, Matthias Brugger wrote:
> The probe function requests the interrupt before initializing
>
.
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> +/* Note we copy the properties from userspace outside of the i915 perf
> + * mutex to avoid an awkward lockdep with mmap_sem.
> + *
> + * Note this function only validates properties in isolation it doesn't
> + * validate that the combination of properties makes sense or that all
> + *
On Fri, 28 Oct 2016, Jani Nikula wrote:
> On Thu, 27 Oct 2016, Manasi Navare wrote:
>> This work struct will be used to schedule a uevent on a separate
>> thread. This will be scheduled after a link train failure during modeset
>> to indicate a modeset retry request. It will get executed after
On Thu, 27 Oct 2016, Manasi Navare wrote:
> This defines a helper function to set the property value.
> This will be used to set the link status to Bad in case
> of link training failures.
>
> Cc: dri-devel at lists.freedesktop.org
> Cc: Jani Nikula
> Cc: Daniel Vetter
> Cc: Ville Syrjala
>
On Thu, 27 Oct 2016, Manasi Navare wrote:
> This work struct will be used to schedule a uevent on a separate
> thread. This will be scheduled after a link train failure during modeset
> to indicate a modeset retry request. It will get executed after the
> current modeset is complete and all locks
Am 28.10.2016 um 13:47 schrieb Christian König:
> Am 24.10.2016 um 11:43 schrieb Grazvydas Ignotas:
>> On Mon, Oct 24, 2016 at 12:13 PM, Christian König
>> wrote:
>>> Am 24.10.2016 um 04:25 schrieb zhoucm1:
On 2016å¹´10æ24æ¥ 02:31, Grazvydas Ignotas wrote:
> It's done in
On 2016-10-19 14:31, Thierry Reding wrote:
> On Wed, Oct 19, 2016 at 02:27:50PM +0200, Thierry Reding wrote:
>> On Tue, Oct 04, 2016 at 05:29:21PM +0200, Peter Rosin wrote:
>>> From: Gustaf Lindström
>>>
>>> The Sharp 15" LQ150X1LG11 panel is an XGA TFT LCD panel.
>>>
>>> The simple-panel driver
The use of drm_cvt_mode() in qxl_add_monitors_config_modes() means that
the resolutions we are going to present to user-space are going to be
rounded down to a multiple of 8. In the QXL arbitrary resolution case,
this is not useful.
This commit forces the actual width/height that was requested by
When the QXL driver receives a QXL_INTERRUPT_CLIENT_MONITORS_CONFIG interrupt,
we currently always notify userspace that there was some hotplug event.
However, gnome-shell/mutter is reacting to this event by attempting a
resolution change, which it does by issueing drmModeRmFB, drmModeAddFB,
and
qdev->gem.objects was initialized directly in qxl_device_init() rather
than going through qxl_gem_init(), and qxl_gem_fini() was never called.
Signed-off-by: Christophe Fergeau
---
drivers/gpu/drm/qxl/qxl_kms.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
The message has to be terminated by a newline as it's not going to get
added automatically.
Signed-off-by: Christophe Fergeau
---
drivers/gpu/drm/qxl/qxl_fb.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/qxl/qxl_fb.c b/drivers/gpu/drm/qxl/qxl_fb.c
index
qxl_crtc_set_from_monitors_config() is defined in qxl_drv.h but never
implemented.
Signed-off-by: Christophe Fergeau
---
drivers/gpu/drm/qxl/qxl_drv.h | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/qxl/qxl_drv.h b/drivers/gpu/drm/qxl/qxl_drv.h
index da41e1f..590ba25
They are not used outside of their respective source file
Signed-off-by: Christophe Fergeau
---
drivers/gpu/drm/qxl/qxl_cmd.c | 2 +-
drivers/gpu/drm/qxl/qxl_display.c | 4 ++--
drivers/gpu/drm/qxl/qxl_drv.h | 3 ---
3 files changed, 3 insertions(+), 6 deletions(-)
diff --git
Hey,
This patch series starts by doing some various small cleanups (patch 1 to 4),
and
then there are 2 fixes for issues which were noticed in fedora 25, the more
annoying one
being the one fixed by patch 5 where the VM screen would constantly flicker
when wayland is used. Patch 6 is very
This error message will be printed when a FIFO underflow irq has
triggered. Since this happens sometimes and the error message will be
displayed on the console, it should have a correct spelling.
Signed-off-by: Daniel Schultz
---
drivers/gpu/drm/tilcdc/tilcdc_crtc.c | 2 +-
1 file changed, 1
The commit d8ff0c63fbcb ("drm/tilcdc: Adjust the FB_CEILING address")
added an adjustment of the FB_CEILING address. This is done by decrementing
the address by one.
On the AM335x (rev 0x4F201000) the framebuffer is rotated left over the
display border, because the ceiling address is 8f276fff
Am 24.10.2016 um 11:43 schrieb Grazvydas Ignotas:
> On Mon, Oct 24, 2016 at 12:13 PM, Christian König
> wrote:
>> Am 24.10.2016 um 04:25 schrieb zhoucm1:
>>>
>>>
>>> On 2016å¹´10æ24æ¥ 02:31, Grazvydas Ignotas wrote:
It's done in amd_sched_hw_job_reset(), but not in normal job processing.
because:
You are on the CC list for the bug.
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https://bugzilla.kernel.org/show_bug.cgi?id=63941
Jani Nikula changed:
What|Removed |Added
Status|NEW |RESOLVED
Resolution|---
On 10/28/2016 10:34 AM, CK Hu wrote:
> Hi, Matthias:
>
> Even though OVL HW would not be enabled before component_add() in
> current design, your patch would be safe for any situation.
Maybe the FW I use left an interrupt pending before loading the kernel
and this leads to the case where we
https://bugzilla.kernel.org/show_bug.cgi?id=178281
--- Comment #15 from fin4478 at hotmail.com ---
New Mesa did not fix this. Playing at fullhd TR Legend still hangs xserver in 3
minutes. Tried 2 times, same effect. Works as good as with an 300Hz overclocked
non debug 4.9-rc2 kernel from
'devm_pinctrl_register()' returns an error pointer or a valid handle. So
checking for NULL here is pointless and can never trigger.
Check the returned value with IS_ERR instead and propagate this value as
done in the other functions which call 'devm_pinctrl_register()'
Fixes: 0751bb5c44fe
On 26 October 2016 at 16:53, Dave Airlie wrote:
> Hi Linus,
>
> This is a standalone pull request for the fix for a regression introduced
> in -rc1 by a change to vm_insert_mixed to start using the PAT range tracking
> to validate page protections. With this fix in place, all the VRAM mappings
>
On 27/10/16 10:33 PM, Mike Lothian wrote:
>
> Just another gentle ping to see where you are with this?
I haven't got a chance to look into this any further.
--
Earthling Michel Dänzer | http://www.amd.com
Libre software enthusiast | Mesa
2016-10-28 Daniel Vetter :
> On Thu, Oct 27, 2016 at 05:37:09PM -0200, Gustavo Padovan wrote:
> > From: Gustavo Padovan
> >
> > There is now a new property called FENCE_FD attached to every plane
> > state that receives the sync_file fd from userspace via the atomic commit
> > IOCTL.
> >
> >
Hi Gustavo,
On Thu, Oct 27, 2016 at 05:37:11PM -0200, Gustavo Padovan wrote:
>From: Gustavo Padovan
>
>Support DRM out-fences by creating a sync_file with a fence for each CRTC
>that sets the OUT_FENCE_PTR property.
>
>We use the out_fence pointer received in the OUT_FENCE_PTR prop to send
>the
Am Donnerstag, den 27.10.2016, 19:26 +0200 schrieb Wladimir J. van der
Laan:
> Hello,
>
> After running kmscube (or another KMS executable) on a i.MX6 QuadPlus
> (etnaviv,
> GC3000) a few times on I get the below crash in the drm kernel driver.
> This is on a device with LVDS panel. It is always
Looking at the ioctl permission checks I noticed that it's impossible
to import gem buffers into a control nodes, and fd2handle/handle2fd
also don't work, so no joy with dma-bufs.
The only way to do anything with a control node is by drawing stuff
into a dumb buffer and displaying that. I suspect
On 10/27/2016 11:03 PM, Xiang, Haihao wrote:
>> -Original Message-
>> From: dri-devel [mailto:dri-devel-bounces at lists.freedesktop.org] On Behalf
>> Of Randy Li
>> Sent: Monday, October 24, 2016 3:59 PM
>> To: libva at lists.freedesktop.org
>> Cc: gwenole.beauchesne at intel.com;
On Thu, Oct 27, 2016 at 05:37:11PM -0200, Gustavo Padovan wrote:
> From: Gustavo Padovan
>
> Support DRM out-fences by creating a sync_file with a fence for each CRTC
> that sets the OUT_FENCE_PTR property.
>
> We use the out_fence pointer received in the OUT_FENCE_PTR prop to send
> the
On Fri, Oct 28, 2016 at 09:42:12AM +0200, Daniel Vetter wrote:
>On Thu, Oct 27, 2016 at 05:37:10PM -0200, Gustavo Padovan wrote:
>> From: Gustavo Padovan
>>
>> Create one timeline context for each CRTC to be able to handle out-fences
>> and signal them. It adds a few members to struct drm_crtc:
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On Wed, Oct 26, 2016 at 03:36:32PM -0400, Lyude wrote:
> Now that these have finally made it into 4.9, it's time to finally backport
> these fixes. Skylake has been a mess in multi-monitor setups for a while now
> because up until recently we've been updating the watermarks on Skylake just
> like
On Thu, Oct 27, 2016 at 05:37:10PM -0200, Gustavo Padovan wrote:
> From: Gustavo Padovan
>
> Create one timeline context for each CRTC to be able to handle out-fences
> and signal them. It adds a few members to struct drm_crtc: fence_context,
> where we store the context we get from
On Thu, Oct 27, 2016 at 05:37:09PM -0200, Gustavo Padovan wrote:
> From: Gustavo Padovan
>
> There is now a new property called FENCE_FD attached to every plane
> state that receives the sync_file fd from userspace via the atomic commit
> IOCTL.
>
> The fd is then translated to a fence (that
On Thu, Oct 27, 2016 at 05:37:08PM -0200, Gustavo Padovan wrote:
> From: Gustavo Padovan
>
> drm_atomic_set_fence_for_plane() is smart and won't overwrite
> plane_state->fence if the user already set an explicit fence there.
>
> Signed-off-by: Gustavo Padovan
Reviewed-by: Daniel Vetter
>
On Thu, Oct 27, 2016 at 05:37:07PM -0200, Gustavo Padovan wrote:
> From: Gustavo Padovan
>
> drm_atomic_set_fence_for_plane() is smart and won't overwrite
> plane_state->fence if the user already set an explicit fence there.
>
> Signed-off-by: Gustavo Padovan
Process nit: Please make sure you
On Fri, Oct 28, 2016 at 09:30:26AM +0200, Daniel Vetter wrote:
> On Thu, Oct 27, 2016 at 05:37:06PM -0200, Gustavo Padovan wrote:
> > From: Gustavo Padovan
> >
> > This new function should be used by drivers when setting a implicit
> > fence for the plane. It abstracts the fact that the user
On Thu, Oct 27, 2016 at 05:37:06PM -0200, Gustavo Padovan wrote:
> From: Gustavo Padovan
>
> This new function should be used by drivers when setting a implicit
> fence for the plane. It abstracts the fact that the user might have
> chosen explicit fencing instead.
>
> Signed-off-by: Gustavo
https://bugzilla.kernel.org/show_bug.cgi?id=178281
--- Comment #14 from fin4478 at hotmail.com ---
One hour ago published Oibaf Mesa fixed Xserver hanging when playing TR Legend
at fullhd.
https://launchpad.net/~oibaf/+archive/ubuntu/graphics-drivers/+packages
--
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https://bugzilla.kernel.org/show_bug.cgi?id=178281
--- Comment #13 from fin4478 at hotmail.com ---
I tested latest drm-next-4.10-wip today that have couple of more patches that
yesterday. Still Xserver hangs when playing Tomb Raider Legend at full hd.
With dmesg, I have these errors at boot:
[
https://bugzilla.kernel.org/show_bug.cgi?id=178281
--- Comment #12 from fin4478 at hotmail.com ---
With Tomb Raider Legend the game hangs Xserver in one minute when playing at
fullhd.Dropping resolution to 720p allows to play stable. drm-next-4.10-wip and
Oipaf ppa mesa from yesterday used. There
In particular this tries to capture for posterity some of the early
challenges we had with using the core perf infrastructure in case we
ever want to revisit adapting perf for device metrics.
Cc: Chris Wilson
Signed-off-by: Robert Bragg
Reviewed-by: Matthew Auld
---
This adds 'compute', 'compute extended', 'memory reads', 'memory writes'
and 'sampler balance' metric sets for Haswell.
The code is auto generated from an XML description of metric sets,
currently maintained in gputop, ref:
https://github.com/rib/gputop
> gputop-data/oa-*.xml
>
The minimal sampling period is now configurable via a
dev.i915.oa_min_timer_exponent sysctl parameter.
Following the precedent set by perf, the default is the minimum that
won't (on its own) exceed the default kernel.perf_event_max_sample_rate
default of 10 samples/s.
Signed-off-by: Robert
Consistent with the kernel.perf_event_paranoid sysctl option that can
allow non-root users to access system wide cpu metrics, this can
optionally allow non-root users to access system wide OA counter metrics
from Gen graphics hardware.
Signed-off-by: Robert Bragg
Reviewed-by: Matthew Auld
---
Each metric set is given a sysfs entry like:
/sys/class/drm/card0/metrics//id
This allows userspace to enumerate the specific sets that are available
for the current system. The 'id' file contains an unsigned integer that
can be used to open the associated metric set via
Gen graphics hardware can be set up to periodically write snapshots of
performance counters into a circular buffer via its Observation
Architecture and this patch exposes that capability to userspace via the
i915 perf interface.
v2:
Make sure to initialize ->specific_ctx_id when opening,
Adds a static OA unit, MUX + B Counter configuration for basic render
metrics on Haswell. This is auto generated from an XML
description of metric sets, currently maintained in gputop, ref:
https://github.com/rib/gputop
> gputop-data/oa-*.xml
> scripts/i915-perf-kernelgen.py
$ make -C
Being able to program OACONTROL from a non-privileged batch buffer is
not sufficient to be able to configure the OA unit. This was originally
allowed to help enable Mesa to expose OA counters via the
INTEL_performance_query extension, but the current implementation based
on programming OACONTROL
check_cmd() is checking whether a command adheres to certain
restrictions that ensure it's safe to execute within a privileged batch
buffer. Returning false implies a privilege problem, not that the
command is invalid.
The distinction makes the difference between allowing the buffer to be
OACONTROL changes quite a bit for gen8, with some bits split out into a
per-context OACTXCONTROL register. Rename now before adding more gen7 OA
registers
Signed-off-by: Robert Bragg
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/gvt/handlers.c| 2 +-
Adds base i915 perf infrastructure for Gen performance metrics.
This adds a DRM_IOCTL_I915_PERF_OPEN ioctl that takes an array of uint64
properties to configure a stream of metrics and returns a new fd usable
with standard VFS system calls including read() to read typed and sized
records; ioctl()
From: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_gem_context.c | 34 ++---
2 files changed, 24 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h
Rebased on nightly, and updated as per review from Matt and Chris
The first patch from Chris adds an i915_gem_context_pin_legacy() utility that
I'm depending on now - though it doesn't really form part of the i915-perf
series proper. I'm assuming Chris plans to send a version of this to the list
From: Kuninori Morimoto
Current dw-hdmi is supporting sound via AHB bus, but it has
I2S audio feature too. This patch adds I2S audio support to dw-hdmi.
This HDMI I2S is supported by using ALSA SoC common HDMI encoder
driver.
Signed-off-by: Kuninori Morimoto
On Fri, Oct 21, 2016 at 3:44 PM, Jean-Francois Moine wrote:
> Allwinner's SoCs include support for both audio and video on HDMI.
> This patch defines a simple audio CODEC which may be used in sunxi
> HDMI video drivers.
>
> Signed-off-by: Jean-Francois Moine
There's already a driver for
> + chan = plane2layer[plane_ix].chan;
> > > + layer = plane2layer[plane_ix].layer;
> > > +
> > > + mux_o += (lcd_num == 0) ? DE_MUX0_BASE : DE_MUX1_BASE;
> > > + chan_o = mux_o;
> > > + chan_o += DE_MUX_CHAN_REGS + DE_MUX_CHAN_SZ * chan;
> > > +
> > > + /* (only 2 layers) */
> > > + if (chan == 0) {
> > > + if (vi_read(chan_o, cfg[1 - layer].attr) == 0)
> > > + chan_disable = 1;
> > > + } else {
> > > + if (ui_read(chan_o, cfg[1 - layer].attr) == 0)
> > > + chan_disable = 1;
> > > + }
> > > +
> > > + spin_lock_irqsave(_lock, flags);
> > > +
> > > + fcolor = bld_read(mux_o + DE_MUX_BLD_REGS, fcolor_ctl);
> > > +
> > > + de_lcd_select(priv, lcd_num, mux_o);
> > > +
> > > + if (chan == 0)
> > > + vi_write(chan_o, cfg[layer].attr, 0);
> > > + else
> > > + ui_write(chan_o, cfg[layer].attr, 0);
> > > +
> > > + if (chan_disable)
> > > + bld_write(mux_o + DE_MUX_BLD_REGS, fcolor_ctl,
> > > + fcolor & ~(0x100 << plane2layer[plane_ix].pipe));
> > > +
> > > + spin_unlock_irqrestore(_lock, flags);
> > > +}
> >
> > Can't you just disable it?
>
> Which 'it'? A layer must be disabled and it is not useful to let the
> DE2 processor to scan a pipe (channel) without any layer.
Oh, so that's what it does.
I really think that you should put as much comments as possible on
what you found out working on this, especially because of the lack of
documentation.
> > > +static int __init de2_drm_init(void)
> > > +{
> > > + int ret;
> > > +
> > > +/* uncomment to activate the drm traces at startup time */
> > > +/* drm_debug = DRM_UT_CORE | DRM_UT_DRIVER | DRM_UT_KMS |
> > > + DRM_UT_PRIME | DRM_UT_ATOMIC; */
> >
> > That's useless.
>
> Right, but it seems that some people don't know how to debug a DRM
> driver. This is only a reminder.
>
> > > + DRM_DEBUG_DRIVER("\n");
> > > +
> > > + ret = platform_driver_register(_lcd_platform_driver);
> > > + if (ret < 0)
> > > + return ret;
> > > +
> > > + ret = platform_driver_register(_drm_platform_driver);
> > > + if (ret < 0)
> > > + platform_driver_unregister(_lcd_platform_driver);
> > > +
> > > + return ret;
> > > +}
> >
> > And that really shouldn't be done that way.
>
> May you explain?
This goes against the whole idea of the device and driver
model. Drivers should only register themselves, device should be
created by buses (or by using some external components if the bus
can't: DT, ACPI, etc.). If there's a match, you get probed.
A driver that creates its own device just to probe itself violates
that.
> > > +int de2_plane_init(struct drm_device *drm, struct lcd *lcd)
> > > +{
> > > + int ret, possible_crtcs = 1 << lcd->crtc_idx;
> > > +
> > > + ret = de2_one_plane_init(drm, >planes[DE2_PRIMARY_PLANE],
> > > + DRM_PLANE_TYPE_PRIMARY, possible_crtcs,
> > > + ui_formats, ARRAY_SIZE(ui_formats));
> > > + if (ret >= 0)
> > > + ret = de2_one_plane_init(drm, >planes[DE2_CURSOR_PLANE],
> > > + DRM_PLANE_TYPE_CURSOR, possible_crtcs,
> > > + ui_formats, ARRAY_SIZE(ui_formats));
> >
> > Nothing looks really special about that cursor plane. Any reasion not
> > to make it an overlay?
>
> As explained above (channel/layer/pipe plane definitions), the cursor
> cannot go in a channel lower or equal to the one of the primary plane.
> Then, it must be known and, so, have an explicit plane.
If you were to make it a plane, you could use atomic_check to check
this and make sure this doesn't happen. And you would gain a generic
plane that can be used for other purposes if needed.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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Hi Gustavo,
Thanks for looking at the patch.
> 2016-10-20 Shawn Guo :
>
> > It adds the initial ZTE VOU display controller DRM driver. There are
> > still some features to be added, like overlay plane, scaling, and more
> > output devices support. But it's already useful with dual CRTCs and
>
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