Re: [PATCH v4 25/26] [DO NOT MERGE] arm64: dts: allwinner: bananapi-m64: Bananapi S070WV20-CT16 DSI panel

2018-11-13 Thread Chen-Yu Tsai
On Wed, Nov 14, 2018 at 2:31 PM Jagan Teki wrote: > > On Tue, Nov 13, 2018 at 5:52 PM Andre Przywara wrote: > > > > On Tue, 13 Nov 2018 16:46:32 +0530 > > Jagan Teki wrote: > > > > Hi, > > > > > This patch add support for Bananapi S070WV20-CT16 DSI panel to > > > BPI-M64 board. > > > > > > DSI

[Bug 108613] amdgpu.dc=1 + xf86-video-amdgpu: changing to a GPU upscaling resolution resets pp_dpm_mclk

2018-11-13 Thread bugzilla-daemon
https://bugs.freedesktop.org/show_bug.cgi?id=108613 --- Comment #7 from bmil...@gmail.com --- I gave up trying to use my monitor at it's supported 75hz. Locking mclk to fix flickering works only temporarily because it resets at certain events (sleep/wake, resolution changes). Why is this

[Bug 108322] RX580 Display flickering after waking from suspend

2018-11-13 Thread bugzilla-daemon
https://bugs.freedesktop.org/show_bug.cgi?id=108322 --- Comment #14 from bmil...@gmail.com --- Problem still present for me on kernels 4.18, 4.19, 4.20 and 4.21-drm-next -- You are receiving this mail because: You are the assignee for the bug.___

[Bug 108710] Since 4.20 kernel Vega 56 hangs when I surf pages in steam client

2018-11-13 Thread bugzilla-daemon
https://bugs.freedesktop.org/show_bug.cgi?id=108710 --- Comment #3 from mikhail.v.gavri...@gmail.com --- Created attachment 142458 --> https://bugs.freedesktop.org/attachment.cgi?id=142458=edit dmesg 4.20 rc2 -- You are receiving this mail because: You are the assignee for the

[Bug 108710] Since 4.20 kernel Vega 56 hangs when I surf pages in steam client

2018-11-13 Thread bugzilla-daemon
https://bugs.freedesktop.org/show_bug.cgi?id=108710 --- Comment #2 from mikhail.v.gavri...@gmail.com --- Unfortunately in 4.20 rc2 this annoying bug still not fixed -- You are receiving this mail because: You are the assignee for the bug.___ dri-devel

[PATCH v9 23/24] i915/dp/fec: Configure the Forward Error Correction bits.

2018-11-13 Thread Manasi Navare
From: Anusha Srivatsa If FEC is supported, the corresponding DP_TP_CTL register bits have to be configured. The driver has to program the FEC_ENABLE in DP_TP_CTL[30] register and wait till FEC_STATUS in DP_TP_CTL[28] is 1. Also add the warn message to make sure that the control register is

[PATCH v9 19/24] drm/i915/dsc: Enable and disable appropriate power wells for VDSC

2018-11-13 Thread Manasi Navare
A separate power well 2 (PG2) is required for VDSC on eDP transcoder whereas all other transcoders use the power wells associated with the transcoders for VDSC. This patch adds a helper to obtain correct power domain depending on transcoder being used and enables/disables the power wells during

[PATCH v9 20/24] drm/i915/dsc: Add Per connector debugfs node for DSC support/enable

2018-11-13 Thread Manasi Navare
DSC can be supported per DP connector. This patch adds a per connector debugfs node to expose DSC support capability by the kernel. The same node can be used from userspace to force DSC enable. force_dsc_en written through this debugfs node is used to force DSC even for lower resolutions. v4: *

[PATCH v9 14/24] drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling

2018-11-13 Thread Manasi Navare
After encoder->pre_enable() hook, after link training sequence is completed, PPS registers for DSC encoder are configured using the DSC state parameters in intel_crtc_state as part of DSC enabling routine in the source. DSC enabling routine is called after encoder->pre_enable() before enbaling the

[PATCH v9 21/24] i915/dp/fec: Add fec_enable to the crtc state.

2018-11-13 Thread Manasi Navare
From: Anusha Srivatsa For DP 1.4 and above, Display Stream compression can be enabled only if Forward Error Correctin can be performed. Add a crtc state for FEC. Currently, the state is determined by platform, DP and DSC being enabled. Moving forward we can use the state to have error

[PATCH v9 24/24] drm/i915/fec: Disable FEC state.

2018-11-13 Thread Manasi Navare
From: Anusha Srivatsa Set the suitable bits in DP_TP_CTL to stop bit correction when DSC is disabled. v2: - rebased. - Add additional check for compression state. (Gaurav) v3: rebased. v4: - Move the code to the proper spot according to spec (Ville) - Use proper checks (manasi) v5: Remove

[PATCH v9 22/24] drm/i915/fec: Set FEC_READY in FEC_CONFIGURATION

2018-11-13 Thread Manasi Navare
From: Anusha Srivatsa If the panel supports FEC, the driver has to set the FEC_READY bit in the dpcd register: FEC_CONFIGURATION. This has to happen before link training. v2: s/intel_dp_set_fec_ready/intel_dp_sink_set_fec_ready - change commit message. (Gaurav) v3: rebased. (r-b Manasi)

[PATCH v9 18/24] drm/i915/dp: Disable DSC in source by disabling DSS CTL bits

2018-11-13 Thread Manasi Navare
1. Disable Left/right VDSC branch in DSS Ctrl reg depending on the number of VDSC engines being used 2. Disable joiner in DSS Ctrl reg v4: * Remove encoder, make crtc_state const (Ville) v3 (From Manasi): * Add Disable PG2 for VDSC on eDP v2 (From Manasi): * Use old_crtc_state to find dsc

[PATCH v9 15/24] drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs

2018-11-13 Thread Manasi Navare
Infoframes are used to send secondary data packets. This patch adds support for DSC Picture parameter set secondary data packets in the existing write_infoframe helpers. v3: * Unused variables cleanup (Ville) v2: * Rebase on drm-tip (Manasi) Cc: Jani Nikula Cc: Ville Syrjala Cc: Anusha

[PATCH v9 06/24] drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants

2018-11-13 Thread Manasi Navare
DSC specification defines linebuf_depth which contains the line buffer bit depth used to generate the bitstream. These values are defined as per Table 4.1 in DSC 1.2 spec v2 (From Manasi): * Rename as MAX_LINEBUF_DEPTH for DSC 1.1 and DSC 1.2 Cc: dri-devel@lists.freedesktop.org Cc: Jani Nikula

[PATCH v9 10/24] drm/i915/dsc: Define & Compute VESA DSC params

2018-11-13 Thread Manasi Navare
From: Gaurav K Singh This patches does the following: 1. This patch defines all the DSC parameters as per the VESA DSC specification. These are stored in the encoder and used to compute the PPS parameters to be sent to the Sink. 2. Compute all the DSC parameters which are derived from DSC state

[PATCH v9 12/24] drm/i915/dp: Enable/Disable DSC in DP Sink

2018-11-13 Thread Manasi Navare
From: Gaurav K Singh This patch enables decompression support in sink device before link training and disables the same during the DDI disabling. v3 (From manasi): * Pass bool state to enable/disable (Ville) v2:(From Manasi) * Change the enable/disable function to take crtc_state instead of

[PATCH v9 03/24] drm/dsc: Define VESA Display Stream Compression Capabilities

2018-11-13 Thread Manasi Navare
This defines all the DSC parameters as per the VESA DSC spec that will be required for DSC encoder/decoder v6: (From Manasi) * Add a bit mask for RANGE_BPG_OFFSET for 6 bits(Manasi) v5 (From Manasi) * Add the RC constants as per the spec v4 (From Manasi) * Add the DSC_MUX_WORD_SIZE constants

[PATCH v9 07/24] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state

2018-11-13 Thread Manasi Navare
Basic DSC parameters and DSC configuration data needs to be computed for each of the requested mode during atomic check. This is required since for certain modes, valid DSC parameters and config data might not be computed in which case compression cannot be enabled for that mode. For that reason

[PATCH v9 11/24] drm/i915/dsc: Compute Rate Control parameters for DSC

2018-11-13 Thread Manasi Navare
From: Gaurav K Singh This computation of RC params happens in the atomic commit phase during compute_config() to validate if display stream compression can be enabled for the requested mode. v7 (From Manasi): * Use DRM_DEBUG instead of DRM_ERROR (Ville) * Use Error numberinstead of -1 (Ville)

[PATCH v9 13/24] drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI

2018-11-13 Thread Manasi Navare
On Icelake, a separate power well PG2 is created for VDSC engine used for eDP/MIPI DSI. This patch adds a new display power domain for Power well 2. v3: * Call it POWER_DOMAIN_TRANSCODER_EDP_VDSC (Ville) * Move it around TRANSCODER power domain defs (Ville) v2: * Fix the power well mismatch CI

[PATCH v9 16/24] drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes

2018-11-13 Thread Manasi Navare
DSC PPS secondary data packet infoframes are filled with DSC picure parameter set metadata according to the DSC standard. These infoframes are sent to the sink device and used during DSC decoding. v3: * Rename to intel_dp_write_pps_sdp (Ville) * Use const intel_crtc_state (Ville) v2: * Rebase ond

[PATCH v9 08/24] drm/i915/dp: Compute DSC pipe config in atomic check

2018-11-13 Thread Manasi Navare
DSC params like the enable, compressed bpp, slice count and dsc_split are added to the intel_crtc_state. These parameters are set based on the requested mode and available link parameters during the pipe configuration in atomic check phase. These values are then later used to populate the

[PATCH v9 01/24] drm/dsc: Modify DRM helper to return complete DSC color depth capabilities

2018-11-13 Thread Manasi Navare
DSC DPCD color depth register advertises its color depth capabilities by setting each of the bits that corresponding to a specific color depth. This patch defines those specific color depths and adds a helper to return an array of color depth capabilities. Signed-off-by: Manasi Navare Cc: Ville

[PATCH v9 02/24] drm/dsc: Define Display Stream Compression PPS infoframe

2018-11-13 Thread Manasi Navare
This patch defines a new header file for all the DSC 1.2 structures and creates a structure for PPS infoframe which will be used to send picture parameter set secondary data packet for display stream compression. All the PPS infoframe syntax elements are taken from DSC 1.2 specification from VESA.

[PATCH v9 04/24] drm/dsc: Define Rate Control values that do not change over configurations

2018-11-13 Thread Manasi Navare
From: "Srivatsa, Anusha" DSC has some Rate Control values that remain constant across all configurations. These are as per the DSC standard. v3: * Define them in drm_dsc.h as they are DSC constants (Manasi) v2: * Add DP_DSC_ prefix (Jani Nikula) Cc: dri-devel@lists.freedesktop.org Cc: Manasi

[PATCH v9 05/24] drm/dsc: Add helpers for DSC picture parameter set infoframes

2018-11-13 Thread Manasi Navare
According to Display Stream compression spec 1.2, the picture parameter set metadata is sent from source to sink device using the DP Secondary data packet. An infoframe is formed for the PPS SDP header and PPS SDP payload bytes. This patch adds helpers to fill the PPS SDP header and PPS SDP

[PATCH v9 00/24] Remaining DSC + FEC patches

2018-11-13 Thread Manasi Navare
This patch series addresses review comments from DSC patch set: https://patchwork.freedesktop.org/series/51986/ and FEc patch set: https://patchwork.freedesktop.org/series/47848/ Anusha Srivatsa (4): i915/dp/fec: Add fec_enable to the crtc state. drm/i915/fec: Set FEC_READY in

[PATCH v9 17/24] drm/i915/dp: Configure Display stream splitter registers during DSC enable

2018-11-13 Thread Manasi Navare
Display Stream Splitter registers need to be programmed to enable the joiner if two DSC engines are used and also to enable the left and the right DSC engines. This happens as part of the DSC enabling routine in the source in atomic commit. v4: * Remove redundant comment (Ville) v3: * Use

[PATCH v9 09/24] drm/i915/dp: Do not enable PSR2 if DSC is enabled

2018-11-13 Thread Manasi Navare
If a eDP panel supports both PSR2 and VDSC, our HW cannot support both at a time. Give priority to PSR2 if a requested resolution can be supported without compression else enable VDSC and keep PSR2 disabled. v4: Fix the unrealted stuff removed during rebase (Ville) v3: * Rebase v2: * Add warning

Re: [Intel-gfx] [RFC v5 2/8] drm: Add Plane Degamma properties

2018-11-13 Thread Matt Roper
On Sun, Sep 16, 2018 at 01:45:25PM +0530, Uma Shankar wrote: > Add Plane Degamma as a blob property and plane degamma size as > a range property. > > v2: Rebase > > v3: Fixed Sean, Paul's review comments. Moved the property from > mode_config to drm_plane. Created a helper function to

Re: [git pull] drm fixes for 4.20-rc2

2018-11-13 Thread pr-tracker-bot
The pull request you sent on Sun, 11 Nov 2018 04:43:57 +1000: > git://anongit.freedesktop.org/drm/drm tags/drm-fixes-2018-11-11 has been merged into torvalds/linux.git: https://git.kernel.org/torvalds/c/20ef6d06ef9a31a33516637a80521b9fc7f1f849 Thank you! -- Deet-doot-dot, I am a bot.

Re: [PATCH 6/8] drm/msm: dpu: Separate crtc assignment from vblank enable

2018-11-13 Thread Jeykumar Sankaran
On 2018-11-13 12:52, Sean Paul wrote: From: Sean Paul Instead of assigning/clearing the crtc on vblank enable/disable, we can just assign and clear the crtc on modeset. That allows us to just toggle the encoder's vblank interrupts on vblank_enable. So why is this important? Previously the

Re: [PATCH 7/8] drm/msm: dpu: Remove vblank_requested flag from dpu_crtc

2018-11-13 Thread Jeykumar Sankaran
On 2018-11-13 12:52, Sean Paul wrote: From: Sean Paul It's just for debug output, we don't need it Signed-off-by: Sean Paul --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 6 -- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 2 -- drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 14

Re: [PATCH 3/8] drm/msm: dpu: Remove vblank_callback from encoder

2018-11-13 Thread Jeykumar Sankaran
On 2018-11-13 12:52, Sean Paul wrote: From: Sean Paul The indirection of registering a callback and opaque pointer isn't real useful when there's only one callsite. So instead of having the vblank_cb registration, just give encoder a crtc and let it directly call the vblank handler. In a

[Bug 201067] [bisected] [4.19-rc2 regression] Display corruption with Vega 64 in 4.19-rc2

2018-11-13 Thread bugzilla-daemon
https://bugzilla.kernel.org/show_bug.cgi?id=201067 --- Comment #10 from Benjamin Xiao (ben.r.x...@gmail.com) --- (In reply to Nicholas Kazlauskas from comment #3) > Created attachment 278455 [details] > 0001-drm-amd-display-Use-higher-dispclk-value-for-dce120.patch > > Do you mind testing

[Bug 201067] [bisected] [4.19-rc2 regression] Display corruption with Vega 64 in 4.19-rc2

2018-11-13 Thread bugzilla-daemon
https://bugzilla.kernel.org/show_bug.cgi?id=201067 --- Comment #9 from Benjamin Xiao (ben.r.x...@gmail.com) --- I get the same visual corruption as well. It only appears when I run the monitor at 144Hz. 120Hz seems fine. -- You are receiving this mail because: You are watching the assignee of

[Bug 102322] System crashes after "[drm] IP block:gmc_v8_0 is hung!" / [drm] IP block:sdma_v3_0 is hung!

2018-11-13 Thread bugzilla-daemon
https://bugs.freedesktop.org/show_bug.cgi?id=102322 --- Comment #68 from dwagner --- Tested today's current amd-staging-drm-next git head, to see if there has been any improvement over the last two months. The bad news: The 3-fps-video-replay test still crashes the driver reproducably after few

Re: Sound and the TDA998x binding

2018-11-13 Thread Russell King - ARM Linux
On Tue, Nov 13, 2018 at 08:58:15PM +, Peter Rosin wrote: > On 2018-11-13 20:09, Russell King - ARM Linux wrote: > > On Tue, Nov 13, 2018 at 06:12:37PM +, Peter Rosin wrote: > >> On 2018-11-13 18:24, Russell King - ARM Linux wrote: > >>> On Tue, Nov 13, 2018 at 01:28:40PM +, Peter Rosin

[PATCH v2 3/3] drm/i915/gen9+: Add support for pipe background color (v2)

2018-11-13 Thread Matt Roper
Gen9+ platforms allow CRTC's to be programmed with a background/canvas color below the programmable planes. Let's expose this for use by compositors. v2: - Split out bgcolor sanitization and programming of csc/gamma bits to a separate patch that we can land before the ABI changes are ready

[PATCH v2 0/3] CRTC background color

2018-11-13 Thread Matt Roper
This is a second revision of the series previously posted here: https://lists.freedesktop.org/archives/intel-gfx/2018-October/178202.html As noted before, this functionality adds new ABI so we need a userspace consumer ready before we merge the kernel work. My understanding is that some of

[PATCH v2 2/3] drm: Add CRTC background color property (v2)

2018-11-13 Thread Matt Roper
Some display controllers can be programmed to present non-black colors for pixels not covered by any plane (or pixels covered by the transparent regions of higher planes). Compositors that want a UI with a solid color background can potentially save memory bandwidth by setting the CRTC background

[PATCH] drm/dp_mst: Skip validating ports during destruction, just ref

2018-11-13 Thread Lyude Paul
Jerry Zuo pointed out a rather obscure hotplugging issue that it seems I accidentally introduced into DRM two years ago. Pretend we have a topology like this: |- DP-1: mst_primary |- DP-4: active display |- DP-5: disconnected |- DP-6: active hub |- DP-7: active display |-

Re: [PATCH 1/2] drm/vc4: Fix NULL pointer dereference in the async update path

2018-11-13 Thread Boris Brezillon
On Tue, 13 Nov 2018 13:24:07 -0800 Eric Anholt wrote: > Boris Brezillon writes: > > > vc4_plane_atomic_async_update() calls vc4_plane_atomic_check() > > which in turn calls vc4_plane_setup_clipping_and_scaling(), and since > > commit 58a6a36fe8e0 ("drm/vc4: Use > >

Re: [PATCH 4/4] drm/v3d: Add support for submitting jobs to the TFU.

2018-11-13 Thread Eric Anholt
Eric Anholt writes: > The TFU can copy from raster, UIF, and SAND input images to UIF output > images, with optional mipmap generation. This will certainly be > useful for media EGL image input, but is also useful immediately for > mipmap generation without bogging the V3D core down. > > For

Re: [PATCH 1/2] drm/vc4: Fix NULL pointer dereference in the async update path

2018-11-13 Thread Eric Anholt
Boris Brezillon writes: > vc4_plane_atomic_async_update() calls vc4_plane_atomic_check() > which in turn calls vc4_plane_setup_clipping_and_scaling(), and since > commit 58a6a36fe8e0 ("drm/vc4: Use > drm_atomic_helper_check_plane_state() to simplify the logic"), this > function accesses

Re: [PATCH 2/2] drm/vc4: Set ->legacy_cursor_update to false when doing non-async updates

2018-11-13 Thread Eric Anholt
Boris Brezillon writes: > drm_atomic_helper_setup_commit() auto-completes commit->flip_done when > state->legacy_cursor_update is true, but we now for sure that we want > a sync update when we call drm_atomic_helper_setup_commit() from > vc4_atomic_commit(). > > Explicitly set

Re: [PATCH 1/8] drm/msm: dpu: Move pm_runtime_(get|put) from vblank_enable

2018-11-13 Thread Sean Paul
On Tue, Nov 13, 2018 at 03:52:44PM -0500, Sean Paul wrote: > From: Sean Paul I neglected to add --cover-letter to send-email, so pasting my cover here instead: Hi all, So I kept digging into the locking and dependencies around encoder/crtc and this is the latest series to pop out. I think

[PATCH 6/8] drm/msm: dpu: Separate crtc assignment from vblank enable

2018-11-13 Thread Sean Paul
From: Sean Paul Instead of assigning/clearing the crtc on vblank enable/disable, we can just assign and clear the crtc on modeset. That allows us to just toggle the encoder's vblank interrupts on vblank_enable. So why is this important? Previously the driver was using the legacy pointers to

[PATCH 7/8] drm/msm: dpu: Remove vblank_requested flag from dpu_crtc

2018-11-13 Thread Sean Paul
From: Sean Paul It's just for debug output, we don't need it Signed-off-by: Sean Paul --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 6 -- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 2 -- drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 14 -- 3 files changed, 4 insertions(+),

[PATCH 5/8] drm/msm: dpu: Don't bother checking ->enabled in dpu_crtc_vblank

2018-11-13 Thread Sean Paul
From: Sean Paul The drm_crtc_vblank_on/off calls in enable/disable guarantee that we won't call this function when crtc is not enabled. Signed-off-by: Sean Paul --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git

[PATCH 8/8] drm/msm: dpu: Remove crtc_lock

2018-11-13 Thread Sean Paul
From: Sean Paul Each time it's called we're holding the crtc modeset lock, so it's redundant. Signed-off-by: Sean Paul --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 11 --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 3 --- 2 files changed, 14 deletions(-) diff --git

[PATCH 2/8] drm/msm: dpu: Remove crtc_lock from setup_mixers

2018-11-13 Thread Sean Paul
From: Sean Paul I think the intention here was to protect the enc->crtc access, but that's insufficient to avoid enc->crtc changing. Fortunately we're already holding the modeset lock when this is called (from atomic_check), so remove the crtc_lock and add a modeset lock check. While we're at

[PATCH 4/8] drm/msm: dpu: Use atomic_disable for dpu_crtc_disable

2018-11-13 Thread Sean Paul
From: Sean Paul Matches dpu_crtc_enable and we'll need the old state in a future patch Signed-off-by: Sean Paul --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

[PATCH 1/8] drm/msm: dpu: Move pm_runtime_(get|put) from vblank_enable

2018-11-13 Thread Sean Paul
From: Sean Paul There are 4 times that _dpu_crtc_vblank_enable_no_lock() is called: 1- crtc enable 2- crtc disable 3- crtc vblank enable 4- crtc vblank disable When we enable or disable the crtc, we call drm_crtc_vblank_on and drm_crtc_vblank_off respectively. That will gate vblank enables and

[PATCH 3/8] drm/msm: dpu: Remove vblank_callback from encoder

2018-11-13 Thread Sean Paul
From: Sean Paul The indirection of registering a callback and opaque pointer isn't real useful when there's only one callsite. So instead of having the vblank_cb registration, just give encoder a crtc and let it directly call the vblank handler. In a later patch, we'll make use of this further.

Re: [PATCH xf86-video-intel v8 2/2] sna: Added AYUV format support for textured and sprite video adapters.

2018-11-13 Thread Chris Wilson
Quoting Ville Syrjälä (2018-11-13 19:13:40) > On Tue, Nov 13, 2018 at 06:49:38PM +, Chris Wilson wrote: > > Quoting Stanislav Lisovskiy (2018-11-13 07:45:02) > > > @@ -408,6 +424,9 @@ void sna_video_textured_setup(struct sna *sna, > > > ScreenPtr screen) > > > } else if (sna->kgem.gen

[Bug 200695] Blank screen on RX 580 with amdgpu.dc=1 enabled (no displays detected)

2018-11-13 Thread bugzilla-daemon
https://bugzilla.kernel.org/show_bug.cgi?id=200695 Claude Heiland-Allen (cla...@mathr.co.uk) changed: What|Removed |Added Kernel Version|4.17.19, 4.18.0-rc7,|4.17.19,

Re: [Intel-gfx] [PATCH 1/2] drm/edid: Add and export function to parse manufacturer id

2018-11-13 Thread Jani Nikula
On Thu, 08 Nov 2018, Daniel Vetter wrote: > On Thu, Nov 08, 2018 at 08:42:52PM +, Souza, Jose wrote: >> On Thu, 2018-11-08 at 09:31 +0100, Daniel Vetter wrote: >> > On Wed, Nov 07, 2018 at 04:23:52PM -0800, José Roberto de Souza >> > wrote: >> > > This function will be helpful to drivers that

Re: [PATCH 0/2] Docs/EDID: Fixed and improved EDID documentation

2018-11-13 Thread Jani Nikula
On Tue, 06 Nov 2018, Jonathan Corbet wrote: > On Mon, 5 Nov 2018 09:48:33 +0100 > Christoph Niedermaier wrote: > >> A problem was found when EDID data sets for displays other >> than the provided samples were generated. The patch series has >> no effect on the provided samples that still match

[Bug 108330] WarThunder game performance killed after Ryzen optimisations

2018-11-13 Thread bugzilla-daemon
https://bugs.freedesktop.org/show_bug.cgi?id=108330 --- Comment #6 from aceman --- So strangely the patch didn't work, but updating mesa today (presents itself as 19.0.0), containing the commit https://cgit.freedesktop.org/mesa/mesa/commit/?id=e0c7114eb3c19d4c2653f661698a6baa3bc9bedf FIXES the

Re: [PATCH xf86-video-intel v8 2/2] sna: Added AYUV format support for textured and sprite video adapters.

2018-11-13 Thread Ville Syrjälä
On Tue, Nov 13, 2018 at 06:49:38PM +, Chris Wilson wrote: > Quoting Stanislav Lisovskiy (2018-11-13 07:45:02) > > @@ -408,6 +424,9 @@ void sna_video_textured_setup(struct sna *sna, > > ScreenPtr screen) > > } else if (sna->kgem.gen < 040) { > > adaptor->nImages =

Re: Sound and the TDA998x binding

2018-11-13 Thread Russell King - ARM Linux
On Tue, Nov 13, 2018 at 06:12:37PM +, Peter Rosin wrote: > On 2018-11-13 18:24, Russell King - ARM Linux wrote: > > On Tue, Nov 13, 2018 at 01:28:40PM +, Peter Rosin wrote: > >> Hi! > >> > >> I'm wondering about some programming details regarding the TDA998x > >> driver... > >> > >> The

Re: [PATCH xf86-video-intel v8 2/2] sna: Added AYUV format support for textured and sprite video adapters.

2018-11-13 Thread Chris Wilson
Quoting Stanislav Lisovskiy (2018-11-13 07:45:02) > @@ -408,6 +424,9 @@ void sna_video_textured_setup(struct sna *sna, ScreenPtr > screen) > } else if (sna->kgem.gen < 040) { > adaptor->nImages = ARRAY_SIZE(gen3_Images); > adaptor->pImages = (XvImageRec

Re: Sound and the TDA998x binding

2018-11-13 Thread Russell King - ARM Linux
On Tue, Nov 13, 2018 at 01:28:40PM +, Peter Rosin wrote: > Hi! > > I'm wondering about some programming details regarding the TDA998x > driver... > > The bindings documentation [1] state that one should fill in the > desired register content of the AP_ENA register. However, I cannot > find

[Bug 107978] [amdgpu] Switching to tty fails with DisplayPort 1.2 monitor going to sleep (REG_WAIT timeout / dce110_stream_encoder_dp_blank)

2018-11-13 Thread bugzilla-daemon
https://bugs.freedesktop.org/show_bug.cgi?id=107978 --- Comment #16 from Daniel Exner --- I own a Dell U3415W also connected via DisplayPort and I have the same issue. Worked like a charm in the past. -- You are receiving this mail because: You are the assignee for the

Re: [PATCH v2] Fix the possible watermark miswriting for skl+

2018-11-13 Thread Chris Wilson
Quoting Stanislav Lisovskiy (2018-11-13 14:31:38) > Currently whenever we attempt to recalculate > watermarks, we assign dirty_pipes to zero, > then compare current wm results to the recalculated > one and if they changed we set correspondent dirty_pipes > bit again. > This can lead to situation,

[Bug 108591] [CI][DRMTIP] igt@gem_tiled_fence_blits@normal - fail - Failed assertion: linear[i] == start_val

2018-11-13 Thread bugzilla-daemon
https://bugs.freedesktop.org/show_bug.cgi?id=108591 --- Comment #9 from Chris Wilson --- (In reply to Chris Wilson from comment #8) > Fwiw, my slow pIIIm i915gm doesn't seem to suffer the same fate. Except I should check pnv for my closest equiv to blb. -- You are receiving this mail because:

[Bug 108591] [CI][DRMTIP] igt@gem_tiled_fence_blits@normal - fail - Failed assertion: linear[i] == start_val

2018-11-13 Thread bugzilla-daemon
https://bugs.freedesktop.org/show_bug.cgi?id=108591 --- Comment #8 from Chris Wilson --- Probably should have mentioned the gpu hang, as that makes it a completely different bug. <7> [99.123649] hangcheck rcs0 <7> [99.123667] hangcheck \x09current seqno 1ec, last 1fb, hangcheck 1ec [5952 ms]

[PATCH v2 13/12] drm/msm: dpu: Don't drop locks in crtc_vblank_enable

2018-11-13 Thread Sean Paul
From: Sean Paul Now that runtime resume is handled in encoder, we don't need to worry about crtc_lock recursion when calling pm_runtime_(get|put). So drop the lock drops in _dpu_crtc_vblank_enable_no_lock(). Changes in v2: - Added to patch series Signed-off-by: Sean Paul ---

[Bug 108591] [CI][DRMTIP] igt@gem_tiled_fence_blits@normal - fail - Failed assertion: linear[i] == start_val

2018-11-13 Thread bugzilla-daemon
https://bugs.freedesktop.org/show_bug.cgi?id=108591 Martin Peres changed: What|Removed |Added Status|RESOLVED|REOPENED Resolution|FIXED

Re: [Freedreno] [PATCH v2] drm/msm/dpu: Correct dpu destroy and disable order

2018-11-13 Thread Sean Paul
On Fri, Nov 09, 2018 at 11:37:17AM +0530, Rajendra Nayak wrote: > > On 11/2/2018 6:19 PM, Jayant Shekhar wrote: > > In case of msm drm bind failure, dpu_mdss_destroy is triggered. > > In this function, resources are freed and pm runtime disable is > > called, which triggers dpu_mdss_disable. Now

[PATCH v2 04/12] drm/msm: dpu: Don't use power_event for vbif_init_memtypes

2018-11-13 Thread Sean Paul
From: Sean Paul power_events are only used for pm_runtime, and that's all handled in dpu_kms. So just call vbif_init_memtypes at the correct times. Changes in v2: - Removed obsolete comment (Jeykumar) Cc: Jeykumar Sankaran Signed-off-by: Sean Paul --- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

Re: [PATCH 12/12] drm/msm: dpu: Move crtc runtime resume to encoder

2018-11-13 Thread Sean Paul
On Mon, Nov 12, 2018 at 05:47:58PM -0800, Jeykumar Sankaran wrote: > On 2018-11-12 11:42, Sean Paul wrote: > > From: Sean Paul > > > > The crtc runtime resume doesn't actually operate on the crtc, but rather > > its encoders. The problem with this is that we need to inspect the crtc > > state to

Re: [PATCH 11/12] drm/msm: dpu: Add ->enabled to dpu_encoder_virt

2018-11-13 Thread Sean Paul
On Mon, Nov 12, 2018 at 05:43:17PM -0800, Jeykumar Sankaran wrote: > On 2018-11-12 11:42, Sean Paul wrote: > > From: Sean Paul > > > > Add a bool to dpu_encoder_virt to track whether the encoder is enabled > > or not. Repurpose the enc_lock mutex to ensure that it is consistent > > with the hw

Re: [PATCH 05/12] drm/msm: dpu: Handle crtc pm_runtime_resume() directly

2018-11-13 Thread Sean Paul
On Mon, Nov 12, 2018 at 05:20:28PM -0800, Jeykumar Sankaran wrote: > On 2018-11-12 11:42, Sean Paul wrote: > > From: Sean Paul > > > > Instead of registering through dpu_power_handle just to get a call on > > runtime_resume, call the crtc function directly. > > > > Signed-off-by: Sean Paul > >

[Bug 108729] [Kaveri CIK 7400K] [regression, works on radeon] [drm:vce_v2_0_start [amdgpu]] *ERROR* VCE not responding, trying to reset the ECPU!!!

2018-11-13 Thread bugzilla-daemon
https://bugs.freedesktop.org/show_bug.cgi?id=108729 --- Comment #2 from Alex Deucher --- Please attach your full dmesg output and xorg log if using X. -- You are receiving this mail because: You are the assignee for the bug.___ dri-devel mailing list

Re: [Intel-gfx] [PATCH v1] Fix the possible watermark miswriting

2018-11-13 Thread Ville Syrjälä
On Tue, Nov 13, 2018 at 04:27:28PM +0200, Stanislav Lisovskiy wrote: > Currently whenever we attempt to recalculate > watermarks, we assign dirty_pipes to zero, > then compare current wm results to the recalculated > one and if they changed we set correspondent dirty_pipes > bit again. > This can

[Bug 108729] [Kaveri CIK 7400K] [regression, works on radeon] [drm:vce_v2_0_start [amdgpu]] *ERROR* VCE not responding, trying to reset the ECPU!!!

2018-11-13 Thread bugzilla-daemon
https://bugs.freedesktop.org/show_bug.cgi?id=108729 Vedran Miletić changed: What|Removed |Added Keywords||regression Summary|[Kaveri

[PATCH v2] Fix the possible watermark miswriting for skl+

2018-11-13 Thread Stanislav Lisovskiy
Currently whenever we attempt to recalculate watermarks, we assign dirty_pipes to zero, then compare current wm results to the recalculated one and if they changed we set correspondent dirty_pipes bit again. This can lead to situation, when we are clearing dirty_pipes, same wm results twice in a

[Bug 108729] [Kaveri CIK 7400K] [drm:vce_v2_0_start [amdgpu]] *ERROR* VCE not responding, trying to reset the ECPU!!!

2018-11-13 Thread bugzilla-daemon
https://bugs.freedesktop.org/show_bug.cgi?id=108729 Bug ID: 108729 Summary: [Kaveri CIK 7400K] [drm:vce_v2_0_start [amdgpu]] *ERROR* VCE not responding, trying to reset the ECPU!!! Product: DRI Version: DRI git

[PATCH v1] Fix the possible watermark miswriting

2018-11-13 Thread Stanislav Lisovskiy
Currently whenever we attempt to recalculate watermarks, we assign dirty_pipes to zero, then compare current wm results to the recalculated one and if they changed we set correspondent dirty_pipes bit again. This can lead to situation, when we same clearing dirty_pipes, same wm results twice and

Re: [PATCH 0/3] drm/meson: Add support for Overlay and OSD Plane scaling

2018-11-13 Thread Neil Armstrong
On 06/11/2018 10:39, Neil Armstrong wrote: > This serie adds support for : > - Overlay Plane blended with the primary plane, we can describe as "behind" > - Primary Plane up-scaling up to 5x factor to support the OSD plane being > upscaled from 1920x1080 when the display mode is set as

Re: [PATCH 0/2] drm/meson: Allow using optional canvas provider

2018-11-13 Thread Neil Armstrong
On 05/11/2018 15:02, Maxime Jourdan wrote: > Hi Neil, > > On Mon, Nov 5, 2018 at 1:51 PM Neil Armstrong wrote: >> >> Hi Maxime, >> >> On 05/11/2018 11:45, Maxime Jourdan wrote: >>> The meson DRM driver currently uses constant, static canvas indexes. >>> >>> This is not optimal and could conflict

Re: [PATCH] drm/meson: venc: dmt mode must use encp

2018-11-13 Thread Neil Armstrong
On 13/11/2018 09:35, Neil Armstrong wrote: > On 12/11/2018 19:41, Jorge Ramirez-Ortiz wrote: >> From: Jorge Ramirez-Ortiz >> >> The video mode for DMT is only populated to support encp. >> >> Signed-off-by: Jorge Ramirez-Ortiz >> --- >> drivers/gpu/drm/meson/meson_venc.c | 15 --- >>

Re: [PATCH v4 03/26] clk: sunxi-ng: Add check for maximum rate to NKM PLLs

2018-11-13 Thread Maxime Ripard
On Tue, Nov 13, 2018 at 04:46:10PM +0530, Jagan Teki wrote: > Some NKM PLLs, frequency can be set above PLL working range. > > Add a constraint for maximum supported rate. This way, drivers can > specify which is maximum allowed rate for PLL. > > Signed-off-by: Jagan Teki > Acked-by: Stephen

Re: [PATCH v2 1/2] dt-bindings: gpu: mali-utgard: Add compatible for A64 Mali

2018-11-13 Thread Maxime Ripard
On Tue, Nov 13, 2018 at 05:30:53PM +0530, Jagan Teki wrote: > Allwinner A64 has Mali-400MP2, so document the relevant compatible > as "allwinner,sun50i-a64-mali" > > Signed-off-by: Jagan Teki > --- > Changes for v2: > - New patch, separated from previous version patch. > >

Re: [PATCH v2 2/2] arm64: dts: allwinner: a64: Add device node for Mali-400 GPU

2018-11-13 Thread Maxime Ripard
On Tue, Nov 13, 2018 at 05:30:54PM +0530, Jagan Teki wrote: > Add support for Allwinner A64 has Mali-400MP2. > > All interrupt lines are mentioned in the manual so used the same. > Used 408MHz as assigned clock rate used by BSP, so used the same as > well. You're not using that frequency

Re: [PATCH v4 01/26] clk: sunxi-ng: a64: Fix gate bit of DSI DPHY

2018-11-13 Thread Maxime Ripard
On Tue, Nov 13, 2018 at 04:46:08PM +0530, Jagan Teki wrote: > DSI DPHY gate bit on MIPI DSI clock register is bit 15 > not bit 30. > > Signed-off-by: Jagan Teki > Acked-by: Stephen Boyd Applied, thanks! Maxime -- Maxime Ripard, Bootlin Embedded Linux and Kernel engineering

Re: [PATCH v6 4/4] arm64: defconfig: Enable PWM_SUN4I

2018-11-13 Thread Maxime Ripard
On Tue, Nov 13, 2018 at 05:45:35PM +0530, Jagan Teki wrote: > Allwinner PWM support need for ARM64 Allwinner SoC's > which used pwms, builds it as module. > > Signed-off-by: Jagan Teki Applied all 4 patches, thanks! Maxime -- Maxime Ripard, Bootlin Embedded Linux and Kernel engineering

[PATCH] dt-bindings: display: add binding for Innolux ee101ia-01d panel

2018-11-13 Thread Heiko Stuebner
From: Heiko Stuebner This is a panel handled through the generic lvds-panel binding, so only needs its additional compatible specified. Signed-off-by: Heiko Stuebner --- .../bindings/display/panel/innolux,ee101ia-01d.txt | 7 +++ 1 file changed, 7 insertions(+) create mode 100644

Re: [PATCH v4 26/26] arm64: dts: allwinner: a64-amarula-relic: Enable Techstar TS8550B MIPI-DSI panel

2018-11-13 Thread Andre Przywara
On Tue, 13 Nov 2018 16:46:33 +0530 Jagan Teki wrote: Hi, I couldn't find a schematic for this board, but some things in here look inconsistent: > Amarula A64-Relic board by default bound with Techstar TS8550B > MIPI-DSI panel, add support for it. > > DSI panel connected via board DSI port

Re: [PATCH v4 25/26] [DO NOT MERGE] arm64: dts: allwinner: bananapi-m64: Bananapi S070WV20-CT16 DSI panel

2018-11-13 Thread Andre Przywara
On Tue, 13 Nov 2018 16:46:32 +0530 Jagan Teki wrote: Hi, > This patch add support for Bananapi S070WV20-CT16 DSI panel to > BPI-M64 board. > > DSI panel connected via board DSI port with, > - DC1SW as AVDD supply Are you sure of that? I don't see anything in the schematic to support this. The

Re: Performance regression in ast drm driver

2018-11-13 Thread Thomas Zimmermann
Hi Am 13.11.18 um 13:08 schrieb Jean Delvare: > Hi Thomas, > > On Tue, 13 Nov 2018 10:23:45 +0100, Thomas Zimmermann wrote: >> ast doesn't remove the vesafb's framebuffer before attaching to the >> device. I have a patch at [1]. If you have a way of testing it, I'd >> appreciate. >> >> [1]

Re: [PATCH -next] drm/sti: remove set but not used variable 'priv'

2018-11-13 Thread Benjamin Gaignard
Le sam. 10 nov. 2018 à 03:48, YueHaibing a écrit : > > Fixes gcc '-Wunused-but-set-variable' warning: > > drivers/gpu/drm/sti/sti_crtc.c: In function 'sti_crtc_vblank_cb': > drivers/gpu/drm/sti/sti_crtc.c:255:22: warning: > variable 'priv' set but not used [-Wunused-but-set-variable] > > It

Re: [PATCH 3/4] drm/v3d: Clean up the reservation object setup.

2018-11-13 Thread Boris Brezillon
On Thu, 8 Nov 2018 08:16:53 -0800 Eric Anholt wrote: > The extra to_v3d_bo() calls came from copying this from the vc4 > driver, which stored the cma gem object in the structs. > > Signed-off-by: Eric Anholt Reviewed-by: Boris Brezillon > --- > drivers/gpu/drm/v3d/v3d_gem.c | 32

Re: [PATCH 1/4] drm/v3d: Fix whitespace inconsistency in the header.

2018-11-13 Thread Boris Brezillon
On Thu, 8 Nov 2018 08:16:51 -0800 Eric Anholt wrote: Maybe you could add a short description here to avoid having an empty commit message. > Signed-off-by: Eric Anholt Reviewed-by: Boris Brezillon > --- > include/uapi/drm/v3d_drm.h | 4 ++-- > 1 file changed, 2 insertions(+), 2

Re: [PATCH 2/4] drm/v3d: Update a comment about what uses v3d_job_dependency().

2018-11-13 Thread Boris Brezillon
On Thu, 8 Nov 2018 08:16:52 -0800 Eric Anholt wrote: > I merged bin and render's paths in a late refactoring. > > Signed-off-by: Eric Anholt Reviewed-by: Boris Brezillon > --- > drivers/gpu/drm/v3d/v3d_sched.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git

[PATCH 1/2] drm/vc4: Fix NULL pointer dereference in the async update path

2018-11-13 Thread Boris Brezillon
vc4_plane_atomic_async_update() calls vc4_plane_atomic_check() which in turn calls vc4_plane_setup_clipping_and_scaling(), and since commit 58a6a36fe8e0 ("drm/vc4: Use drm_atomic_helper_check_plane_state() to simplify the logic"), this function accesses plane_state->state which will be NULL when

[PATCH 2/2] drm/vc4: Set ->legacy_cursor_update to false when doing non-async updates

2018-11-13 Thread Boris Brezillon
drm_atomic_helper_setup_commit() auto-completes commit->flip_done when state->legacy_cursor_update is true, but we now for sure that we want a sync update when we call drm_atomic_helper_setup_commit() from vc4_atomic_commit(). Explicitly set state->legacy_cursor_update to false to prevent this

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