On Tue, 2023-05-02 at 11:32 +0200, Javier Martinez Canillas wrote:
> !! External Email
>
> Daniel Vetter writes:
>
> > On Mon, Jul 11, 2022 at 11:32:39PM -0400, Zack Rusin wrote:
> > > From: Zack Rusin
> > >
> > > Cursor planes on virtualized drivers have special meaning and require
> > >
>
> >
> >> > the GROUP until after the FIRMWARE, so this can't work, as it already
> >> > will have included all the ones below, hence why I bracketed top and
> >> > bottom with a group.
> >>
> >> well... that is something that can be adapted easily by using a 2 pass
> >> approach, filtering out
Currently, word count is calculated using slice_count. This is incorrect
as downstream uses slice per packet, which is different from
slice_count.
Slice count represents the number of soft slices per interface, and its
value will not always match that of slice per packet. For example, it is
This is a series of changes for DSI to enable support for DSC v1.2.
This includes:
1) Dividing the pclk_rate by the compression ratio when DSC is enabled
2) Fixing the word count calculation for DSC
3) Setting the DATA_COMPRESS bit when DSC is enabled
With these changes (and the dependency
Add a dpu_hw_intf op to enable data compression.
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 4
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 7 +++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 2 ++
3 files changed, 13
Add data_compress feature to DPU HW catalog.
In DPU 7.x and later, there is a DATA_COMPRESS register that must be set
within the DPU INTF block for DSC to work.
As core_rev (and related macros) was removed from the dpu_kms struct, the
most straightforward way to indicate the presence of this
Divide the pclk rate by the compression ratio when DSC is enabled
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
b/drivers/gpu/drm/msm/dsi/dsi_host.c
On 5/2/2023 4:58 PM, Dmitry Baryshkov wrote:
On 03/05/2023 02:57, Abhinav Kumar wrote:
On 4/30/2023 4:57 PM, Dmitry Baryshkov wrote:
There is little sense to get intf index just to call dpu_rm_get_intf()
on it. Move dpu_rm_get_intf() call to dpu_encoder_get_intf() function.
On 01/05/2023 02:57, Dmitry Baryshkov wrote:
The atomic_mode_set() callback only sets the phys_enc's IRQ data. As the
INTF and WB are statically allocated to each encoder/phys_enc, drop the
atomic_mode_set callback and set the IRQs during encoder init.
Signed-off-by: Dmitry Baryshkov
Please
On 03/05/2023 02:58, Abhinav Kumar wrote:
On 5/2/2023 4:54 PM, Dmitry Baryshkov wrote:
On 03/05/2023 02:51, Abhinav Kumar wrote:
On 4/30/2023 4:57 PM, Dmitry Baryshkov wrote:
The function dpu_encoder_get_wb() returns controller_id if the
corresponding WB is present in the catalog. We can
On 03/05/2023 02:57, Abhinav Kumar wrote:
On 4/30/2023 4:57 PM, Dmitry Baryshkov wrote:
There is little sense to get intf index just to call dpu_rm_get_intf()
on it. Move dpu_rm_get_intf() call to dpu_encoder_get_intf() function.
Signed-off-by: Dmitry Baryshkov
---
On 5/2/2023 4:54 PM, Dmitry Baryshkov wrote:
On 03/05/2023 02:51, Abhinav Kumar wrote:
On 4/30/2023 4:57 PM, Dmitry Baryshkov wrote:
The function dpu_encoder_get_wb() returns controller_id if the
corresponding WB is present in the catalog. We can inline this function
and rely on
On 4/30/2023 4:57 PM, Dmitry Baryshkov wrote:
There is little sense to get intf index just to call dpu_rm_get_intf()
on it. Move dpu_rm_get_intf() call to dpu_encoder_get_intf() function.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 20
On 03/05/2023 02:51, Abhinav Kumar wrote:
On 4/30/2023 4:57 PM, Dmitry Baryshkov wrote:
The function dpu_encoder_get_wb() returns controller_id if the
corresponding WB is present in the catalog. We can inline this function
and rely on dpu_rm_get_wb() returning NULL for indices for which the
On 03/05/2023 02:19, Abhinav Kumar wrote:
On 5/2/2023 4:15 PM, Dmitry Baryshkov wrote:
On Wed, 3 May 2023 at 02:04, Abhinav Kumar
wrote:
On 4/30/2023 4:57 PM, Dmitry Baryshkov wrote:
Remove intf_idx and wb_idx fields from struct dpu_encoder_phys and
struct dpu_enc_phys_init_params. Set
On 4/30/2023 4:57 PM, Dmitry Baryshkov wrote:
The function dpu_encoder_get_wb() returns controller_id if the
corresponding WB is present in the catalog. We can inline this function
and rely on dpu_rm_get_wb() returning NULL for indices for which the
WB is not present on the device.
On 5/2/2023 2:38 PM, Dmitry Baryshkov wrote:
On 03/05/2023 00:03, Kuogee Hsieh wrote:
Add support for DSC 1.2 by providing the necessary hooks to program
the DPU DSC 1.2 encoder.
Changes in v3:
-- fixed kernel test rebot report that "__iomem *off" is declared but
not
used at
From: John Harrison
If the DEBUG_GEM config option is set then escalate the 'unexpected
firmware version' message from a notice to an error. This will ensure
that the CI system treats such occurences as a failure and logs a bug
about it (or fails the pre-merge testing).
Signed-off-by: John
From: John Harrison
It was noticed that duplicate entries in the firmware table could cause
an infinite loop in the firmware loading code if that entry failed to
load. Duplicate entries are a bug anyway and so should never happen.
Ensure they don't by tweaking the table validation code to reject
From: John Harrison
The validation of the firmware table was being done inside the code
for scanning the table for the next available firmware blob. Which is
unnecessary. So pull it out into a separate function that is only
called once per blob type at init time.
Also, drop the CONFIG_SELFTEST
From: John Harrison
Explain another potential firmware failure mode and early exit the
long wait if hit.
Signed-off-by: John Harrison
Reviewed-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gt/uc/abi/guc_errors_abi.h | 1 +
drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 6 ++
2
From: John Harrison
If the GuC load is taking an excessively long time, the wait loop
currently prints the GT frequency. Extend that to include the GuC
status as well so we can see if the GuC is actually making progress or
not.
Signed-off-by: John Harrison
Reviewed-by: Daniele Ceraolo Spurio
From: John Harrison
When reduced version firmware files were added (matching major
component being the only strict requirement), the minor version was
still tracked and a notification reported if it was older. However,
the patch version should really be tracked as well for the same
reasons. The
From: John Harrison
Enhance the firmware table verification code to catch more potential
errors and to generally improve the code itself.
Track patch level version even on reduced version files to allow user
notification of missing bug fixes.
Detect another immediate failure case when loading
On 5/2/2023 4:15 PM, Dmitry Baryshkov wrote:
On Wed, 3 May 2023 at 02:04, Abhinav Kumar wrote:
On 4/30/2023 4:57 PM, Dmitry Baryshkov wrote:
Remove intf_idx and wb_idx fields from struct dpu_encoder_phys and
struct dpu_enc_phys_init_params. Set the hw_intf and hw_wb directly and
use
On Wed, 3 May 2023 at 02:04, Abhinav Kumar wrote:
>
>
>
> On 4/30/2023 4:57 PM, Dmitry Baryshkov wrote:
> > Remove intf_idx and wb_idx fields from struct dpu_encoder_phys and
> > struct dpu_enc_phys_init_params. Set the hw_intf and hw_wb directly and
> > use them to get the instance index.
> >
>
On Tue, May 02, 2023 at 01:21:43PM -0400, Rodrigo Vivi wrote:
> On Tue, May 02, 2023 at 03:40:50PM +, Matthew Brost wrote:
> > On Wed, Apr 26, 2023 at 04:57:02PM -0400, Rodrigo Vivi wrote:
> > > Unfortunately devcoredump infrastructure does not provide and
> > > interface for us to force the
On 4/30/2023 4:57 PM, Dmitry Baryshkov wrote:
Remove intf_idx and wb_idx fields from struct dpu_encoder_phys and
struct dpu_enc_phys_init_params. Set the hw_intf and hw_wb directly and
use them to get the instance index.
Signed-off-by: Dmitry Baryshkov
---
From whatever I can see, this
On 03/05/2023 00:02, Kuogee Hsieh wrote:
At legacy chipsets, it required DPU_PINGPONG_DSC bit be set to indicate
pingpong ops functions are required to complete DSC data path setup if
this chipset has DSC hardware block presented. This patch add
DPU_PINGPONG_DSC bit to both PP_BLK and PP_BLK_TE
On Tue, May 02, 2023 at 11:11:58AM -0700, Lucas De Marchi wrote:
> Based on the above and my previous reply, I think we should have
> something more explicit about the order rather than relying on the
> toolchain behavior.
You can open code ELF sections and provide SORT() but you can also use
On 03/05/2023 00:03, Kuogee Hsieh wrote:
From: Abhinav Kumar
Add DSC 1.2 hardware blocks to the catalog with necessary sub-block and
feature flag information. Each display compression engine (DCE) contains
dual hard slice DSC encoders so both share same base address but with
its own different
On 03/05/2023 00:03, Kuogee Hsieh wrote:
Add support for DSC 1.2 by providing the necessary hooks to program
the DPU DSC 1.2 encoder.
Changes in v3:
-- fixed kernel test rebot report that "__iomem *off" is declared but not
used at dpu_hw_dsc_config_1_2()
-- unrolling thresh loops
On 03/05/2023 00:33, Abhinav Kumar wrote:
On 4/30/2023 4:57 PM, Dmitry Baryshkov wrote:
Move common DPU physical encoder initialization code to the new function
dpu_encoder_phys_init().
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 31
On 4/30/2023 4:57 PM, Dmitry Baryshkov wrote:
Move common DPU physical encoder initialization code to the new function
dpu_encoder_phys_init().
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 31 +--
On Tue, May 2, 2023 at 12:44 PM Simon Horman wrote:
>
> On Wed, Apr 26, 2023 at 11:54:29AM -0700, Justin Chen wrote:
> > Add support for the Broadcom ASP 2.0 Ethernet controller which is first
> > introduced with 72165. This controller features two distinct Ethernet
> > ports that can be
On 03/05/2023 00:02, Kuogee Hsieh wrote:
During DSC setup, the crossbar mux need to be programmed to engage
DSC to specified PINGPONG. Hence during tear down, the crossbar mux
need to be reset to disengage DSC from PINGPONG. This patch add
PINGPONG_NONE to serve as disable to reset crossbar mux.
On 03/05/2023 00:02, Kuogee Hsieh wrote:
Legacy DPU requires PP block to be involved during DSC setting up.
This patch adds DDPU_PINGPONG_DSC feature bit to indicate that both
DPU_PINGPONG_DSC
dpu_hw_pp_setup_dsc() and dpu_hw_pp_dsc_enable() pingpong ops
functions are required to complete
On 03/05/2023 00:02, Kuogee Hsieh wrote:
From: Abhinav Kumar
There are some platforms has DSC blocks but it is not declared at catalog.
For completeness, this patch adds DSC blocks for platforms which missed
them.
Signed-off-by: Abhinav Kumar
---
On 03/05/2023 00:02, Kuogee Hsieh wrote:
This series adds the DPU side changes to support DSC 1.2 encoder. This
was validated with both DSI DSC 1.2 panel and DP DSC 1.2 monitor.
The DSI and DP parts will be pushed later on top of this change.
This seriel is rebase on [1], [2] and catalog fixes
On 02/05/2023 23:59, Abhinav Kumar wrote:
On 5/2/2023 1:54 PM, Dmitry Baryshkov wrote:
On Tue, 2 May 2023 at 23:45, Abhinav Kumar
wrote:
On 4/30/2023 4:57 PM, Dmitry Baryshkov wrote:
There is no need to clean up debugfs manually, it will be done by the
DRM core on device deregistration.
Current DSC flush update is piggyback inside dpu_hw_ctl_intf_cfg_v1().
This patch separates DSC flush away from dpu_hw_ctl_intf_cfg_v1() by
adding dpu_hw_ctl_update_pending_flush_dsc_v1() to handle both per
DSC engine and DSC flush bits at same time to make it consistent with
the location of flush
From: Abhinav Kumar
Add DSC 1.2 hardware blocks to the catalog with necessary sub-block and
feature flag information. Each display compression engine (DCE) contains
dual hard slice DSC encoders so both share same base address but with
its own different sub block address.
Signed-off-by: Abhinav
Add support for DSC 1.2 by providing the necessary hooks to program
the DPU DSC 1.2 encoder.
Changes in v3:
-- fixed kernel test rebot report that "__iomem *off" is declared but not
used at dpu_hw_dsc_config_1_2()
-- unrolling thresh loops
Reported-by: kernel test robot
Signed-off-by: Kuogee
From: Abhinav Kumar
There are some platforms has DSC blocks but it is not declared at catalog.
For completeness, this patch adds DSC blocks for platforms which missed
them.
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 7 +++
During DSC setup, the crossbar mux need to be programmed to engage
DSC to specified PINGPONG. Hence during tear down, the crossbar mux
need to be reset to disengage DSC from PINGPONG. This patch add
PINGPONG_NONE to serve as disable to reset crossbar mux.
Signed-off-by: Kuogee Hsieh
---
At legacy chipsets, it required DPU_PINGPONG_DSC bit be set to indicate
pingpong ops functions are required to complete DSC data path setup if
this chipset has DSC hardware block presented. This patch add
DPU_PINGPONG_DSC bit to both PP_BLK and PP_BLK_TE marcos if it has DSC
hardware block
Legacy DPU requires PP block to be involved during DSC setting up.
This patch adds DDPU_PINGPONG_DSC feature bit to indicate that both
dpu_hw_pp_setup_dsc() and dpu_hw_pp_dsc_enable() pingpong ops
functions are required to complete DSC data path set up and start
DSC engine.
Reported-by : Marijn
This series adds the DPU side changes to support DSC 1.2 encoder. This
was validated with both DSI DSC 1.2 panel and DP DSC 1.2 monitor.
The DSI and DP parts will be pushed later on top of this change.
This seriel is rebase on [1], [2] and catalog fixes from [3].
[1]:
On 5/2/2023 1:54 PM, Dmitry Baryshkov wrote:
On Tue, 2 May 2023 at 23:45, Abhinav Kumar wrote:
On 4/30/2023 4:57 PM, Dmitry Baryshkov wrote:
There is no need to clean up debugfs manually, it will be done by the
DRM core on device deregistration.
Signed-off-by: Dmitry Baryshkov
---
On Tue, 2 May 2023 at 23:45, Abhinav Kumar wrote:
>
>
>
> On 4/30/2023 4:57 PM, Dmitry Baryshkov wrote:
> > There is no need to clean up debugfs manually, it will be done by the
> > DRM core on device deregistration.
> >
> > Signed-off-by: Dmitry Baryshkov
> > ---
>
> There are two reasons to
On 4/30/2023 4:57 PM, Dmitry Baryshkov wrote:
There is no need to clean up debugfs manually, it will be done by the
DRM core on device deregistration.
Signed-off-by: Dmitry Baryshkov
---
There are two reasons to have the debugfs removed in the early_unregister:
1) Today, registration
Hi,
a kind reminder on this patch, would be fantastic if anyone from
the x86 maintainers cha give it a look.
The patch has been tested thoroughly and even if it's marked as
an RFC in my opinion it can be already considered for a proper
review.
Thanks,
Andi
On Mon, Apr 24, 2023 at 02:35:24PM
On Tue, May 02, 2023 at 02:06:55PM -0400, Rodrigo Vivi wrote:
> On Tue, May 02, 2023 at 07:57:02AM +, Matthew Brost wrote:
> > On Thu, Apr 27, 2023 at 10:28:13AM +0200, Thomas Hellström wrote:
> > >
> > > On 4/26/23 22:57, Rodrigo Vivi wrote:
> > > > The goal is to use devcoredump
On 5/1/2023 2:27 PM, Dmitry Baryshkov wrote:
On 02/05/2023 00:22, Abhinav Kumar wrote:
On 5/1/2023 1:45 PM, Dmitry Baryshkov wrote:
On 01/05/2023 22:58, Abhinav Kumar wrote:
On 4/30/2023 4:57 PM, Dmitry Baryshkov wrote:
There is no reason to split the dpu_encoder interface into
Le 26/04/2023 à 20:54, Justin Chen a écrit :
Add support for the Broadcom ASP 2.0 Ethernet controller which is first
introduced with 72165. This controller features two distinct Ethernet
ports that can be independently operated.
This patch supports:
- Wake-on-LAN using magic packets
- basic
Hi Thomas.
On Tue, May 02, 2023 at 03:02:23PM +0200, Thomas Zimmermann wrote:
> Update the names of the fb_mem*() helpers to be consistent with their
> regular counterparts. Hence, fb_memset() now becomes fb_memset_io(),
> fb_memcpy_fromfb() now becomes fb_memcpy_fromio() and fb_memcpy_tofb()
>
On Tue, May 2, 2023, at 15:02, Thomas Zimmermann wrote:
> Implement framebuffer I/O helpers, such as fb_read*() and fb_write*(),
> in the architecture's header file or the generic one.
>
> The common case has been the use of regular I/O functions, such as
> __raw_readb() or memset_io(). A few
Hi Thomas,
On Tue, May 02, 2023 at 03:02:22PM +0200, Thomas Zimmermann wrote:
> Implement framebuffer I/O helpers, such as fb_read*() and fb_write*(),
> in the architecture's header file or the generic one.
In reality they are now all implemented in the generic one.
>
> The common case has
Hi Thomas,
On Tue, May 02, 2023 at 03:02:21PM +0200, Thomas Zimmermann wrote:
> Fbdev's main header file, , includes to get
> declarations for I/O helper functions. From these declarations, it
> later defines framebuffer I/O helpers, such as fb_{read,write}[bwlq]()
> or fb_memset().
>
> The
On Wed, Apr 26, 2023 at 11:54:29AM -0700, Justin Chen wrote:
> Add support for the Broadcom ASP 2.0 Ethernet controller which is first
> introduced with 72165. This controller features two distinct Ethernet
> ports that can be independently operated.
>
> This patch supports:
>
> - Wake-on-LAN
On Tue, May 2, 2023 at 11:22 AM Timur Kristóf wrote:
>
> On Tue, 2023-05-02 at 09:45 -0400, Alex Deucher wrote:
> > On Tue, May 2, 2023 at 9:35 AM Timur Kristóf
> > wrote:
> > >
> > > Hi,
> > >
> > > On Tue, 2023-05-02 at 13:14 +0200, Christian König wrote:
> > > > >
> > > > > Christian König
On Tue, May 2, 2023 at 3:35 AM Marek Szyprowski
wrote:
>
> On 02.05.2023 03:07, Adam Ford wrote:
> > This series fixes the blanking pack size and the PMS calculation. It then
> > adds support to allows the DSIM to dynamically DPHY clocks, and support
> > non-burst mode while allowing the removal
On Mon, Apr 24, 2023 at 03:56:53PM -0700, Luis Chamberlain wrote:
On Mon, Apr 24, 2023 at 10:01:13AM -0700, Lucas De Marchi wrote:
On Mon, Apr 24, 2023 at 03:44:18PM +1000, Dave Airlie wrote:
> On Fri, 21 Apr 2023 at 05:09, Lucas De Marchi
wrote:
> >
> > On Wed, Apr 19, 2023 at 02:36:52PM
On Tue, May 02, 2023 at 07:57:02AM +, Matthew Brost wrote:
> On Thu, Apr 27, 2023 at 10:28:13AM +0200, Thomas Hellström wrote:
> >
> > On 4/26/23 22:57, Rodrigo Vivi wrote:
> > > The goal is to use devcoredump infrastructure to report error states
> > > captured at the crash time.
> > >
> >
On Tue, May 02, 2023 at 10:55:14AM +0300, Jani Nikula wrote:
> On Wed, 26 Apr 2023, Rodrigo Vivi wrote:
> > + drm_info(>drm, "Check your
> > /sys/class/drm/card/device/devcoredump/data\n");
>
> Drive-by comment, could use %d and xe->drm.primary->index instead of
yeap, I wondered about that.
On Tue, May 02, 2023 at 03:40:50PM +, Matthew Brost wrote:
> On Wed, Apr 26, 2023 at 04:57:02PM -0400, Rodrigo Vivi wrote:
> > Unfortunately devcoredump infrastructure does not provide and
> > interface for us to force the device removal upon the pci_remove
> > time of our device.
> >
> > The
-mediatek-gamma-Adjust-mtk_drm_gamma_set_common-parameters/20230502-161758
base: git://anongit.freedesktop.org/drm/drm-misc drm-misc-next
patch link:
https://lore.kernel.org/r/20230502081650.25947-7-angelogioacchino.delregno%40collabora.com
patch subject: [PATCH 06/11] drm/mediatek: gamma: Use
As made mention of, in commit 9128e6babf10 ("drm/amdgpu: fix
amdgpu_irq_put call trace in gmc_v10_0_hw_fini") and commit c094b8923bdd
("drm/amdgpu: fix amdgpu_irq_put call trace in gmc_v11_0_hw_fini"). It
is meaningless to call amdgpu_irq_put() for gmc.ecc_irq. So, remove it
from
+Matthew who's been working on the kthread -> wq transition.
On Tue, 2 May 2023 13:36:07 +0200
Christian König wrote:
> Hi Boris,
>
> Am 02.05.23 um 13:19 schrieb Boris Brezillon:
> > Hello Christian, Alex,
> >
> > As part of our transition to drm_sched for the powervr GPU driver, we
> >
Hi Sam
Am 30.04.23 um 20:14 schrieb Sam Ravnborg:
Hi Thomas,
On Fri, Apr 28, 2023 at 02:24:51PM +0200, Thomas Zimmermann wrote:
Move the existing I/O read and write code for I/O memory into
the new helpers fb_cfb_read() and fb_cfb_write(). Make them the
You may want to update the changelog
The GSC uC needs to communicate with the CSME to perform certain
operations. Since the GSC can't perform this communication directly
on platforms where it is integrated in GT, i915 needs to transfer the
messages from GSC to CSME and back.
The proxy flow is as follow:
1 - i915 submits a request to
The GSC notifies us of a proxy request via the HECI2 interrupt. The
interrupt must be enabled both in the HECI layer and in our usual gt irq
programming; for the latter, the interrupt is enabled via the same enable
register as the GSC CS, but it does have its own mask register. When the
interrupt
From: Alexander Usyskin
GSC Proxy component is used for communication between the
Intel graphics driver and MEI driver.
Cc: Alan Previn
Signed-off-by: Alexander Usyskin
Signed-off-by: Tomas Winkler
Signed-off-by: Daniele Ceraolo Spurio
Acked-by: Greg Kroah-Hartman
---
v2: Improve
From: Alexander Usyskin
Add GSC proxy driver. It to allows messaging between GSC component
on Intel graphics card and CSE device.
Cc: Alan Previn
Signed-off-by: Alexander Usyskin
Signed-off-by: Tomas Winkler
Signed-off-by: Daniele Ceraolo Spurio
Acked-by: Greg Kroah-Hartman
---
v2:
On platforms where the GSC is part of GT, it needs to communicate with
CSME for some of its operations. However, there is no direct HW
communication channel, so the i915 and mei drivers must carry the
messages back and forth between the 2 units. The protocol is fully
described in the i915 patch
From: Rob Clark
Otherwise it is not always obvious if a dt or iommu change is causing us
to fall back to global pgtable.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_iommu.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/msm_iommu.c
From: Rob Clark
When the special handling of qcom,adreno-smmu was moved into
qcom_smmu_create(), it was overlooked that we didn't have all the
required entries in qcom_smmu_impl_of_match. So we stopped getting
adreno_smmu_priv on sc7180, breaking per-process pgtables.
Fixes: 30b912a03d91
On Wed, Apr 26, 2023 at 04:57:02PM -0400, Rodrigo Vivi wrote:
> Unfortunately devcoredump infrastructure does not provide and
> interface for us to force the device removal upon the pci_remove
> time of our device.
>
> The devcoredump is linked at the device level, so when in use
> it will
On Wed, Apr 26, 2023 at 04:57:13PM -0400, Rodrigo Vivi wrote:
> With this patch, we now have some parity between xe_devcoredump
> and the simple_error_capture. The only difference is that
> xe_devcoredump will only stash the 'first' hang, which is the one
> that we care most and should analyze
On Wed, Apr 26, 2023 at 04:57:11PM -0400, Rodrigo Vivi wrote:
> There are multiple kind of config prints and with the upcoming
> devcoredump there will be another layer. Let's limit the config
> to the top level functions and leave the clean-up work for the
> compilers so we don't create a
On Wed, Apr 26, 2023 at 04:57:10PM -0400, Rodrigo Vivi wrote:
> Let's continue to add our existent simple logs to devcoredump one
> by one. Any format change should come on follow-up work.
>
> Signed-off-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/xe/xe_devcoredump.c | 45
The new binaries that support the 2-step authentication have contain the
legacy-style binary, which we can use for loading the HuC via DMA. To
find out where this is located in the image, we need to parse the meu
manifest of the GSC binary. The manifest consist of a partition header
followed by
On Wed, Apr 26, 2023 at 04:57:09PM -0400, Rodrigo Vivi wrote:
> The goal is to allow for a snapshot capture to be taken at the time
> of the crash, while the print out can happen at a later time through
> the exposed devcoredump virtual device.
>
> Signed-off-by: Rodrigo Vivi
> ---
>
On Wed, Apr 26, 2023 at 04:57:08PM -0400, Rodrigo Vivi wrote:
> Let's start to move our existent logs to devcoredump one by
> one. Any format change should come on follow-up work.
>
> Signed-off-by: Rodrigo Vivi
Reviewed-by: Matthew Brost
> ---
> drivers/gpu/drm/xe/xe_devcoredump.c | 7
Now as the struct dpu_hw_pipe_qos_cfg consists of only one bool field,
drop the structure and use corresponding bool directly.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 10 +++---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 13 ++---
After removal of DPU_PLANE_QOS_VBLANK_CTRL, several fields of struct
dpu_hw_pipe_qos_cfg are fixed to false/0. Drop them from the structure
(and drop the corresponding code from the functions).
The DPU_PLANE_QOS_VBLANK_AMORTIZE flag is also removed, since it is now
a NOP.
Signed-off-by: Dmitry
Drop support for DPU_PLANE_QOS_VBLANK_CTRL flag. It is not used both
in upstream driver and in vendor SDE driver.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 4
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c| 8
This flag is always passed to _dpu_plane_set_qos_ctrl(), so drop it and
remove corresponding conditions from the mentioned function.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 27 +++
1 file changed, 8 insertions(+), 19 deletions(-)
diff
Rework SSPP and WB code to use common helper for programming QoS
settings.
Signed-off-by: Dmitry Baryshkov
---
.../drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 4 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 31 ++-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 19 +
Slightly rearrainge code in dpu_plane_sspp_update_pipe() to group
QoS/LUT related functions.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
Get rid of intermediatory configuration structure and defines. Pass the
format and the enablement bit directly to the new helper. The
WB_CDP_CNTL register ignores BIT(2), so we can write it for both SSPP
and WB CDP settings.
Signed-off-by: Dmitry Baryshkov
---
The function dpu_plane_sspp_update_pipe() contains code to skip enabling
the QoS and OT limitis for CURSOR pipes. However all DPU since sdm845
repurpose DMA SSPP for the cursor planes because they lack the real
CURSOR SSPP. Fix the condition to actually check that the plane is
CURSOR or not.
Reorder SSPP register definitions to sort them in the ascending order.
Move register bitfields after the register definitions.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 66 +++--
1 file changed, 34 insertions(+), 32 deletions(-)
diff
Merge SSPP and WB code programming QoS and CDP. This allows us to drop
intermediate structures and duplicate code.
Changes since v1:
- Fixed kerneldoc for _dpu_plane_set_qos_ctrl()
- Fixed danger_safe_en programming conditions (Jeykumar)
- Simplified the code surrounding setup_cdp() calls
On Wed, Apr 26, 2023 at 04:57:07PM -0400, Rodrigo Vivi wrote:
> The goal is to allow for a snapshot capture to be taken at the time
> of the crash, while the print out can happen at a later time through
> the exposed devcoredump virtual device.
>
> Signed-off-by: Rodrigo Vivi
> ---
>
On 02/05/2023 03:56, Jeykumar Sankaran wrote:
On 4/30/2023 1:57 PM, Dmitry Baryshkov wrote:
The function dpu_plane_sspp_update_pipe() contains code to skip enabling
the QoS and OT limitis for CURSOR pipes. However all DPU since sdm845
repurpose DMA SSPP for the cursor planes because they lack
On Wed, Apr 26, 2023 at 04:57:05PM -0400, Rodrigo Vivi wrote:
> Let's start to move our existent logs to devcoredump one by
> one. Any format change should come on follow-up work.
>
> Signed-off-by: Rodrigo Vivi
Reviewed-by: Matthew Brost
> ---
> drivers/gpu/drm/xe/xe_devcoredump.c |
gcc on aarch64 reports
drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c: In function ‘mtk_hdmi_pll_set_rate’:
drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c:240:52: error: ‘-mgeneral-regs-only’
is incompatible with the use of floating-point types
240 | else if (tmds_clk >= 54 * MEGA && tmds_clk
From: Ville Syrjälä
On pre-TGL FEC is a port level feature, not a transcoder
level features, and it's DDI A which doesn't have it, not
trancodere A. Check for the correct thing when determining
whether FEC is supported or not.
Signed-off-by: Ville Syrjälä
---
From: Ville Syrjälä
We always check whether combo PHYs need to be re-initialized
after disabling DC states, which leads to log spam. Switch things
around so that we only log something when we actually have to
re-initialized a PHY.
The log spam was exacerbated by commit 41b4c7fe72b6 ("drm/i915:
1 - 100 of 186 matches
Mail list logo
