date:20230525

On Thu, May 25, 2023 at 11:19 AM Neil Armstrong
 wrote:
>
> On 25/05/2023 18:15, neil.armstr...@linaro.org wrote:
> > On 25/05/2023 17:57, Adam Ford wrote:
> >> On Thu, May 25, 2023 at 10:39 AM Neil Armstrong
> >>  wrote:
> >>>
> >>> On 24/05/2023 14:49, Adam Ford wrote:
>  On Wed, May 24, 2023 at 7:45 AM Fabio Estevam  wrote:
> >
> > Hi Adam,
> >
> > On Tue, May 23, 2023 at 8:49 PM Adam Ford  wrote:
> >
> >> Inki,
> >>
> >> I haven't heard back from you on whether or not you want the bindings
> >> patch to be included with me resending the series as V7 or if you're
> >> OK with a single, stand-alone patch.
> >> Will you let me know?  I have the patch standing by waiting for
> >> instructions.  If you're not the right person to ask, please let me
> >> know who the right person is.
> >
> > Neil has also been collecting samsung-dsim patches. Maybe he can 
> > clarify.
> 
>  If it matters, my preference all along was to do the bindings as a
>  separate thing once the driver updates were merged into the tree.
>  Since the bindings can be done in different ways, I was hoping to have
>  a separate discussion on the right way to do the bindings. If they
>  need to be part of the series, I can do that.
> >>>
> >>> If you don't introduce compatibles, no need to send bindings, it can
> >>> be send separately.
> >>
> >> This series doesn't change any compatibility.
> >>
> >>>
> >>> Can I apply this serie and 20230503163313.2640898-2-frie...@fris.de ? 
> >>> seems all has been reviewed.
> >>
> >> Looking at the driver, it looks like linux-next has some newer
> >> features added into the driver since I started, so this series might
> >> need a re-base.  If that's the case, let me know, and I'll do the
> >> re-base.
> >
> > Ok I'll pull the other bits and let you know if this one needs a rebase.
>
> Indeed, starting at patch 3 it fails to apply, a rebase on drm-misc-next is 
> welcome!

Neil,

I rebased and I added the dt-bindings as an additional patch to the
series.  If people are unhappy with the bindings, I am hoping you can
apply the first 6 since they don't seem to break any backwards
compatibility, and we can discuss the bindings separately if
necessary.

adam

>
> Neil
>
> >
> > Neil
> >
> >>
> >> adam
> >>
> >>>
> >>> Neil
> >>>
> 
>  adam
> >>>
> >
>

[PATCH V8 4/7] drm: bridge: samsung-dsim: Select GENERIC_PHY_MIPI_DPHY

In order to support variable DPHY timings, it's necessary
to enable GENERIC_PHY_MIPI_DPHY so phy_mipi_dphy_get_default_config
can be used to determine the nominal values for a given resolution
and refresh rate.

Signed-off-by: Adam Ford 
Tested-by: Frieder Schrempf 
Reviewed-by: Frieder Schrempf 
Tested-by: Chen-Yu Tsai 
---
 drivers/gpu/drm/bridge/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index f076a09afac0..82c68b042444 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -227,6 +227,7 @@ config DRM_SAMSUNG_DSIM
select DRM_KMS_HELPER
select DRM_MIPI_DSI
select DRM_PANEL_BRIDGE
+   select GENERIC_PHY_MIPI_DPHY
help
  The Samsung MIPI DSIM bridge controller driver.
  This MIPI DSIM bridge can be found it on Exynos SoCs and
-- 
2.39.2

[PATCH V8 6/7] drm: bridge: samsung-dsim: Support non-burst mode

The high-speed clock is hard-coded to the burst-clock
frequency specified in the device tree.  However, when
using devices like certain bridge chips without burst mode
and varying resolutions and refresh rates, it may be
necessary to set the high-speed clock dynamically based
on the desired pixel clock for the connected device.

This also removes the need to set a clock speed from
the device tree for non-burst mode operation, since the
pixel clock rate is the rate requested from the attached
device like a bridge chip.  This should have no impact
for people using burst-mode and setting the burst clock
rate is still required for those users.  If the burst
clock is not present, change the error message to
dev_info indicating the clock use the pixel clock.

Signed-off-by: Adam Ford 
Tested-by: Chen-Yu Tsai 
Tested-by: Frieder Schrempf 
Reviewed-by: Frieder Schrempf 
Tested-by: Marek Szyprowski 
Reviewed-by: Jagan Teki 
Tested-by: Jagan Teki  # imx8mm-icore
---
 drivers/gpu/drm/bridge/samsung-dsim.c | 25 +++--
 1 file changed, 19 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c 
b/drivers/gpu/drm/bridge/samsung-dsim.c
index 41f557fee29a..99ce2690582b 100644
--- a/drivers/gpu/drm/bridge/samsung-dsim.c
+++ b/drivers/gpu/drm/bridge/samsung-dsim.c
@@ -667,11 +667,21 @@ static unsigned long samsung_dsim_set_pll(struct 
samsung_dsim *dsi,
 
 static int samsung_dsim_enable_clock(struct samsung_dsim *dsi)
 {
-   unsigned long hs_clk, byte_clk, esc_clk;
+   unsigned long hs_clk, byte_clk, esc_clk, pix_clk;
unsigned long esc_div;
u32 reg;
+   struct drm_display_mode *m = >mode;
+   int bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
+
+   /* m->clock is in KHz */
+   pix_clk = m->clock * 1000;
+
+   /* Use burst_clk_rate if available, otherwise use the pix_clk */
+   if (dsi->burst_clk_rate)
+   hs_clk = samsung_dsim_set_pll(dsi, dsi->burst_clk_rate);
+   else
+   hs_clk = samsung_dsim_set_pll(dsi, DIV_ROUND_UP(pix_clk * bpp, 
dsi->lanes));
 
-   hs_clk = samsung_dsim_set_pll(dsi, dsi->burst_clk_rate);
if (!hs_clk) {
dev_err(dsi->dev, "failed to configure DSI PLL\n");
return -EFAULT;
@@ -943,7 +953,7 @@ static void samsung_dsim_set_display_mode(struct 
samsung_dsim *dsi)
u32 reg;
 
if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
-   int byte_clk_khz = dsi->burst_clk_rate / 1000 / 8;
+   int byte_clk_khz = dsi->hs_clock / 1000 / 8;
int hfp = (m->hsync_start - m->hdisplay) * byte_clk_khz / 
m->clock;
int hbp = (m->htotal - m->hsync_end) * byte_clk_khz / m->clock;
int hsa = (m->hsync_end - m->hsync_start) * byte_clk_khz / 
m->clock;
@@ -1794,10 +1804,13 @@ static int samsung_dsim_parse_dt(struct samsung_dsim 
*dsi)
return PTR_ERR(pll_clk);
}
 
+   /* If it doesn't exist, use pixel clock instead of failing */
ret = samsung_dsim_of_read_u32(node, "samsung,burst-clock-frequency",
-  >burst_clk_rate, 0);
-   if (ret < 0)
-   return ret;
+  >burst_clk_rate, 1);
+   if (ret < 0) {
+   dev_dbg(dev, "Using pixel clock for HS clock frequency\n");
+   dsi->burst_clk_rate = 0;
+   }
 
ret = samsung_dsim_of_read_u32(node, "samsung,esc-clock-frequency",
   >esc_clk_rate, 0);
-- 
2.39.2

[PATCH V8 5/7] drm: bridge: samsung-dsim: Dynamically configure DPHY timing

The DPHY timings are currently hard coded. Since the input
clock can be variable, the phy timings need to be variable
too.  To facilitate this, we need to cache the hs_clock
based on what is generated from the PLL.

The phy_mipi_dphy_get_default_config_for_hsclk function
configures the DPHY timings in pico-seconds, and a small macro
converts those timings into clock cycles based on the hs_clk.

Signed-off-by: Adam Ford 
Signed-off-by: Lucas Stach 
Tested-by: Chen-Yu Tsai 
Tested-by: Frieder Schrempf 
Reviewed-by: Frieder Schrempf 
Tested-by: Michael Walle 
Tested-by: Marek Szyprowski 
Reviewed-by: Jagan Teki 
Tested-by: Jagan Teki  # imx8mm-icore
---
 drivers/gpu/drm/bridge/samsung-dsim.c | 58 +++
 include/drm/bridge/samsung-dsim.h |  1 +
 2 files changed, 52 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c 
b/drivers/gpu/drm/bridge/samsung-dsim.c
index 307f1c20cfb9..41f557fee29a 100644
--- a/drivers/gpu/drm/bridge/samsung-dsim.c
+++ b/drivers/gpu/drm/bridge/samsung-dsim.c
@@ -220,6 +220,8 @@
 
 #define OLD_SCLK_MIPI_CLK_NAME "pll_clk"
 
+#define PS_TO_CYCLE(ps, hz) DIV64_U64_ROUND_CLOSEST(((ps) * (hz)), 
1ULL)
+
 static const char *const clk_names[5] = {
"bus_clk",
"sclk_mipi",
@@ -658,6 +660,8 @@ static unsigned long samsung_dsim_set_pll(struct 
samsung_dsim *dsi,
reg = samsung_dsim_read(dsi, DSIM_STATUS_REG);
} while ((reg & DSIM_PLL_STABLE) == 0);
 
+   dsi->hs_clock = fout;
+
return fout;
 }
 
@@ -705,13 +709,47 @@ static void samsung_dsim_set_phy_ctrl(struct samsung_dsim 
*dsi)
const struct samsung_dsim_driver_data *driver_data = dsi->driver_data;
const unsigned int *reg_values = driver_data->reg_values;
u32 reg;
+   struct phy_configure_opts_mipi_dphy cfg;
+   int clk_prepare, lpx, clk_zero, clk_post, clk_trail;
+   int hs_exit, hs_prepare, hs_zero, hs_trail;
+   unsigned long long byte_clock = dsi->hs_clock / 8;
 
if (driver_data->has_freqband)
return;
 
+   phy_mipi_dphy_get_default_config_for_hsclk(dsi->hs_clock,
+  dsi->lanes, );
+
+   /*
+* TODO:
+* The tech Applications Processor manuals for i.MX8M Mini, Nano,
+* and Plus don't state what the definition of the PHYTIMING
+* bits are beyond their address and bit position.
+* After reviewing NXP's downstream code, it appears
+* that the various PHYTIMING registers take the number
+* of cycles and use various dividers on them.  This
+* calculation does not result in an exact match to the
+* downstream code, but it is very close to the values
+* generated by their lookup table, and it appears
+* to sync at a variety of resolutions. If someone
+* can get a more accurate mathematical equation needed
+* for these registers, this should be updated.
+*/
+
+   lpx = PS_TO_CYCLE(cfg.lpx, byte_clock);
+   hs_exit = PS_TO_CYCLE(cfg.hs_exit, byte_clock);
+   clk_prepare = PS_TO_CYCLE(cfg.clk_prepare, byte_clock);
+   clk_zero = PS_TO_CYCLE(cfg.clk_zero, byte_clock);
+   clk_post = PS_TO_CYCLE(cfg.clk_post, byte_clock);
+   clk_trail = PS_TO_CYCLE(cfg.clk_trail, byte_clock);
+   hs_prepare = PS_TO_CYCLE(cfg.hs_prepare, byte_clock);
+   hs_zero = PS_TO_CYCLE(cfg.hs_zero, byte_clock);
+   hs_trail = PS_TO_CYCLE(cfg.hs_trail, byte_clock);
+
/* B D-PHY: D-PHY Master & Slave Analog Block control */
reg = reg_values[PHYCTRL_ULPS_EXIT] | reg_values[PHYCTRL_VREG_LP] |
reg_values[PHYCTRL_SLEW_UP];
+
samsung_dsim_write(dsi, DSIM_PHYCTRL_REG, reg);
 
/*
@@ -719,7 +757,9 @@ static void samsung_dsim_set_phy_ctrl(struct samsung_dsim 
*dsi)
 * T HS-EXIT: Time that the transmitter drives LP-11 following a HS
 *  burst
 */
-   reg = reg_values[PHYTIMING_LPX] | reg_values[PHYTIMING_HS_EXIT];
+
+   reg  = DSIM_PHYTIMING_LPX(lpx) | DSIM_PHYTIMING_HS_EXIT(hs_exit);
+
samsung_dsim_write(dsi, DSIM_PHYTIMING_REG, reg);
 
/*
@@ -735,10 +775,11 @@ static void samsung_dsim_set_phy_ctrl(struct samsung_dsim 
*dsi)
 * T CLK-TRAIL: Time that the transmitter drives the HS-0 state after
 *  the last payload clock bit of a HS transmission burst
 */
-   reg = reg_values[PHYTIMING_CLK_PREPARE] |
-   reg_values[PHYTIMING_CLK_ZERO] |
-   reg_values[PHYTIMING_CLK_POST] |
-   reg_values[PHYTIMING_CLK_TRAIL];
+
+   reg = DSIM_PHYTIMING1_CLK_PREPARE(clk_prepare)  |
+ DSIM_PHYTIMING1_CLK_ZERO(clk_zero)|
+ DSIM_PHYTIMING1_CLK_POST(clk_post)|
+ DSIM_PHYTIMING1_CLK_TRAIL(clk_trail);
 
samsung_dsim_write(dsi, DSIM_PHYTIMING1_REG, reg);
 
@@ -751,8 +792,11 @@ static void

[PATCH V8 7/7] dt-bindings: bridge: samsung-dsim: Make some flags optional

In the event a device is connected to the samsung-dsim
controller that doesn't support the burst-clock, the
driver is able to get the requested pixel clock from the
attached device or bridge.  In these instances, the
samsung,burst-clock-frequency isn't needed, so remove
it from the required list.

The pll-clock frequency can be set by the device tree entry
for samsung,pll-clock-frequency, but in some cases, the
pll-clock may have the same clock rate as sclk_mipi clock.
If they are equal, this flag is not needed since the driver
will use the sclk_mipi rate as a fallback.

Signed-off-by: Adam Ford 
---
 .../bindings/display/bridge/samsung,mipi-dsim.yaml   | 9 +
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git 
a/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml 
b/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml
index 9f61ebdfefa8..360fea81f4b6 100644
--- a/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml
+++ b/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml
@@ -70,7 +70,9 @@ properties:
   samsung,burst-clock-frequency:
 $ref: /schemas/types.yaml#/definitions/uint32
 description:
-  DSIM high speed burst mode frequency.
+  DSIM high speed burst mode frequency when connected to devices
+  that support burst mode. If absent, the driver will use the pixel
+  clock from the attached device or bridge.
 
   samsung,esc-clock-frequency:
 $ref: /schemas/types.yaml#/definitions/uint32
@@ -80,7 +82,8 @@ properties:
   samsung,pll-clock-frequency:
 $ref: /schemas/types.yaml#/definitions/uint32
 description:
-  DSIM oscillator clock frequency.
+  DSIM oscillator clock frequency. If absent, the driver will
+  use the clock frequency of sclk_mipi.
 
   phys:
 maxItems: 1
@@ -134,9 +137,7 @@ required:
   - compatible
   - interrupts
   - reg
-  - samsung,burst-clock-frequency
   - samsung,esc-clock-frequency
-  - samsung,pll-clock-frequency
 
 allOf:
   - $ref: ../dsi-controller.yaml#
-- 
2.39.2

[PATCH V8 3/7] drm: bridge: samsung-dsim: Fetch pll-clock-frequency automatically

Make the pll-clock-frequency optional.  If it's present, use it
to maintain backwards compatibility with existing hardware.  If it
is absent, read clock rate of "sclk_mipi" to determine the rate.
Since it can be optional, change the message from an error to
dev_info.

Signed-off-by: Adam Ford 
Tested-by: Chen-Yu Tsai 
Tested-by: Frieder Schrempf 
Reviewed-by: Frieder Schrempf 
Tested-by: Marek Szyprowski 
Reviewed-by: Jagan Teki 
Tested-by: Jagan Teki  # imx8mm-icore
---
 drivers/gpu/drm/bridge/samsung-dsim.c | 22 +++---
 1 file changed, 15 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c 
b/drivers/gpu/drm/bridge/samsung-dsim.c
index ead922c3ce9f..307f1c20cfb9 100644
--- a/drivers/gpu/drm/bridge/samsung-dsim.c
+++ b/drivers/gpu/drm/bridge/samsung-dsim.c
@@ -1719,11 +1719,11 @@ static const struct mipi_dsi_host_ops samsung_dsim_ops 
= {
 };
 
 static int samsung_dsim_of_read_u32(const struct device_node *np,
-   const char *propname, u32 *out_value)
+   const char *propname, u32 *out_value, bool 
optional)
 {
int ret = of_property_read_u32(np, propname, out_value);
 
-   if (ret < 0)
+   if (ret < 0 && !optional)
pr_err("%pOF: failed to get '%s' property\n", np, propname);
 
return ret;
@@ -1736,19 +1736,27 @@ static int samsung_dsim_parse_dt(struct samsung_dsim 
*dsi)
u32 lane_polarities[5] = { 0 };
struct device_node *endpoint;
int i, nr_lanes, ret;
+   struct clk *pll_clk;
 
ret = samsung_dsim_of_read_u32(node, "samsung,pll-clock-frequency",
-  >pll_clk_rate);
-   if (ret < 0)
-   return ret;
+  >pll_clk_rate, 1);
+   /* If it doesn't exist, read it from the clock instead of failing */
+   if (ret < 0) {
+   dev_dbg(dev, "Using sclk_mipi for pll clock frequency\n");
+   pll_clk = devm_clk_get(dev, "sclk_mipi");
+   if (!IS_ERR(pll_clk))
+   dsi->pll_clk_rate = clk_get_rate(pll_clk);
+   else
+   return PTR_ERR(pll_clk);
+   }
 
ret = samsung_dsim_of_read_u32(node, "samsung,burst-clock-frequency",
-  >burst_clk_rate);
+  >burst_clk_rate, 0);
if (ret < 0)
return ret;
 
ret = samsung_dsim_of_read_u32(node, "samsung,esc-clock-frequency",
-  >esc_clk_rate);
+  >esc_clk_rate, 0);
if (ret < 0)
return ret;
 
-- 
2.39.2

[PATCH V8 1/7] drm: bridge: samsung-dsim: fix blanking packet size calculation

From: Lucas Stach 

Scale the blanking packet sizes to match the ratio between HS clock
and DPI interface clock. The controller seems to do internal scaling
to the number of active lanes, so we don't take those into account.

Signed-off-by: Lucas Stach 
Signed-off-by: Adam Ford 
Tested-by: Chen-Yu Tsai 
Tested-by: Frieder Schrempf 
Tested-by: Marek Szyprowski 
Reviewed-by: Jagan Teki 
Tested-by: Jagan Teki  # imx8mm-icore
---
 drivers/gpu/drm/bridge/samsung-dsim.c | 18 +++---
 1 file changed, 15 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c 
b/drivers/gpu/drm/bridge/samsung-dsim.c
index 0f3f6846beea..a2d1eaf0ed1c 100644
--- a/drivers/gpu/drm/bridge/samsung-dsim.c
+++ b/drivers/gpu/drm/bridge/samsung-dsim.c
@@ -881,17 +881,29 @@ static void samsung_dsim_set_display_mode(struct 
samsung_dsim *dsi)
u32 reg;
 
if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
+   int byte_clk_khz = dsi->burst_clk_rate / 1000 / 8;
+   int hfp = (m->hsync_start - m->hdisplay) * byte_clk_khz / 
m->clock;
+   int hbp = (m->htotal - m->hsync_end) * byte_clk_khz / m->clock;
+   int hsa = (m->hsync_end - m->hsync_start) * byte_clk_khz / 
m->clock;
+
+   /* remove packet overhead when possible */
+   hfp = max(hfp - 6, 0);
+   hbp = max(hbp - 6, 0);
+   hsa = max(hsa - 6, 0);
+
+   dev_dbg(dsi->dev, "calculated hfp: %u, hbp: %u, hsa: %u",
+   hfp, hbp, hsa);
+
reg = DSIM_CMD_ALLOW(0xf)
| DSIM_STABLE_VFP(m->vsync_start - m->vdisplay)
| DSIM_MAIN_VBP(m->vtotal - m->vsync_end);
samsung_dsim_write(dsi, DSIM_MVPORCH_REG, reg);
 
-   reg = DSIM_MAIN_HFP(m->hsync_start - m->hdisplay)
-   | DSIM_MAIN_HBP(m->htotal - m->hsync_end);
+   reg = DSIM_MAIN_HFP(hfp) | DSIM_MAIN_HBP(hbp);
samsung_dsim_write(dsi, DSIM_MHPORCH_REG, reg);
 
reg = DSIM_MAIN_VSA(m->vsync_end - m->vsync_start)
-   | DSIM_MAIN_HSA(m->hsync_end - m->hsync_start);
+   | DSIM_MAIN_HSA(hsa);
samsung_dsim_write(dsi, DSIM_MSYNC_REG, reg);
}
reg =  DSIM_MAIN_HRESOL(m->hdisplay, num_bits_resol) |
-- 
2.39.2

[PATCH V8 2/7] drm: bridge: samsung-dsim: Fix PMS Calculator on imx8m[mnp]

According to Table 13-45 of the i.MX8M Mini Reference Manual, the min
and max values for M and the frequency range for the VCO_out
calculator were incorrect.  This information was contradicted in other
parts of the mini, nano and plus manuals.  After reaching out to my
NXP Rep, when confronting him about discrepencies in the Nano manual,
he responded with:
 "Yes it is definitely wrong, the one that is part
  of the NOTE in MIPI_DPHY_M_PLLPMS register table against PMS_P,
  PMS_M and PMS_S is not correct. I will report this to Doc team,
  the one customer should be take into account is the Table 13-40
  DPHY PLL Parameters and the Note above."

These updated values also match what is used in the NXP downstream
kernel.

To fix this, make new variables to hold the min and max values of m
and the minimum value of VCO_out, and update the PMS calculator to
use these new variables instead of using hard-coded values to keep
the backwards compatibility with other parts using this driver.

Fixes: 4d562c70c4dc ("drm: bridge: samsung-dsim: Add i.MX8M Mini/Nano support")
Signed-off-by: Adam Ford 
Reviewed-by: Lucas Stach 
Tested-by: Chen-Yu Tsai 
Tested-by: Frieder Schrempf 
Reviewed-by: Frieder Schrempf 
Tested-by: Marek Szyprowski 
Reviewed-by: Jagan Teki 
Tested-by: Jagan Teki  # imx8mm-icore
---
 drivers/gpu/drm/bridge/samsung-dsim.c | 22 --
 include/drm/bridge/samsung-dsim.h |  3 +++
 2 files changed, 23 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c 
b/drivers/gpu/drm/bridge/samsung-dsim.c
index a2d1eaf0ed1c..ead922c3ce9f 100644
--- a/drivers/gpu/drm/bridge/samsung-dsim.c
+++ b/drivers/gpu/drm/bridge/samsung-dsim.c
@@ -407,6 +407,9 @@ static const struct samsung_dsim_driver_data 
exynos3_dsi_driver_data = {
.num_bits_resol = 11,
.pll_p_offset = 13,
.reg_values = reg_values,
+   .m_min = 41,
+   .m_max = 125,
+   .min_freq = 500,
 };
 
 static const struct samsung_dsim_driver_data exynos4_dsi_driver_data = {
@@ -420,6 +423,9 @@ static const struct samsung_dsim_driver_data 
exynos4_dsi_driver_data = {
.num_bits_resol = 11,
.pll_p_offset = 13,
.reg_values = reg_values,
+   .m_min = 41,
+   .m_max = 125,
+   .min_freq = 500,
 };
 
 static const struct samsung_dsim_driver_data exynos5_dsi_driver_data = {
@@ -431,6 +437,9 @@ static const struct samsung_dsim_driver_data 
exynos5_dsi_driver_data = {
.num_bits_resol = 11,
.pll_p_offset = 13,
.reg_values = reg_values,
+   .m_min = 41,
+   .m_max = 125,
+   .min_freq = 500,
 };
 
 static const struct samsung_dsim_driver_data exynos5433_dsi_driver_data = {
@@ -443,6 +452,9 @@ static const struct samsung_dsim_driver_data 
exynos5433_dsi_driver_data = {
.num_bits_resol = 12,
.pll_p_offset = 13,
.reg_values = exynos5433_reg_values,
+   .m_min = 41,
+   .m_max = 125,
+   .min_freq = 500,
 };
 
 static const struct samsung_dsim_driver_data exynos5422_dsi_driver_data = {
@@ -455,6 +467,9 @@ static const struct samsung_dsim_driver_data 
exynos5422_dsi_driver_data = {
.num_bits_resol = 12,
.pll_p_offset = 13,
.reg_values = exynos5422_reg_values,
+   .m_min = 41,
+   .m_max = 125,
+   .min_freq = 500,
 };
 
 static const struct samsung_dsim_driver_data imx8mm_dsi_driver_data = {
@@ -471,6 +486,9 @@ static const struct samsung_dsim_driver_data 
imx8mm_dsi_driver_data = {
 */
.pll_p_offset = 14,
.reg_values = imx8mm_dsim_reg_values,
+   .m_min = 64,
+   .m_max = 1023,
+   .min_freq = 1050,
 };
 
 static const struct samsung_dsim_driver_data *
@@ -549,12 +567,12 @@ static unsigned long samsung_dsim_pll_find_pms(struct 
samsung_dsim *dsi,
tmp = (u64)fout * (_p << _s);
do_div(tmp, fin);
_m = tmp;
-   if (_m < 41 || _m > 125)
+   if (_m < driver_data->m_min || _m > driver_data->m_max)
continue;
 
tmp = (u64)_m * fin;
do_div(tmp, _p);
-   if (tmp < 500 * MHZ ||
+   if (tmp < driver_data->min_freq  * MHZ ||
tmp > driver_data->max_freq * MHZ)
continue;
 
diff --git a/include/drm/bridge/samsung-dsim.h 
b/include/drm/bridge/samsung-dsim.h
index 6a37d1e079bf..2c20b9460c9a 100644
--- a/include/drm/bridge/samsung-dsim.h
+++ b/include/drm/bridge/samsung-dsim.h
@@ -54,11 +54,14 @@ struct samsung_dsim_driver_data {
unsigned int has_freqband:1;
unsigned int has_clklane_stop:1;
unsigned int num_clks;
+   unsigned int min_freq;
unsigned int max_freq;
unsigned int wait_for_reset;
unsigned int num_bits_resol;
unsigned int pll_p_offset;
const unsigned int *reg_values;
+   u16

[PATCH V8 0/7] drm: bridge: samsung-dsim: Support variable clocking

This series fixes the blanking pack size and the PMS calculation.  It then
adds support to allows the DSIM to dynamically DPHY clocks, and support
non-burst mode while allowing the removal of the hard-coded clock values
for the PLL for imx8m mini/nano/plus, and it allows the removal of the
burst-clock device tree entry when burst-mode isn't supported by connected
devices like an HDMI brige.  In that event, the HS clock is set to the
value requested by the bridge chip.

This has been tested on both an i.MX8M Nano and i.MX8M Plus, and should
work on i.MX8M Mini as well. Marek Szyprowski has tested it on various
Exynos boards.

Adam Ford (6):
  drm: bridge: samsung-dsim: Fix PMS Calculator on imx8m[mnp]
  drm: bridge: samsung-dsim: Fetch pll-clock-frequency automatically
  drm: bridge: samsung-dsim: Select GENERIC_PHY_MIPI_DPHY
  drm: bridge: samsung-dsim: Dynamically configure DPHY timing
  drm: bridge: samsung-dsim: Support non-burst mode
  dt-bindings: bridge: samsung-dsim: Make some flags optional

Lucas Stach (1):
  drm: bridge: samsung-dsim: fix blanking packet size calculation

V8:  Rebase.  Add dt-bindings to series as Patch 7/7

V7:  Move messages indicating the optional device tree items are going
 to be automatically read elsewhere was move to dev_dbg instead of
 dev_info.  Cleaned up some of the comments to be a bit more clear.
 Eliminated a double variable assignement accidentally introduced
 in V6 when some of the items were moved from patch 6 to patch 5.

V6:  Squash-in an additional error fix from Lucas Stach regarding the
 DPHY calcuations.  Remove the dynamic_dphy variable and let
 everyone use the new calculations.  Move the hs_clock caching
 from patch 6 to patch 5 to go along with the DPHY calcuations
 since they are now based on the recorded hs_clock rate.
 
V5:  Update error message to dev_info and change them to indicate
 what is happening without sounding like an error when optional
 device tree entries are missing.

V4:  Undo some accidental whitespace changes, rename PS_TO_CYCLE
 variables to ps and hz from PS and MHz. Remove if check
 before the samsung_dsim_set_phy_ctrl call since it's
 unnecessary.
 Added additional tested-by and reviewed-by comments.
 Squash patches 6 and 7 together since the supporting
 non-burst (patch 6) mode doesn't really work until
 patch 7 was applied.

V3:  When checking if the bust-clock is present, only check for it
 in the device tree, and don't check the presence of the
 MIPI_DSI_MODE_VIDEO_BURST flag as it breaks an existing Exynos
 board.

 Add a new patch to the series to select GENERIC_PHY_MIPI_DPHY in
 Kconfig otherwise the build breaks on the 32-bit Exynos.

 Change vco_min variable name to min_freq

 Added tested-by from Chen-Yu Tsai

V2:  Instead of using my packet blanking calculation, this integrates
 on from Lucas Stach which gets modified later in the series to
 cache the value of the HS-clock instead of having to do the
 calucations again.

 Instead of completely eliminating the PLL clock frequency from
 the device tree, this makes it optional to avoid breaking some
 Samsung devices.  When the samsung,pll-clock-frequency is not
 found, it reads the value of the clock named "sclk_mipi"
 This also maintains backwards compatibility with older device
 trees.

 This also changes the DPHY calcuation from a Look-up table,
 a reverse engineered algorithm which uses
 phy_mipi_dphy_get_default_config to determine the standard
 nominal values and calculates the cycles necessary to update
 the DPHY timings accordingly.pu/drm/bridge/Kconfig|   1 +
 drivers/gpu/drm/bridge/samsung-dsim.c | 141 +++---
 include/drm/bridge/samsung-dsim.h |   4 +
 4 files changed, 128 insertions(+), 27 deletions(-)

V8:  Rebase onto the current master branch.  Add dt-bindings to series.

V7:  Move messages indicating the optional device tree items are going
 to be automatically read elsewhere was move to dev_dbg instead of
 dev_info.  Cleaned up some of the comments to be a bit more clear.
 Eliminated a double variable assignement accidentally introduced
 in V6 when some of the items were moved from patch 6 to patch 5.

V6:  Squash-in an additional error fix from Lucas Stach regarding the
 DPHY calcuations.  Remove the dynamic_dphy variable and let
 everyone use the new calculations.  Move the hs_clock caching
 from patch 6 to patch 5 to go along with the DPHY calcuations
 since they are now based on the recorded hs_clock rate.
 
V5:  Update error message to dev_info and change them to indicate
 what is happening without sounding like an error when optional
 device tree entries are missing.

V4:  Undo some accidental whitespace changes, rename PS_TO_CYCLE
 variables to ps and hz from PS and MHz. Remove if check
 before

Re: [PATCH v4 05/11] drm/mediatek: gamma: Enable the Gamma LUT table only after programming

2023-05-25 Thread 胡俊光

RE: [PATCH] drm/amdkfd: remove unused function get_reserved_sdma_queues_bitmap

2023-05-25 Thread Joshi, Mukul

[AMD Official Use Only - General]

> -Original Message-
> From: Kuehling, Felix 
> Sent: Thursday, May 25, 2023 5:10 PM
> To: Tom Rix ; Deucher, Alexander
> ; Koenig, Christian
> ; Pan, Xinhui ;
> airl...@gmail.com; dan...@ffwll.ch; nat...@kernel.org;
> ndesaulni...@google.com; Joshi, Mukul 
> Cc: amd-...@lists.freedesktop.org; dri-devel@lists.freedesktop.org; linux-
> ker...@vger.kernel.org; l...@lists.linux.dev
> Subject: Re: [PATCH] drm/amdkfd: remove unused function
> get_reserved_sdma_queues_bitmap
>
> [+Mukul]
>
> Looks like this problem was introduced by Mukul's patch "drm/amdkfd:
> Update SDMA queue management for GFX9.4.3". Could this be a merge
> error between GFX 9.4.3 and GFX11 branches? I think the
> reserved_sdma_queues_bitmap was introduced after the 9.4.3 branch was
> created. Mukul, you worked on both, so you're probably in the best position
> to resolve this.
>

Yes my patch introduced this regression. We need the 
get_reserved_sdma_queues_bitmap function.
I will fix this regression and send out a new patch.

Thanks for noticing/catching this.

Regards,
Mukul

> Regards,
>Felix
>
>
> On 2023-05-25 16:07, Tom Rix wrote:
> > clang with W=1 reports
> >
> drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_device_queue_manager.c:12
> 2:24: error:
> >unused function 'get_reserved_sdma_queues_bitmap'
> > [-Werror,-Wunused-function] static inline uint64_t
> get_reserved_sdma_queues_bitmap(struct device_queue_manager *dqm)
> > ^
> > This function is not used so remove it.
> >
> > Signed-off-by: Tom Rix 
> > ---
> >   drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 5 -
> >   1 file changed, 5 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> > b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> > index 493b4b66f180..2fbd0a96424f 100644
> > --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> > +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> > @@ -119,11 +119,6 @@ unsigned int get_num_xgmi_sdma_queues(struct
> device_queue_manager *dqm)
> > dqm->dev->kfd-
> >device_info.num_sdma_queues_per_engine;
> >   }
> >
> > -static inline uint64_t get_reserved_sdma_queues_bitmap(struct
> > device_queue_manager *dqm) -{
> > -   return dqm->dev->kfd-
> >device_info.reserved_sdma_queues_bitmap;
> > -}
> > -
> >   static void init_sdma_bitmaps(struct device_queue_manager *dqm)
> >   {
> > bitmap_zero(dqm->sdma_bitmap, KFD_MAX_SDMA_QUEUES);

Re: [PATCH 5/6] drm/i915/uc/gsc: define gsc fw

2023-05-25 Thread Teres Alexis, Alan Previn

Considering the only request i have below is touching up of existing comments 
(as
far as this patch is concerned), and since the rest of the code looks good, 
here is
my R-b - but i hope you can anwser my newbie question at the bottom:

Reviewed-by: Alan Previn 

On Fri, 2023-05-05 at 09:04 -0700, Ceraolo Spurio, Daniele wrote:
> Add FW definition and the matching override modparam.
> 
> The GSC FW has both a release version, based on platform and a rolling
> counter, and a compatibility version, which is the one tracking
> interface changes. Since what we care about is the interface, we use
> the compatibility version in the buinary names.
alan :s/buinary/binary

> 
> Same as with the GuC, a major version bump indicate a
> backward-incompatible change, while a minor version bump indicates a
> backward-compatible one, so we use only the former in the file name.
> 
> Signed-off-by: Daniele Ceraolo Spurio 
> Cc: Alan Previn 
> Cc: John Harrison 
> ---
>  drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 32 ++--
>  1 file changed, 24 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c 
> b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
> index 36ee96c02d74..531cd172151d 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
> @@ -124,6 +124,18 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw,
>   fw_def(BROXTON,  0, huc_mmp(bxt,  2, 0, 0)) \
>   fw_def(SKYLAKE,  0, huc_mmp(skl,  2, 0, 0))
>  
> +/*
> + * The GSC FW has both a release version, based on platform and a rolling
> + * counter, and a compatibility version, which is the one tracking
> + * interface changes. Since what we care about is the interface, we use
> + * the compatibility version in the buinary names.
alan:s/buinary/binary
also, since we will (i hope) be adding several comments (alongside the new
version objects under intel_gsc_uc structure) in the patch #3 about what
their differences are and which one we care about and when they get populated,
perhaps we can minimize the information here and redirect to that other
comment... OR ... we can minimize the comments in patch #3 and redirect here
(will be good to have a single location with detailed explaination in the
comments and a redirect-ptr from the other location since a reader would
most likely stumble onto those questions from either of these locations).

> + * Same as with the GuC, a major version bump indicate a
> + * backward-incompatible change, while a minor version bump indicates a
> + * backward-compatible one, so we use only the former in the file name.
> + */
> +#define INTEL_GSC_FIRMWARE_DEFS(fw_def, gsc_def) \
> + fw_def(METEORLAKE,   0, gsc_def(mtl, 1, 0))
> +
>  /*
>  
> 
alan:snip

> @@ -257,14 +281,6 @@ __uc_fw_auto_select(struct drm_i915_private *i915, 
> struct intel_uc_fw *uc_fw)
>   int i;
>   bool found;
>  
> - /*
> -  * GSC FW support is still not fully in place, so we're not defining
> -  * the FW blob yet because we don't want the driver to attempt to load
> -  * it until we're ready for it.
> -  */
> - if (uc_fw->type == INTEL_UC_FW_TYPE_GSC)
> - return;
> -
alan: more of a newbie question from myself: considering this is a new firmware
we are adding, is there some kind of requirement to provide a link to the patch
targetting the linux firmware repo that is a dependency of this series?
or perhaps we should mention in the series that merge will only happen after
that patch gets merged (with a final rev that includes the patch on
the fw-repo side?). Just trying to understand the process.


>   /*
>* The only difference between the ADL GuC FWs is the HWConfig support.
>* ADL-N does not support HWConfig, so we should use the same binary as

Re: [PATCH v10 00/10] drm/hdcp: Pull HDCP auth/exchange/check into helpers

2023-05-25 Thread Doug Anderson

Mark,

On Mon, May 22, 2023 at 5:59 AM Rodrigo Vivi  wrote:
>
> On Sat, May 20, 2023 at 02:07:51AM +0300, Dmitry Baryshkov wrote:
> > On 20/05/2023 00:16, Rodrigo Vivi wrote:
> > > On Fri, May 19, 2023 at 07:55:47PM +0300, Dmitry Baryshkov wrote:
> > > > On 19/04/2023 18:43, Mark Yacoub wrote:
> > > > > Hi all,
> > > > > This is v10 of the HDCP patches. The patches are authored by Sean 
> > > > > Paul.
> > > > > I rebased and addressed the review comments in v6-v10.
> > > > >
> > > > > Main change in v10 is handling the kernel test bot warnings.
> > > > >
> > > > > Patches 1-4 focus on moving the common HDCP helpers to common DRM.
> > > > > This introduces a slight change in the original intel flow
> > > > > as it splits the unique driver protocol from the generic 
> > > > > implementation.
> > > > >
> > > > > Patches 5-7 split the HDCP flow on the i915 driver to make use of the 
> > > > > common DRM helpers.
> > > > >
> > > > > Patches 8-10 implement HDCP on MSM driver.
> > > > >
> > > > > Thanks,
> > > > > -Mark Yacoub
> > > > >
> > > > > Sean Paul (10):
> > > > > drm/hdcp: Add drm_hdcp_atomic_check()
> > > > > drm/hdcp: Avoid changing crtc state in hdcp atomic check
> > > > > drm/hdcp: Update property value on content type and user changes
> > > > > drm/hdcp: Expand HDCP helper library for enable/disable/check
> > > > > drm/i915/hdcp: Consolidate HDCP setup/state cache
> > > > > drm/i915/hdcp: Retain hdcp_capable return codes
> > > > > drm/i915/hdcp: Use HDCP helpers for i915
> > > > > dt-bindings: msm/dp: Add bindings for HDCP registers
> > > > > arm64: dts: qcom: sc7180: Add support for HDCP in dp-controller
> > > >
> > > > Dear i915 maintainers,
> > > >
> > > > I wanted to ping you regarding this patch series. If there are no 
> > > > comments
> > > > for the series from you side, would it be possible to land 
> > > > Intel-specific
> > > > and generic patches into drm-intel tree? We will continue working on 
> > > > the msm
> > > > specific parts and merge them through the msm tree.
> > >
> > > pushed to drm-intel-next.
> > >
> > > should be propagated in a few weeks to drm-next on our next pull request.
> >
> > Probably there is some kind of confusion here. You've pushed the DSC
> > patches, while the response was sent to the HDCP series.
>
> I'm sorry, my confusion for replying to the wrong thread.
>
> So, on this one here I believe it would be helpful if there's a split
> in the series with the already reviewed ones related to i915 are resent
> separated from the rest, send with --subject-prefix="CI" so when that
> pass CI we just merge it through drm-intel-next

It sounds like this is waiting on you to post just the first 7 patches
with the proper subject prefix so they can land through the Intel
tree.

-Doug

Re: [PATCH 4/6] drm/i915/uc/gsc: query the GSC FW for its compatibility version

2023-05-25 Thread Teres Alexis, Alan Previn

On Fri, 2023-05-05 at 09:04 -0700, Ceraolo Spurio, Daniele wrote:
> The compatibility version is queried via an MKHI command. Right now, the
> only existing interface is 1.0
> This is basically the interface version for the GSC FW, so the plan is
> to use it as the main tracked version, including for the binary naming
> in the fetch code.
> 
> Signed-off-by: Daniele Ceraolo Spurio 
> 

alan: just a couple of minor things nits below.
One ask though, in line with the clarification we had over the offline 
coversation,
I am wondering if we can document the fact that the file_selected.ver remains 
as major-minor::zero-zero
for the case of gsc until after the firmware is loaded and we query via this 
function (which happens
later at gt-late-init). However, that comment might not belong here - perhaps 
it belongs in the prior
patch together with the other comment i requested for (asking for additional 
explainations about the
different types of versions for gsc).

That said, for this patch, LGTM:
Reviewed-by: Alan Previn 

alan:snip
> +static int gsc_fw_query_compatibility_version(struct intel_gsc_uc *gsc)
> +{
> + struct intel_gt *gt = gsc_uc_to_gt(gsc);
> + struct mtl_gsc_ver_msg_in *msg_in;
> + struct mtl_gsc_ver_msg_out *msg_out;
> + struct i915_vma *vma;
> + u64 offset;
> + void *vaddr;
> + int err;
> +
> + err = intel_guc_allocate_and_map_vma(>uc.guc, PAGE_SIZE * 2,
> +  , );
alan: nit: im assuming this code will be used for future discrete cards,.. if 
so,
perhaps we should also be using "SZ_4K * 2" above since different host-cpu-arch
could have different PAGE sizes - this way we'll be consistent with exact size 
allocations.
also its more consistent in this function - maybe a #define 
GSC_UC_GET_ABI_VER_PKT_SIZE SZ_4K
at top of function is nice. either way, i consider this a nit.

> + if (err) {
> + gt_err(gt, "failed to allocate vma for GSC version query\n");
> + return err;
> + }

alan:snip

> +
>  int intel_gsc_uc_fw_upload(struct intel_gsc_uc *gsc)
>  {
>   struct intel_gt *gt = gsc_uc_to_gt(gsc);
> @@ -327,11 +406,21 @@ int intel_gsc_uc_fw_upload(struct intel_gsc_uc *gsc)
>   if (err)
>   goto fail;
>  
> + err = gsc_fw_query_compatibility_version(gsc);
> + if (err)
> + goto fail;
> +
> + /* we only support compatibility version 1.0 at the moment */
> + err = intel_uc_check_file_version(gsc_fw, NULL);
> + if (err)
> + goto fail;
> +
>   /* FW is not fully operational until we enable SW proxy */
>   intel_uc_fw_change_status(gsc_fw, INTEL_UC_FIRMWARE_TRANSFERRED);
>  
> - gt_info(gt, "Loaded GSC firmware %s (r%u.%u.%u.%u, svn%u)\n",
> + gt_info(gt, "Loaded GSC firmware %s (cv%u.%u, r%u.%u.%u.%u, svn %u)\n",
alan:nit "abi" instead of "cv"?
>   gsc_fw->file_selected.path,
> + gsc_fw->file_selected.ver.major, 
> gsc_fw->file_selected.ver.minor,
>   gsc->release.major, gsc->release.minor,
>   gsc->release.patch, gsc->release.build,
>   gsc->security_version);
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.h 
> b/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.h
> index 8f199d5f963e..fb1453ed4ecf 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.h
alan:snip

> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c 
> b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
> index cd8fc194f7fa..36ee96c02d74 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
alan:snip

> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h 
> b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h
> index 279244744d43..4406e7b48b27 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h
alan:snip

Re: [Freedreno] [PATCH v2 3/6] drm/msm/dpu: split interrupt address arrays

2023-05-25 Thread Abhinav Kumar





On 5/25/2023 3:30 PM, Dmitry Baryshkov wrote:

On Fri, 26 May 2023 at 00:40, Jeykumar Sankaran
 wrote:




On 5/22/2023 2:45 PM, Dmitry Baryshkov wrote:

There is no point in having a single enum (and a single array) for both
DPU < 7.0 and DPU >= 7.0 interrupt registers. Instead define a single
enum and two IRQ address arrays.

Signed-off-by: Dmitry Baryshkov 
---
   .../msm/disp/dpu1/catalog/dpu_7_0_sm8350.h|  1 +
   .../msm/disp/dpu1/catalog/dpu_7_2_sc7280.h|  1 +
   .../msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h  |  1 +
   .../msm/disp/dpu1/catalog/dpu_8_1_sm8450.h|  1 +
   .../msm/disp/dpu1/catalog/dpu_9_0_sm8550.h|  1 +
   .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h|  2 +
   .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 82 +--
   .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 28 ---
   8 files changed, 79 insertions(+), 38 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h 
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
index 3c1b2c13398d..320cfa4be633 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
@@ -15,6 +15,7 @@ static const struct dpu_caps sm8350_dpu_caps = {
   .has_dim_layer = true,
   .has_idle_pc = true,
   .has_3d_merge = true,
+ .has_7xxx_intr = true,
   .max_linewidth = 4096,
   .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
   };
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h 
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
index 5d894cbb0a62..9306c7a115e9 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
@@ -13,6 +13,7 @@ static const struct dpu_caps sc7280_dpu_caps = {
   .qseed_type = DPU_SSPP_SCALER_QSEED4,
   .has_dim_layer = true,
   .has_idle_pc = true,
+ .has_7xxx_intr = true,
   .max_linewidth = 2400,
   .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
   };
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h 
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
index c3f1ae000a21..fc1e17c495f0 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
@@ -15,6 +15,7 @@ static const struct dpu_caps sc8280xp_dpu_caps = {
   .has_dim_layer = true,
   .has_idle_pc = true,
   .has_3d_merge = true,
+ .has_7xxx_intr = true,
   .max_linewidth = 5120,
   .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
   };
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h 
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
index 86c2e68ebd2c..eb72411c16db 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
@@ -14,6 +14,7 @@ static const struct dpu_caps sm8450_dpu_caps = {
   .has_src_split = true,
   .has_dim_layer = true,
   .has_idle_pc = true,
+ .has_7xxx_intr = true,
   .has_3d_merge = true,
   .max_linewidth = 5120,
   .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h 
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
index 85dc34458b88..8209ca317bdc 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
@@ -15,6 +15,7 @@ static const struct dpu_caps sm8550_dpu_caps = {
   .has_dim_layer = true,
   .has_idle_pc = true,
   .has_3d_merge = true,
+ .has_7xxx_intr = true,
   .max_linewidth = 5120,
   .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
   };
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 677048cc3b7d..72530ebb0ae6 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -351,6 +351,7 @@ struct dpu_rotation_cfg {
* @has_dim_layer  dim layer feature status
* @has_idle_pcindicate if idle power collapse feature is supported
* @has_3d_merge   indicate if 3D merge is supported
+ * @has_7xxx_intr  indicate that INTF/IRQs use addressing for DPU 7.0 and 
greater


I see the requirement to distinguish feature support based on the DPU
version in more than one series. Is it a good idea to bring in the DPU
version info in chipset catalog? This will relieve us from maintaining
such version flags for individual HW sub-blocks.


This would not play well with the rest of the driver. The driver
usually does not compute features by DPU revision. Instead it lists
feature flags.



So I am increasingly seeing examples such as data_compress, widebus 
where it looks like version based enablement in the code will be just 
more efficient. For example.


if (DPU_MAJOR_VER > xxx && DPU_MAJOR_VER < yyy)
enable data_compress;

will be much easier to

Re: [Freedreno] [PATCH v2 3/6] drm/msm/dpu: split interrupt address arrays

2023-05-25 Thread Dmitry Baryshkov

On Fri, 26 May 2023 at 00:40, Jeykumar Sankaran
 wrote:
>
>
>
> On 5/22/2023 2:45 PM, Dmitry Baryshkov wrote:
> > There is no point in having a single enum (and a single array) for both
> > DPU < 7.0 and DPU >= 7.0 interrupt registers. Instead define a single
> > enum and two IRQ address arrays.
> >
> > Signed-off-by: Dmitry Baryshkov 
> > ---
> >   .../msm/disp/dpu1/catalog/dpu_7_0_sm8350.h|  1 +
> >   .../msm/disp/dpu1/catalog/dpu_7_2_sc7280.h|  1 +
> >   .../msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h  |  1 +
> >   .../msm/disp/dpu1/catalog/dpu_8_1_sm8450.h|  1 +
> >   .../msm/disp/dpu1/catalog/dpu_9_0_sm8550.h|  1 +
> >   .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h|  2 +
> >   .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 82 +--
> >   .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 28 ---
> >   8 files changed, 79 insertions(+), 38 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h 
> > b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> > index 3c1b2c13398d..320cfa4be633 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> > @@ -15,6 +15,7 @@ static const struct dpu_caps sm8350_dpu_caps = {
> >   .has_dim_layer = true,
> >   .has_idle_pc = true,
> >   .has_3d_merge = true,
> > + .has_7xxx_intr = true,
> >   .max_linewidth = 4096,
> >   .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
> >   };
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h 
> > b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> > index 5d894cbb0a62..9306c7a115e9 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> > @@ -13,6 +13,7 @@ static const struct dpu_caps sc7280_dpu_caps = {
> >   .qseed_type = DPU_SSPP_SCALER_QSEED4,
> >   .has_dim_layer = true,
> >   .has_idle_pc = true,
> > + .has_7xxx_intr = true,
> >   .max_linewidth = 2400,
> >   .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
> >   };
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h 
> > b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> > index c3f1ae000a21..fc1e17c495f0 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> > @@ -15,6 +15,7 @@ static const struct dpu_caps sc8280xp_dpu_caps = {
> >   .has_dim_layer = true,
> >   .has_idle_pc = true,
> >   .has_3d_merge = true,
> > + .has_7xxx_intr = true,
> >   .max_linewidth = 5120,
> >   .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
> >   };
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h 
> > b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> > index 86c2e68ebd2c..eb72411c16db 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> > @@ -14,6 +14,7 @@ static const struct dpu_caps sm8450_dpu_caps = {
> >   .has_src_split = true,
> >   .has_dim_layer = true,
> >   .has_idle_pc = true,
> > + .has_7xxx_intr = true,
> >   .has_3d_merge = true,
> >   .max_linewidth = 5120,
> >   .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h 
> > b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> > index 85dc34458b88..8209ca317bdc 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> > @@ -15,6 +15,7 @@ static const struct dpu_caps sm8550_dpu_caps = {
> >   .has_dim_layer = true,
> >   .has_idle_pc = true,
> >   .has_3d_merge = true,
> > + .has_7xxx_intr = true,
> >   .max_linewidth = 5120,
> >   .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
> >   };
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h 
> > b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> > index 677048cc3b7d..72530ebb0ae6 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> > @@ -351,6 +351,7 @@ struct dpu_rotation_cfg {
> >* @has_dim_layer  dim layer feature status
> >* @has_idle_pcindicate if idle power collapse feature is 
> > supported
> >* @has_3d_merge   indicate if 3D merge is supported
> > + * @has_7xxx_intr  indicate that INTF/IRQs use addressing for DPU 7.0 
> > and greater
>
> I see the requirement to distinguish feature support based on the DPU
> version in more than one series. Is it a good idea to bring in the DPU
> version info in chipset catalog? This will relieve us from maintaining
> such version flags for individual HW sub-blocks.

This would not play well with the rest of the driver. The driver
usually does not compute features by DPU revision. Instead it lists

Re: [PATCH 2/2] drm/panel: Add driver for Visionox r66451 panel

2023-05-25 Thread Jessica Zhang





On 5/23/2023 1:33 PM, Jessica Zhang wrote:



On 5/21/2023 3:28 AM, Marijn Suijten wrote:

On 2023-05-18 03:19:49, Dmitry Baryshkov wrote:

On 16/05/2023 23:20, Jessica Zhang wrote:

Add support for the 1080x2340 Visionox R66451 AMOLED DSI panel that
comes with the Qualcomm HDK8350 display expansion pack.

The panel enables display compression (DSC v1.2) by default.

Signed-off-by: Jessica Zhang 
---
   drivers/gpu/drm/panel/Kconfig |   8 +
   drivers/gpu/drm/panel/Makefile    |   1 +
   drivers/gpu/drm/panel/panel-visionox-r66451.c | 395 
++

   3 files changed, 404 insertions(+)

diff --git a/drivers/gpu/drm/panel/Kconfig 
b/drivers/gpu/drm/panel/Kconfig

index 29cf5fa39ff2..9c2c36dbddf3 100644
--- a/drivers/gpu/drm/panel/Kconfig
+++ b/drivers/gpu/drm/panel/Kconfig
@@ -766,6 +766,14 @@ config DRM_PANEL_VISIONOX_VTDR6130
 Say Y here if you want to enable support for Visionox
 VTDR6130 1080x2400 AMOLED DSI panel.
+config DRM_PANEL_VISIONOX_R66451
+    tristate "Visionox R66451"
+    depends on OF
+    depends on DRM_MIPI_DSI
+    help
+  Say Y here if you want to enable support for Visionox
+  R66451 1080x2340 AMOLED DSI panel.
+
   config DRM_PANEL_WIDECHIPS_WS2401
   tristate "Widechips WS2401 DPI panel driver"
   depends on SPI && GPIOLIB
diff --git a/drivers/gpu/drm/panel/Makefile 
b/drivers/gpu/drm/panel/Makefile

index b3e8ba29edd3..e043a92ee676 100644
--- a/drivers/gpu/drm/panel/Makefile
+++ b/drivers/gpu/drm/panel/Makefile
@@ -78,5 +78,6 @@ obj-$(CONFIG_DRM_PANEL_TPO_TPG110) += 
panel-tpo-tpg110.o

   obj-$(CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA) += panel-truly-nt35597.o
   obj-$(CONFIG_DRM_PANEL_VISIONOX_RM69299) += panel-visionox-rm69299.o
   obj-$(CONFIG_DRM_PANEL_VISIONOX_VTDR6130) += 
panel-visionox-vtdr6130.o

+obj-$(CONFIG_DRM_PANEL_VISIONOX_R66451) += panel-visionox-r66451.o
   obj-$(CONFIG_DRM_PANEL_WIDECHIPS_WS2401) += panel-widechips-ws2401.o
   obj-$(CONFIG_DRM_PANEL_XINPENG_XPP055C272) += 
panel-xinpeng-xpp055c272.o
diff --git a/drivers/gpu/drm/panel/panel-visionox-r66451.c 
b/drivers/gpu/drm/panel/panel-visionox-r66451.c

new file mode 100644
index ..e3648ead3e84
--- /dev/null
+++ b/drivers/gpu/drm/panel/panel-visionox-r66451.c
@@ -0,0 +1,395 @@
+//SPDX-License-Identifier: GPL-2.0-only
+//Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights 
reserved.

+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+struct visionox_r66451 {
+    struct drm_panel panel;
+    struct mipi_dsi_device *dsi;
+    struct gpio_desc *reset_gpio;
+    struct regulator_bulk_data supplies[2];
+    bool prepared, enabled;
+};
+
+static inline struct visionox_r66451 *to_visionox_r66451(struct 
drm_panel *panel)

+{
+    return container_of(panel, struct visionox_r66451, panel);
+}
+
+static void visionox_r66451_reset(struct visionox_r66451 *ctx)
+{
+    gpiod_set_value_cansleep(ctx->reset_gpio, 0);
+    usleep_range(1, 10100);
+    gpiod_set_value_cansleep(ctx->reset_gpio, 1);
+    usleep_range(1, 10100);
+    gpiod_set_value_cansleep(ctx->reset_gpio, 0);
+    usleep_range(1, 10100);
+}
+
+static int visionox_r66451_on(struct visionox_r66451 *ctx)
+{
+    struct mipi_dsi_device *dsi = ctx->dsi;
+    struct device *dev = >dev;
+    int ret;
+
+    dsi->mode_flags |= MIPI_DSI_MODE_LPM;
+
+    mipi_dsi_dcs_write_seq(dsi, 0xb0, 0x00);
+    mipi_dsi_dcs_write_seq(dsi, 0xc2,
+   0x09, 0x24, 0x0c, 0x00, 0x00, 0x0c, 0x00, 0x00, 
0x00,

+   0x09, 0x3c);
+    mipi_dsi_dcs_write_seq(dsi, 0xd7,
+   0x00, 0xb9, 0x3c, 0x00, 0x40, 0x04, 0x00, 0xa0, 
0x0a,
+   0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
0x19,

+   0x3c, 0x00, 0x40, 0x04, 0x00, 0xa0, 0x0a);
+    mipi_dsi_dcs_write_seq(dsi, 0xb0, 0x80);
+    mipi_dsi_dcs_write_seq(dsi, 0xde,
+   0x40, 0x00, 0x18, 0x00, 0x18, 0x00, 0x18, 0x00, 
0x18,
+   0x10, 0x00, 0x18, 0x00, 0x18, 0x00, 0x18, 0x02, 
0x00, 0x00);

+    mipi_dsi_dcs_write_seq(dsi, 0xb0, 0x04);
+    mipi_dsi_dcs_write_seq(dsi, 0xe8, 0x00, 0x02);
+    mipi_dsi_dcs_write_seq(dsi, 0xe4, 0x00, 0x08);
+    mipi_dsi_dcs_write_seq(dsi, 0xb0, 0x00);
+    mipi_dsi_dcs_write_seq(dsi, 0xc4,
+   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
0x00,

+   0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x32);
+    mipi_dsi_dcs_write_seq(dsi, 0xcf,
+   0x64, 0x0b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
0x08,
+   0x00, 0x0b, 0x77, 0x01, 0x01, 0x01, 0x01, 0x01, 
0x01,

+   0x02, 0x02, 0x02, 0x02, 0x02, 0x03);
+    mipi_dsi_dcs_write_seq(dsi, 0xd3,
+   0x45, 0x00, 0x00, 0x01, 0x13, 0x15, 0x00, 0x15, 
0x07,
+   0x0f, 0x77, 0x77, 0x77, 0x37, 0xb2, 0x11, 0x00, 
0xa0,

+   0x3c, 0x9c);
+

Re: [PATCH 3/6] drm/i915/uc/gsc: extract release and security versions from the gsc binary

2023-05-25 Thread Teres Alexis, Alan Previn

On Thu, 2023-05-25 at 09:56 -0700, Ceraolo Spurio, Daniele wrote:
> On 5/24/2023 10:14 PM, Teres Alexis, Alan Previn wrote:
> > On Fri, 2023-05-05 at 09:04 -0700, Ceraolo Spurio, Daniele wrote:
alan:snip
> > > --- a/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.h
> > > +++ b/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.h
> > > @@ -17,6 +17,9 @@ struct intel_gsc_uc {
> > >   struct intel_uc_fw fw;
> > > 
> > >   /* GSC-specific additions */
> > > + struct intel_uc_fw_ver release;
> > > + u32 security_version;
> > alan: for consistency and less redundancy, can't we add "security_version"
> > into 'struct intel_uc_fw_ver' (which is zero for firmware that doesn't
> > have it). That way, intel_gsc_uc can re-use intel_uc_fw.file_selected
> > just like huc?
> 
> I'm not sure what you mean by re-using intel_uc_fw.file_selected. Is 
> that for the call from intel_uc_fw_version_from_meu_manifest? I'm 
> purposely not doing that. Note that the GSC has 3 versions:
> 
> Release version (incremented with each build and encoded in the header)
> Security version (also encoded in the header)
> Compatibility version (queried via message to the GSC)
> 
> The one we care about for communicating with the GSC is the last one, so 
> that's the one I stored in intel_uc_fw.file_selected (in the next 
> patch). The other 2  versions are not strictly required to use the GSC 
> and we only fetch them for debug purposes, so if something goes wrong we 
> know exactly what we've loaded.
> 
> Daniele
alan: okay thanks - seeing that now in the next patch... (and i also forgot that
the GSC release version doesnt reflect interface versioning in anyway like GuC 
does).
In that case, above additional versions are fine. Would definitely love to see
additional comments under "GSC-specific-additions" that explain those 3 
versioning
items and what we care about as how you have explained here.

RE: [PATCH v2 3/7] drm/i915: Fix CHV CGM CSC coefficient sign handling



> -Original Message-
> From: Shankar, Uma
> Sent: Friday, May 26, 2023 2:25 AM
> To: Ville Syrjala ; 
> intel-...@lists.freedesktop.org
> Cc: dri-devel@lists.freedesktop.org
> Subject: RE: [PATCH v2 3/7] drm/i915: Fix CHV CGM CSC coefficient sign 
> handling
> 
> 
> 
> > -Original Message-
> > From: dri-devel  On Behalf Of
> > Ville Syrjala
> > Sent: Thursday, April 13, 2023 10:19 PM
> > To: intel-...@lists.freedesktop.org
> > Cc: dri-devel@lists.freedesktop.org
> > Subject: [PATCH v2 3/7] drm/i915: Fix CHV CGM CSC coefficient sign
> > handling
> >
> > From: Ville Syrjälä 
> >
> > The CHV CGM CSC coefficients are in s4.12 two's complement format. Fix
> > the CTM-
> > >CGM conversion to handle that correctly instead of pretending that
> > >the hw
> > coefficients are also in some sign-magnitude format.
> 
> Spec is slightly confusing when it says:
> "CGM CSC :  Input pixels to the CGM CSC are 14 bits. (u.14 format). 
> Coefficients are
> 16 bits (s3.12)."
> Also here:
> "Programmable parameters :
> c0[15 :0], c1[15 :0], c2[15 :0], c3[15 :0], c4[15 :0], c5[15 :0], c6[15 :0], 
> c7[15 :0],
> c8[15 :0] ; // signed matrix coefficients  (s3.12)"
> 
> But the coefficients are 16bits, can you help understand how were you able to 
> crack
> this 

I think I got it. Looks good to me.
Reviewed-by: Uma Shankar 

> > Signed-off-by: Ville Syrjälä 
> > ---
> >  drivers/gpu/drm/i915/display/intel_color.c | 46
> > ++
> >  1 file changed, 29 insertions(+), 17 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_color.c
> > b/drivers/gpu/drm/i915/display/intel_color.c
> > index 4fc16cac052d..63141f4ed372 100644
> > --- a/drivers/gpu/drm/i915/display/intel_color.c
> > +++ b/drivers/gpu/drm/i915/display/intel_color.c
> > @@ -568,29 +568,41 @@ static void icl_load_csc_matrix(const struct
> > intel_crtc_state *crtc_state)
> > icl_update_output_csc(crtc, _state->output_csc);  }
> >
> > +static u16 ctm_to_twos_complement(u64 coeff, int int_bits, int
> > +frac_bits) {
> > +   s64 c = CTM_COEFF_ABS(coeff);
> > +
> > +   /* leave an extra bit for rounding */
> > +   c >>= 32 - frac_bits - 1;
> > +
> > +   /* round and drop the extra bit */
> > +   c = (c + 1) >> 1;
> > +
> > +   if (CTM_COEFF_NEGATIVE(coeff))
> > +   c = -c;
> > +
> > +   c = clamp(c, -(s64)BIT(int_bits + frac_bits - 1),
> > + (s64)(BIT(int_bits + frac_bits - 1) - 1));
> > +
> > +   return c & (BIT(int_bits + frac_bits) - 1); }
> > +
> > +/*
> > + * CHV Color Gamut Mapping (CGM) CSC
> > + * |r|   | c0 c1 c2 |   |r|
> > + * |g| = | c3 c4 c5 | x |g|
> > + * |b|   | c6 c7 c8 |   |b|
> > + *
> > + * Coefficients are two's complement s4.12.
> > + */
> >  static void chv_cgm_csc_convert_ctm(const struct intel_crtc_state 
> > *crtc_state,
> > struct intel_csc_matrix *csc)  {
> > const struct drm_color_ctm *ctm = crtc_state->hw.ctm->data;
> > int i;
> >
> > -   for (i = 0; i < 9; i++) {
> > -   u64 abs_coeff = ((1ULL << 63) - 1) & ctm->matrix[i];
> > -
> > -   /* Round coefficient. */
> > -   abs_coeff += 1 << (32 - 13);
> > -   /* Clamp to hardware limits. */
> > -   abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_8_0 - 1);
> > -
> > -   csc->coeff[i] = 0;
> > -
> > -   /* Write coefficients in S3.12 format. */
> > -   if (ctm->matrix[i] & (1ULL << 63))
> > -   csc->coeff[i] |= 1 << 15;
> > -
> > -   csc->coeff[i] |= ((abs_coeff >> 32) & 7) << 12;
> > -   csc->coeff[i] |= (abs_coeff >> 20) & 0xfff;
> > -   }
> > +   for (i = 0; i < 9; i++)
> > +   csc->coeff[i] = ctm_to_twos_complement(ctm->matrix[i], 4, 12);
> >  }
> >
> >  static void chv_load_cgm_csc(struct intel_crtc *crtc,
> > --
> > 2.39.2

RE: [Intel-gfx] [PATCH v2 6/7] drm/i915: No 10bit gamma on desktop gen3 parts



> -Original Message-
> From: Intel-gfx  On Behalf Of Ville 
> Syrjala
> Sent: Thursday, April 13, 2023 10:19 PM
> To: intel-...@lists.freedesktop.org
> Cc: dri-devel@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v2 6/7] drm/i915: No 10bit gamma on desktop gen3 
> parts
> 
> From: Ville Syrjälä 
> 
> Apparently desktop gen3 parts don't support the 10bit gamma mode at all. Stop
> claiming otherwise.
> 
> As is the case with pipe A on gen3 mobile parts, the PIPECONF gamma mode bit 
> can
> be set but it has no effect on the output.
> 
> PNV seems to be the only slight exception, but generally the desktop PNV 
> variant
> looks more like a mobile part so this is not entirely surprising.

Couldn't check the relevant spec to re-confirm, trusting your judgment here.
Reviewed-by: Uma Shankar 

> Fixes: 67630bacae23 ("drm/i915: Add 10bit gamma mode for gen2/3")
> Signed-off-by: Ville Syrjälä 
> ---
>  drivers/gpu/drm/i915/i915_pci.c | 8 +++-
>  1 file changed, 7 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_pci.c 
> b/drivers/gpu/drm/i915/i915_pci.c index
> cddb6e197972..305c05c3f93b 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -250,13 +250,13 @@ static const struct intel_device_info i865g_info = {
>   .dma_mask_size = 32, \
>   I9XX_PIPE_OFFSETS, \
>   I9XX_CURSOR_OFFSETS, \
> - I9XX_COLORS, \
>   GEN_DEFAULT_PAGE_SIZES, \
>   GEN_DEFAULT_REGIONS
> 
>  static const struct intel_device_info i915g_info = {
>   GEN3_FEATURES,
>   PLATFORM(INTEL_I915G),
> + I845_COLORS,
>   .has_coherent_ggtt = false,
>   .display.cursor_needs_physical = 1,
>   .display.has_overlay = 1,
> @@ -268,6 +268,7 @@ static const struct intel_device_info i915g_info = {  
> static
> const struct intel_device_info i915gm_info = {
>   GEN3_FEATURES,
>   PLATFORM(INTEL_I915GM),
> + I9XX_COLORS,
>   .is_mobile = 1,
>   .display.cursor_needs_physical = 1,
>   .display.has_overlay = 1,
> @@ -281,6 +282,7 @@ static const struct intel_device_info i915gm_info = {  
> static
> const struct intel_device_info i945g_info = {
>   GEN3_FEATURES,
>   PLATFORM(INTEL_I945G),
> + I845_COLORS,
>   .display.has_hotplug = 1,
>   .display.cursor_needs_physical = 1,
>   .display.has_overlay = 1,
> @@ -292,6 +294,7 @@ static const struct intel_device_info i945g_info = {  
> static
> const struct intel_device_info i945gm_info = {
>   GEN3_FEATURES,
>   PLATFORM(INTEL_I945GM),
> + I9XX_COLORS,
>   .is_mobile = 1,
>   .display.has_hotplug = 1,
>   .display.cursor_needs_physical = 1,
> @@ -306,6 +309,7 @@ static const struct intel_device_info i945gm_info = {  
> static
> const struct intel_device_info g33_info = {
>   GEN3_FEATURES,
>   PLATFORM(INTEL_G33),
> + I845_COLORS,
>   .display.has_hotplug = 1,
>   .display.has_overlay = 1,
>   .dma_mask_size = 36,
> @@ -314,6 +318,7 @@ static const struct intel_device_info g33_info = {  static
> const struct intel_device_info pnv_g_info = {
>   GEN3_FEATURES,
>   PLATFORM(INTEL_PINEVIEW),
> + I9XX_COLORS,
>   .display.has_hotplug = 1,
>   .display.has_overlay = 1,
>   .dma_mask_size = 36,
> @@ -322,6 +327,7 @@ static const struct intel_device_info pnv_g_info = {  
> static
> const struct intel_device_info pnv_m_info = {
>   GEN3_FEATURES,
>   PLATFORM(INTEL_PINEVIEW),
> + I9XX_COLORS,
>   .is_mobile = 1,
>   .display.has_hotplug = 1,
>   .display.has_overlay = 1,
> --
> 2.39.2

Re: [PATCH v14 3/9] drm/display/dsc: Add drm_dsc_get_bpp_int helper

2023-05-25 Thread Dmitry Baryshkov

On Thu, 25 May 2023 at 23:18, Marijn Suijten
 wrote:
>
> On 2023-05-24 15:38:23, Jessica Zhang wrote:
> 
> > >> +  WARN_ON_ONCE(vdsc_cfg->bits_per_pixel & 0xf);
> > >
> > > You did not add linux/bug.h back, presumably because Dmitry added
> > > another use of WARN_ON_ONCE to this file in a previous series and it
> > > compiles fine as the definition trickles in via another header?
> >
> > Yep, this compiles fine without any error or warning.
>
> Yes it does, just curious (CC Dmitry) if that is expected/intended: I am
> not familiar enough with the current header includes to say for sure.
>
> Dmitry seemed to rely on it already being available in
> https://git.kernel.org/torvalds/c/2b470e5531f57c1b9bfa129cca0ee17a2ecd2183

I think I did not care about including  I checked that
current set of headers provides WARN_ON_ONCE, that's all.

> but that could have been an oversight?
>
> - Marijn



-- 
With best wishes
Dmitry

RE: [Intel-gfx] [PATCH v2 5/7] drm/i915: Implement CTM property support for VLV



> -Original Message-
> From: Intel-gfx  On Behalf Of Ville 
> Syrjala
> Sent: Thursday, April 13, 2023 10:19 PM
> To: intel-...@lists.freedesktop.org
> Cc: dri-devel@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v2 5/7] drm/i915: Implement CTM property support 
> for
> VLV
> 
> From: Ville Syrjälä 
> 
> VLV has a so called "wide gamut color correction" unit (WGC).
> What it is is a 3x3 matrix similar to the later CHV CGM CSC, which less
> precisions/range. In fact CHV also has the WGC but using it there doesn't 
> reall make
> sense when you have the superior CGM CSC around.
> 
> Hook up the necessary stuff to expose the WGC as the CTM crtc property.
> 
> One additional crazy idea that came to mind would be to use the WGC as an 
> output
> CSC on CHV for YCbCr output. But it would be incompatible with the legacy LUT
> usage. In fact since the WGC lacks post-offsets we'd probably have to use the 
> legacy
> LUT to do that final part of the RGB->YCbCr conversion. Sounds doable, but 
> perhaps
> not worth the hassle.

Yeah WGC on CHV was just kept for safety against any hw issue, with plan to 
drop in future platforms.
Exposing it for VLV is nice.

Changes look good to me.
Reviewed-by:  Uma Shankar 

> Signed-off-by: Ville Syrjälä 
> ---
>  drivers/gpu/drm/i915/display/intel_color.c| 170 +-
>  .../drm/i915/display/intel_crtc_state_dump.c  |   6 +-
>  drivers/gpu/drm/i915/display/intel_display.c  |   8 +
>  .../drm/i915/display/intel_display_types.h|   3 +
>  drivers/gpu/drm/i915/i915_reg.h   |  15 ++
>  5 files changed, 198 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c
> b/drivers/gpu/drm/i915/display/intel_color.c
> index 7a705e7d8776..e36d8c248b84 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -587,6 +587,98 @@ static u16 ctm_to_twos_complement(u64 coeff, int
> int_bits, int frac_bits)
>   return c & (BIT(int_bits + frac_bits) - 1);  }
> 
> +/*
> + * VLV/CHV Wide Gamut Color Correction (WGC) CSC
> + * |r|   | c0 c1 c2 |   |r|
> + * |g| = | c3 c4 c5 | x |g|
> + * |b|   | c6 c7 c8 |   |b|
> + *
> + * Coefficients are two's complement s2.10.
> + */
> +static void vlv_wgc_csc_convert_ctm(const struct intel_crtc_state 
> *crtc_state,
> + struct intel_csc_matrix *csc)
> +{
> + const struct drm_color_ctm *ctm = crtc_state->hw.ctm->data;
> + int i;
> +
> + for (i = 0; i < 9; i++)
> + csc->coeff[i] = ctm_to_twos_complement(ctm->matrix[i], 2, 10); }
> +
> +static void vlv_load_wgc_csc(struct intel_crtc *crtc,
> +  const struct intel_csc_matrix *csc) {
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + enum pipe pipe = crtc->pipe;
> +
> + intel_de_write_fw(dev_priv, PIPE_WGC_C01_C00(pipe),
> +   csc->coeff[1] << 16 | csc->coeff[0]);
> + intel_de_write_fw(dev_priv, PIPE_WGC_C02(pipe),
> +   csc->coeff[2]);
> +
> + intel_de_write_fw(dev_priv, PIPE_WGC_C11_C10(pipe),
> +   csc->coeff[4] << 16 | csc->coeff[3]);
> + intel_de_write_fw(dev_priv, PIPE_WGC_C12(pipe),
> +   csc->coeff[5]);
> +
> + intel_de_write_fw(dev_priv, PIPE_WGC_C21_C20(pipe),
> +   csc->coeff[7] << 16 | csc->coeff[6]);
> + intel_de_write_fw(dev_priv, PIPE_WGC_C22(pipe),
> +   csc->coeff[8]);
> +}
> +
> +static void vlv_read_wgc_csc(struct intel_crtc *crtc,
> +  struct intel_csc_matrix *csc)
> +{
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + enum pipe pipe = crtc->pipe;
> + u32 tmp;
> +
> + tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C01_C00(pipe));
> + csc->coeff[0] = tmp & 0x;
> + csc->coeff[1] = tmp >> 16;
> +
> + tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C02(pipe));
> + csc->coeff[2] = tmp & 0x;
> +
> + tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C11_C10(pipe));
> + csc->coeff[3] = tmp & 0x;
> + csc->coeff[4] = tmp >> 16;
> +
> + tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C12(pipe));
> + csc->coeff[5] = tmp & 0x;
> +
> + tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C21_C20(pipe));
> + csc->coeff[6] = tmp & 0x;
> + csc->coeff[7] = tmp >> 16;
> +
> + tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C22(pipe));
> + csc->coeff[8] = tmp & 0x;
> +}
> +
> +static void vlv_read_csc(struct intel_crtc_state *crtc_state) {
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> +
> + if (crtc_state->wgc_enable)
> + vlv_read_wgc_csc(crtc, _state->csc); }
> +
> +static void vlv_assign_csc(struct intel_crtc_state *crtc_state) {
> + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
> +
> + if (crtc_state->hw.ctm) {
> + drm_WARN_ON(>drm,

[PATCH] drm/nouveau/acr: remove unused variable loc

gcc with W=1 reports
drivers/gpu/drm/nouveau/nvkm/subdev/acr/lsfw.c:221:21: error: variable
  ‘loc’ set but not used [-Werror=unused-but-set-variable]
  221 | u32 loc, sig, cnt, *meta;
  | ^~~
This variable is not used so remove it.

Signed-off-by: Tom Rix 
---
 drivers/gpu/drm/nouveau/nvkm/subdev/acr/lsfw.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/acr/lsfw.c 
b/drivers/gpu/drm/nouveau/nvkm/subdev/acr/lsfw.c
index f36a359d4531..bd104a030243 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/acr/lsfw.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/acr/lsfw.c
@@ -218,7 +218,7 @@ nvkm_acr_lsfw_load_sig_image_desc_v2(struct nvkm_subdev 
*subdev,
const struct firmware *hsbl;
const struct nvfw_ls_hsbl_bin_hdr *hdr;
const struct nvfw_ls_hsbl_hdr *hshdr;
-   u32 loc, sig, cnt, *meta;
+   u32 sig, cnt, *meta;
 
ret = nvkm_firmware_load_name(subdev, path, "hs_bl_sig", ver, 
);
if (ret)
@@ -227,7 +227,6 @@ nvkm_acr_lsfw_load_sig_image_desc_v2(struct nvkm_subdev 
*subdev,
hdr = nvfw_ls_hsbl_bin_hdr(subdev, hsbl->data);
hshdr = nvfw_ls_hsbl_hdr(subdev, hsbl->data + 
hdr->header_offset);
meta = (u32 *)(hsbl->data + hshdr->meta_data_offset);
-   loc = *(u32 *)(hsbl->data + hshdr->patch_loc);
sig = *(u32 *)(hsbl->data + hshdr->patch_sig);
cnt = *(u32 *)(hsbl->data + hshdr->num_sig);
 
-- 
2.27.0

Re: [PATCH] drm/amdkfd: remove unused function get_reserved_sdma_queues_bitmap

2023-05-25 Thread Felix Kuehling


[+Mukul]

Looks like this problem was introduced by Mukul's patch "drm/amdkfd: 
Update SDMA queue management for GFX9.4.3". Could this be a merge error 
between GFX 9.4.3 and GFX11 branches? I think the 
reserved_sdma_queues_bitmap was introduced after the 9.4.3 branch was 
created. Mukul, you worked on both, so you're probably in the best 
position to resolve this.


Regards,
  Felix


On 2023-05-25 16:07, Tom Rix wrote:

clang with W=1 reports
drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_device_queue_manager.c:122:24: error:
   unused function 'get_reserved_sdma_queues_bitmap' [-Werror,-Wunused-function]
static inline uint64_t get_reserved_sdma_queues_bitmap(struct 
device_queue_manager *dqm)
^
This function is not used so remove it.

Signed-off-by: Tom Rix 
---
  drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 5 -
  1 file changed, 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
index 493b4b66f180..2fbd0a96424f 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
@@ -119,11 +119,6 @@ unsigned int get_num_xgmi_sdma_queues(struct 
device_queue_manager *dqm)
dqm->dev->kfd->device_info.num_sdma_queues_per_engine;
  }
  
-static inline uint64_t get_reserved_sdma_queues_bitmap(struct device_queue_manager *dqm)

-{
-   return dqm->dev->kfd->device_info.reserved_sdma_queues_bitmap;
-}
-
  static void init_sdma_bitmaps(struct device_queue_manager *dqm)
  {
bitmap_zero(dqm->sdma_bitmap, KFD_MAX_SDMA_QUEUES);

[PATCH] drm/radeon: remove unused variable rbo

gcc with W=1 reports
drivers/gpu/drm/radeon/radeon_ttm.c:200:27: error: variable
  ‘rbo’ set but not used [-Werror=unused-but-set-variable]
  200 | struct radeon_bo *rbo;
  |   ^~~
This variable is not used so remove it.

Signed-off-by: Tom Rix 
---
 drivers/gpu/drm/radeon/radeon_ttm.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c 
b/drivers/gpu/drm/radeon/radeon_ttm.c
index 4eb83ccc4906..de4e6d78f1e1 100644
--- a/drivers/gpu/drm/radeon/radeon_ttm.c
+++ b/drivers/gpu/drm/radeon/radeon_ttm.c
@@ -197,7 +197,6 @@ static int radeon_bo_move(struct ttm_buffer_object *bo, 
bool evict,
 {
struct ttm_resource *old_mem = bo->resource;
struct radeon_device *rdev;
-   struct radeon_bo *rbo;
int r;
 
if (new_mem->mem_type == TTM_PL_TT) {
@@ -210,7 +209,6 @@ static int radeon_bo_move(struct ttm_buffer_object *bo, 
bool evict,
if (r)
return r;
 
-   rbo = container_of(bo, struct radeon_bo, tbo);
rdev = radeon_get_rdev(bo->bdev);
if (!old_mem || (old_mem->mem_type == TTM_PL_SYSTEM &&
 bo->ttm == NULL)) {
-- 
2.27.0

RE: [Intel-gfx] [PATCH v2 4/7] drm/i915: Always enable CGM CSC on CHV



> -Original Message-
> From: Intel-gfx  On Behalf Of Ville 
> Syrjala
> Sent: Thursday, April 13, 2023 10:19 PM
> To: intel-...@lists.freedesktop.org
> Cc: dri-devel@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v2 4/7] drm/i915: Always enable CGM CSC on CHV
> 
> From: Ville Syrjälä 
> 
> On CHV toggling the CGM CSC on/off while the pipe is running leads to 
> underruns.
> Looks like we'd have to do the toggling strictly inside the start_of_vblank-
> frame_start window to avoid this, but that window is less than a scanline so 
> there's
> no way we can guarantee hitting it.
> 
> As a workaround let's just leave the CGM CSC permanently enabled.
> Fortunately the CGM gamma/degamma units don't seem to suffer from this malady.
> 
> I also tried turning off CGM unit clock gating, but that did not help.

Looks Good to me.
Reviewed-by: Uma Shankar 

> Signed-off-by: Ville Syrjälä 
> ---
>  drivers/gpu/drm/i915/display/intel_color.c | 21 +++--
>  1 file changed, 19 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c
> b/drivers/gpu/drm/i915/display/intel_color.c
> index 63141f4ed372..7a705e7d8776 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -605,6 +605,16 @@ static void chv_cgm_csc_convert_ctm(const struct
> intel_crtc_state *crtc_state,
>   csc->coeff[i] = ctm_to_twos_complement(ctm->matrix[i], 4, 12);  
> }
> 
> +#define CHV_CGM_CSC_COEFF_1_0 (1 << 12)
> +
> +static const struct intel_csc_matrix chv_cgm_csc_matrix_identity = {
> + .coeff = {
> + CHV_CGM_CSC_COEFF_1_0, 0, 0,
> + 0, CHV_CGM_CSC_COEFF_1_0, 0,
> + 0, 0, CHV_CGM_CSC_COEFF_1_0,
> + },
> +};
> +
>  static void chv_load_cgm_csc(struct intel_crtc *crtc,
>const struct intel_csc_matrix *csc)  { @@ -667,9 
> +677,9
> @@ static void chv_assign_csc(struct intel_crtc_state *crtc_state)
> 
>   chv_cgm_csc_convert_ctm(crtc_state, _state->csc);
>   } else {
> - drm_WARN_ON(>drm, (crtc_state->cgm_mode &
> CGM_PIPE_MODE_CSC) != 0);
> + drm_WARN_ON(>drm, (crtc_state->cgm_mode &
> CGM_PIPE_MODE_CSC) ==
> +0);
> 
> - intel_csc_clear(_state->csc);
> + crtc_state->csc = chv_cgm_csc_matrix_identity;
>   }
>  }
> 
> @@ -2033,6 +2043,13 @@ static u32 chv_cgm_mode(const struct intel_crtc_state
> *crtc_state)
>   !lut_is_legacy(crtc_state->hw.gamma_lut))
>   cgm_mode |= CGM_PIPE_MODE_GAMMA;
> 
> + /*
> +  * Toggling the CGM CSC on/off outside of the tiny window
> +  * between start of vblank and frame start causes underruns.
> +  * Always enable the CGM CSC as a workaround.
> +  */
> + cgm_mode |= CGM_PIPE_MODE_CSC;
> +
>   return cgm_mode;
>  }
> 
> --
> 2.39.2

RE: [PATCH v2 3/7] drm/i915: Fix CHV CGM CSC coefficient sign handling



> -Original Message-
> From: dri-devel  On Behalf Of Ville 
> Syrjala
> Sent: Thursday, April 13, 2023 10:19 PM
> To: intel-...@lists.freedesktop.org
> Cc: dri-devel@lists.freedesktop.org
> Subject: [PATCH v2 3/7] drm/i915: Fix CHV CGM CSC coefficient sign handling
> 
> From: Ville Syrjälä 
> 
> The CHV CGM CSC coefficients are in s4.12 two's complement format. Fix the 
> CTM-
> >CGM conversion to handle that correctly instead of pretending that the hw
> coefficients are also in some sign-magnitude format.

Spec is slightly confusing when it says:
"CGM CSC :  Input pixels to the CGM CSC are 14 bits. (u.14 format). 
Coefficients are 16 bits (s3.12)."
Also here:
"Programmable parameters : 
c0[15 :0], c1[15 :0], c2[15 :0], c3[15 :0], c4[15 :0], c5[15 :0], c6[15 :0], 
c7[15 :0], c8[15 :0] ; // signed matrix coefficients  (s3.12)"

But the coefficients are 16bits, can you help understand how were you able to 
crack this 

> Signed-off-by: Ville Syrjälä 
> ---
>  drivers/gpu/drm/i915/display/intel_color.c | 46 ++
>  1 file changed, 29 insertions(+), 17 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c
> b/drivers/gpu/drm/i915/display/intel_color.c
> index 4fc16cac052d..63141f4ed372 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -568,29 +568,41 @@ static void icl_load_csc_matrix(const struct
> intel_crtc_state *crtc_state)
>   icl_update_output_csc(crtc, _state->output_csc);  }
> 
> +static u16 ctm_to_twos_complement(u64 coeff, int int_bits, int
> +frac_bits) {
> + s64 c = CTM_COEFF_ABS(coeff);
> +
> + /* leave an extra bit for rounding */
> + c >>= 32 - frac_bits - 1;
> +
> + /* round and drop the extra bit */
> + c = (c + 1) >> 1;
> +
> + if (CTM_COEFF_NEGATIVE(coeff))
> + c = -c;
> +
> + c = clamp(c, -(s64)BIT(int_bits + frac_bits - 1),
> +   (s64)(BIT(int_bits + frac_bits - 1) - 1));
> +
> + return c & (BIT(int_bits + frac_bits) - 1); }
> +
> +/*
> + * CHV Color Gamut Mapping (CGM) CSC
> + * |r|   | c0 c1 c2 |   |r|
> + * |g| = | c3 c4 c5 | x |g|
> + * |b|   | c6 c7 c8 |   |b|
> + *
> + * Coefficients are two's complement s4.12.
> + */
>  static void chv_cgm_csc_convert_ctm(const struct intel_crtc_state 
> *crtc_state,
>   struct intel_csc_matrix *csc)
>  {
>   const struct drm_color_ctm *ctm = crtc_state->hw.ctm->data;
>   int i;
> 
> - for (i = 0; i < 9; i++) {
> - u64 abs_coeff = ((1ULL << 63) - 1) & ctm->matrix[i];
> -
> - /* Round coefficient. */
> - abs_coeff += 1 << (32 - 13);
> - /* Clamp to hardware limits. */
> - abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_8_0 - 1);
> -
> - csc->coeff[i] = 0;
> -
> - /* Write coefficients in S3.12 format. */
> - if (ctm->matrix[i] & (1ULL << 63))
> - csc->coeff[i] |= 1 << 15;
> -
> - csc->coeff[i] |= ((abs_coeff >> 32) & 7) << 12;
> - csc->coeff[i] |= (abs_coeff >> 20) & 0xfff;
> - }
> + for (i = 0; i < 9; i++)
> + csc->coeff[i] = ctm_to_twos_complement(ctm->matrix[i], 4, 12);
>  }
> 
>  static void chv_load_cgm_csc(struct intel_crtc *crtc,
> --
> 2.39.2

Re: [PATCH 01/13] drm: execution context for GEM buffers v4

2023-05-25 Thread Danilo Krummrich


On 5/4/23 13:51, Christian König wrote:

This adds the infrastructure for an execution context for GEM buffers
which is similar to the existing TTMs execbuf util and intended to replace
it in the long term.

The basic functionality is that we abstracts the necessary loop to lock
many different GEM buffers with automated deadlock and duplicate handling.

v2: drop xarray and use dynamic resized array instead, the locking
 overhead is unecessary and measurable.
v3: drop duplicate tracking, radeon is really the only one needing that.
v4: fixes issues pointed out by Danilo, some typos in comments and a
 helper for lock arrays of GEM objects.

Signed-off-by: Christian König 


Reviewed-by: Danilo Krummrich 


---
  Documentation/gpu/drm-mm.rst |  12 ++
  drivers/gpu/drm/Kconfig  |   6 +
  drivers/gpu/drm/Makefile |   2 +
  drivers/gpu/drm/drm_exec.c   | 278 +++
  include/drm/drm_exec.h   | 119 +++
  5 files changed, 417 insertions(+)
  create mode 100644 drivers/gpu/drm/drm_exec.c
  create mode 100644 include/drm/drm_exec.h

diff --git a/Documentation/gpu/drm-mm.rst b/Documentation/gpu/drm-mm.rst
index a79fd3549ff8..a52e6f4117d6 100644
--- a/Documentation/gpu/drm-mm.rst
+++ b/Documentation/gpu/drm-mm.rst
@@ -493,6 +493,18 @@ DRM Sync Objects
  .. kernel-doc:: drivers/gpu/drm/drm_syncobj.c
 :export:
  
+DRM Execution context

+=
+
+.. kernel-doc:: drivers/gpu/drm/drm_exec.c
+   :doc: Overview
+
+.. kernel-doc:: include/drm/drm_exec.h
+   :internal:
+
+.. kernel-doc:: drivers/gpu/drm/drm_exec.c
+   :export:
+
  GPU Scheduler
  =
  
diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig

index ba3fb04bb691..2dc81eb062eb 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -201,6 +201,12 @@ config DRM_TTM
  GPU memory types. Will be enabled automatically if a device driver
  uses it.
  
+config DRM_EXEC

+   tristate
+   depends on DRM
+   help
+ Execution context for command submissions
+
  config DRM_BUDDY
tristate
depends on DRM
diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
index a33257d2bc7f..9c6446eb3c83 100644
--- a/drivers/gpu/drm/Makefile
+++ b/drivers/gpu/drm/Makefile
@@ -78,6 +78,8 @@ obj-$(CONFIG_DRM_PANEL_ORIENTATION_QUIRKS) += 
drm_panel_orientation_quirks.o
  #
  # Memory-management helpers
  #
+#
+obj-$(CONFIG_DRM_EXEC) += drm_exec.o
  
  obj-$(CONFIG_DRM_BUDDY) += drm_buddy.o
  
diff --git a/drivers/gpu/drm/drm_exec.c b/drivers/gpu/drm/drm_exec.c

new file mode 100644
index ..18071bff20f4
--- /dev/null
+++ b/drivers/gpu/drm/drm_exec.c
@@ -0,0 +1,278 @@
+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
+
+#include 
+#include 
+#include 
+
+/**
+ * DOC: Overview
+ *
+ * This component mainly abstracts the retry loop necessary for locking
+ * multiple GEM objects while preparing hardware operations (e.g. command
+ * submissions, page table updates etc..).
+ *
+ * If a contention is detected while locking a GEM object the cleanup procedure
+ * unlocks all previously locked GEM objects and locks the contended one first
+ * before locking any further objects.
+ *
+ * After an object is locked fences slots can optionally be reserved on the
+ * dma_resv object inside the GEM object.
+ *
+ * A typical usage pattern should look like this::
+ *
+ * struct drm_gem_object *obj;
+ * struct drm_exec exec;
+ * unsigned long index;
+ * int ret;
+ *
+ * drm_exec_init(, true);
+ * drm_exec_while_not_all_locked() {
+ * ret = drm_exec_prepare_obj(, boA, 1);
+ * drm_exec_continue_on_contention();
+ * if (ret)
+ * goto error;
+ *
+ * ret = drm_exec_prepare_obj(, boB, 1);
+ * drm_exec_continue_on_contention();
+ * if (ret)
+ * goto error;
+ * }
+ *
+ * drm_exec_for_each_locked_object(, index, obj) {
+ * dma_resv_add_fence(obj->resv, fence, DMA_RESV_USAGE_READ);
+ * ...
+ * }
+ * drm_exec_fini();
+ *
+ * See struct dma_exec for more details.
+ */
+
+/* Dummy value used to initially enter the retry loop */
+#define DRM_EXEC_DUMMY (void*)~0
+
+/* Unlock all objects and drop references */
+static void drm_exec_unlock_all(struct drm_exec *exec)
+{
+   struct drm_gem_object *obj;
+   unsigned long index;
+
+   drm_exec_for_each_locked_object(exec, index, obj) {
+   dma_resv_unlock(obj->resv);
+   drm_gem_object_put(obj);
+   }
+
+   drm_gem_object_put(exec->prelocked);
+   exec->prelocked = NULL;
+}
+
+/**
+ * drm_exec_init - initialize a drm_exec object
+ * @exec: the drm_exec object to initialize
+ * @interruptible: if locks should be acquired interruptible
+ *
+ * Initialize the object and make sure that we can track locked objects.
+ */
+void drm_exec_init(struct drm_exec *exec, bool interruptible)
+{
+

Re: [PATCH] drm/amdgpu: move gfx9_cs_data definition

2023-05-25 Thread Alex Deucher

On Thu, May 25, 2023 at 4:35 PM Tom Rix  wrote:
>
> gcc with W=1 reports
> In file included from drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c:32:
> drivers/gpu/drm/amd/amdgpu/clearstate_gfx9.h:939:36: error:
>   ‘gfx9_cs_data’ defined but not used [-Werror=unused-const-variable=]
>   939 | static const struct cs_section_def gfx9_cs_data[] = {
>   |^~~~
>
> gfx9_cs_data is only used in gfx_v9_0.c, so move its definition there.
>
> Signed-off-by: Tom Rix 

Already fixed with:
https://patchwork.freedesktop.org/patch/539234/
which will show up in my tree momentarily.

Alex


> ---
>  drivers/gpu/drm/amd/amdgpu/clearstate_gfx9.h | 4 
>  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c| 5 +
>  2 files changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/clearstate_gfx9.h 
> b/drivers/gpu/drm/amd/amdgpu/clearstate_gfx9.h
> index 567a904804bc..6de4778789ed 100644
> --- a/drivers/gpu/drm/amd/amdgpu/clearstate_gfx9.h
> +++ b/drivers/gpu/drm/amd/amdgpu/clearstate_gfx9.h
> @@ -936,7 +936,3 @@ static const struct cs_extent_def 
> gfx9_SECT_CONTEXT_defs[] =
>  {gfx9_SECT_CONTEXT_def_8, 0xa2f5, 155 },
>  { 0, 0, 0 }
>  };
> -static const struct cs_section_def gfx9_cs_data[] = {
> -{ gfx9_SECT_CONTEXT_defs, SECT_CONTEXT },
> -{ 0, SECT_NONE }
> -};
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 8bf95a6b0767..c97a68a39d93 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -56,6 +56,11 @@
>  #include "asic_reg/pwr/pwr_10_0_sh_mask.h"
>  #include "asic_reg/gc/gc_9_0_default.h"
>
> +static const struct cs_section_def gfx9_cs_data[] = {
> +{ gfx9_SECT_CONTEXT_defs, SECT_CONTEXT },
> +{ 0, SECT_NONE }
> +};
> +
>  #define GFX9_NUM_GFX_RINGS 1
>  #define GFX9_NUM_SW_GFX_RINGS  2
>  #define GFX9_MEC_HPD_SIZE 4096
> --
> 2.27.0
>

[PATCH] drm/amdgpu: move gfx9_cs_data definition

gcc with W=1 reports
In file included from drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c:32:
drivers/gpu/drm/amd/amdgpu/clearstate_gfx9.h:939:36: error:
  ‘gfx9_cs_data’ defined but not used [-Werror=unused-const-variable=]
  939 | static const struct cs_section_def gfx9_cs_data[] = {
  |^~~~

gfx9_cs_data is only used in gfx_v9_0.c, so move its definition there.

Signed-off-by: Tom Rix 
---
 drivers/gpu/drm/amd/amdgpu/clearstate_gfx9.h | 4 
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c| 5 +
 2 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/clearstate_gfx9.h 
b/drivers/gpu/drm/amd/amdgpu/clearstate_gfx9.h
index 567a904804bc..6de4778789ed 100644
--- a/drivers/gpu/drm/amd/amdgpu/clearstate_gfx9.h
+++ b/drivers/gpu/drm/amd/amdgpu/clearstate_gfx9.h
@@ -936,7 +936,3 @@ static const struct cs_extent_def gfx9_SECT_CONTEXT_defs[] =
 {gfx9_SECT_CONTEXT_def_8, 0xa2f5, 155 },
 { 0, 0, 0 }
 };
-static const struct cs_section_def gfx9_cs_data[] = {
-{ gfx9_SECT_CONTEXT_defs, SECT_CONTEXT },
-{ 0, SECT_NONE }
-};
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 8bf95a6b0767..c97a68a39d93 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -56,6 +56,11 @@
 #include "asic_reg/pwr/pwr_10_0_sh_mask.h"
 #include "asic_reg/gc/gc_9_0_default.h"
 
+static const struct cs_section_def gfx9_cs_data[] = {
+{ gfx9_SECT_CONTEXT_defs, SECT_CONTEXT },
+{ 0, SECT_NONE }
+};
+
 #define GFX9_NUM_GFX_RINGS 1
 #define GFX9_NUM_SW_GFX_RINGS  2
 #define GFX9_MEC_HPD_SIZE 4096
-- 
2.27.0

Re: [PATCH v14 1/9] drm/display/dsc: Add flatness and initial scale value calculations

2023-05-25 Thread Marijn Suijten

On 2023-05-24 18:05:51, Jessica Zhang wrote:

> >> +/**
> >> + * drm_dsc_initial_scale_value() - Calculate the initial scale value for 
> >> the given DSC config
> >> + * @dsc: Pointer to DRM DSC config struct
> >> + *
> >> + * Return: Calculated initial scale value
> > 
> > Perhaps just drop Calculated from Return:?
> > 
> >> + */
> >> +u8 drm_dsc_initial_scale_value(const struct drm_dsc_config *dsc)
> >> +{
> >> +  return 8 * dsc->rc_model_size / (dsc->rc_model_size - 
> >> dsc->initial_offset);
> >> +}
> >> +EXPORT_SYMBOL(drm_dsc_initial_scale_value);
> >> +
> >> +/**
> >> + * drm_dsc_flatness_det_thresh() - Calculate the flatness_det_thresh for 
> >> the given DSC config
> > 
> > You've written out the word ("flatness det thresh" and "initial scale
> > value") entirely elsewhere, why the underscores in the doc comment here?
> > 
> > Instead we should have the full meaning here (and in the Return: below),
> > please correct me if I'm wrong but in VESA DSC v1.2a spec 6.8.5.1
> > Encoder Flatness Decision I think this variable means "flatness
> > determination threshold"?  If so, use that in the doc comment :)
> > 
> > (and drop the leading "the", so just "Calculate flatness determination
> > threshold for the given DSC config")
> > 
> >> + * @dsc: Pointer to DRM DSC config struct
> >> + *
> >> + * Return: Calculated flatness det thresh value
> > 
> > Nit: perhaps we can just drop "calculated" here?
> 
> 
> Hi Marijn,
> 
> Sure, I will make these changes if a v15 is necessary.
> 
> In the future, can we try to group comments on wording/grammar/patch 
> formatting with comments on the code itself?

Can you clarify what you mean?  v14 here is the first series including
this doc comment so there was no way for me to have reviewed this
earlier.  Code contents were already successfully reviewed many
revisions ago.

> I really appreciate your feedback and help in improving the 
> documentation around this feature, however I don't find it very 
> productive to have revisions where the only changes are on (in my 
> opinion) small wording details.

It is also down to you to have some patience and collect more review
from other maintainers and batch up changes, instead of spinning another
revision quickly after a review comment.

But this request can also be turned around: review and scan your own
series for simple inconsistencies before sending it to the lists, that
will surely make the time spent by reviewers much more "productive" as
well.
(Note that this goes hand in hand with the request to slow down
 consecutive revisions!)

And finally, as already said before: you can always decide to ignore my
review nits.  I am not a maintainer and don't have final say on whatever
is blocking for a patch to get merged.
But, when another revision is needed, the things I pointed out can at
least be incorporated, which is why they were shared in the first place.

Thanks for understanding.

- Marijn

Re: [PATCH] drm/i915: Fix clang -Wimplicit-fallthrough in intel_async_flip_check_hw()

2023-05-25 Thread Matthieu Baerts

Hi Nick,

On 24/05/2023 20:56, Nick Desaulniers wrote:
> On Wed, May 24, 2023 at 11:41 AM Nathan Chancellor  wrote:
>>
>> On Wed, May 24, 2023 at 11:32:32AM -0700, Nick Desaulniers wrote:
>>> On Wed, May 24, 2023 at 8:38 AM Nathan Chancellor  wrote:
>>>>
>>>> Clang warns:
>>>>
>>>>   drivers/gpu/drm/i915/display/intel_display.c:6012:3: error: unannotated 
>>>> fall-through between switch labels [-Werror,-Wimplicit-fallthrough]
>>>>   case I915_FORMAT_MOD_X_TILED:
>>>>   ^
>>>>   drivers/gpu/drm/i915/display/intel_display.c:6012:3: note: insert 
>>>> 'break;' to avoid fall-through
>>>>   case I915_FORMAT_MOD_X_TILED:
>>>>   ^
>>>>   break;
>>>>   1 error generated.
>>>>
>>>> Clang is a little more pedantic than GCC, which does not warn when
>>>> falling through to a case that is just break or return. Clang's version
>>>> is more in line with the kernel's own stance in deprecated.rst, which
>>>> states that all switch/case blocks must end in either break,
>>>> fallthrough, continue, goto, or return. Add the missing break to silence
>>>> the warning.
>>>>
>>>> Fixes: 937859485aef ("drm/i915: Support Async Flip on Linear buffers")
>>>> Reported-by: kernel test robot 
>>>> Closes: https://lore.kernel.org/202305241902.uvhtmoxa-...@intel.com/
>>>> Reported-by: Naresh Kamboju 
>>>> Closes: 
>>>> https://lore.kernel.org/CA+G9fYv68V3ewK0Qj-syQj7qX-hQr0H1MFL=qfnudoe_j2z...@mail.gmail.com/
>>>> Signed-off-by: Nathan Chancellor 
>>>
>>> Thanks for the patch! I've never seen the closes tag before, that's
>>> new to me. Can you tell me more about it?
>>
>> It is new to me (at least in the context of the kernel) as well. I only
>> used it over Link: because checkpatch.pl told me to:
>>
>> WARNING: Reported-by: should be immediately followed by Closes: with a URL 
>> to the report
>> #26:
>> Reported-by: kernel test robot 
>> Reported-by: Naresh Kamboju 
>>
>> WARNING: Reported-by: should be immediately followed by Closes: with a URL 
>> to the report
>> #27:
>> Reported-by: Naresh Kamboju 
>> Signed-off-by: Nathan Chancellor 
>>
>> It was Link: for a bit but commit 44c31888098a ("checkpatch: allow
>> Closes tags with links") changed it to Closes:. Looks odd to me but
>> whatever the linter says I suppose.
>>
>> Thanks for the review!
>>
>> Cheers,
>> Nathan
>>
>>> A few more tags
>>>
>>> Reported-by: Tom Rix 
>>> Link: https://lore.kernel.org/all/20230523125116.1669057-1-t...@redhat.com/
>>> Reviewed-by: Nick Desaulniers 
> 
> Ah then I guess my link tag should have been
> 
> Closes: https://lore.kernel.org/all/20230523125116.1669057-1-t...@redhat.com/
> 
> I hope the author of
> commit 44c31888098a ("checkpatch: allow Closes tags with links")
> has coordinated with the maintainer of b4, so that b4 recognizes Closes tags.
> b4 v0.12.2 does not pick up Closes tags.

I'm sorry for the troubles caused by this series, that was not the
intension.

When looking at modifying b4 to support the Closes tag, I realised the
Link tag from your previous message [1] was not taken as well. Was it
just me?

If no, I just sent patches for b4, see [2]. I hope it will help!

Cheers,
Matt

[1]
https://lore.kernel.org/all/CAKwvOd=jzjouunmd3rvc--goa0exphcf6chxua6w1kxjg2a...@mail.gmail.com/
[2]
https://lore.kernel.org/tools/20230525-closes-tags-v1-0-ed41b1773...@tessares.net/T/
-- 
Tessares | Belgium | Hybrid Access Solutions
www.tessares.net

Re: [PATCH 2/2] drm/amdgpu: Remove duplicate fdinfo fields

2023-05-25 Thread Alex Deucher

On Thu, May 25, 2023 at 11:52 AM Rob Clark  wrote:
>
> From: Rob Clark 
>
> Some of the fields that are handled by drm_show_fdinfo() crept back in
> when rebasing the patch.  Remove them again.
>
> Fixes: 376c25f8ca47 ("drm/amdgpu: Switch to fdinfo helper")
> Signed-off-by: Rob Clark 

Series is:
Reviewed-by: 

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c | 3 ---
>  1 file changed, 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c
> index 13d7413d4ca3..a93e5627901a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c
> @@ -80,23 +80,20 @@ void amdgpu_show_fdinfo(struct drm_printer *p, struct 
> drm_file *file)
>
> amdgpu_ctx_mgr_usage(>ctx_mgr, usage);
>
> /*
>  * **
>  * For text output format description please see drm-usage-stats.rst!
>  * **
>  */
>
> drm_printf(p, "pasid:\t%u\n", fpriv->vm.pasid);
> -   drm_printf(p, "drm-driver:\t%s\n", file->minor->dev->driver->name);
> -   drm_printf(p, "drm-pdev:\t%04x:%02x:%02x.%d\n", domain, bus, dev, fn);
> -   drm_printf(p, "drm-client-id:\t%Lu\n", vm->immediate.fence_context);
> drm_printf(p, "drm-memory-vram:\t%llu KiB\n", stats.vram/1024UL);
> drm_printf(p, "drm-memory-gtt: \t%llu KiB\n", stats.gtt/1024UL);
> drm_printf(p, "drm-memory-cpu: \t%llu KiB\n", stats.cpu/1024UL);
> drm_printf(p, "amd-memory-visible-vram:\t%llu KiB\n",
>stats.visible_vram/1024UL);
> drm_printf(p, "amd-evicted-vram:\t%llu KiB\n",
>stats.evicted_vram/1024UL);
> drm_printf(p, "amd-evicted-visible-vram:\t%llu KiB\n",
>stats.evicted_visible_vram/1024UL);
> drm_printf(p, "amd-requested-vram:\t%llu KiB\n",
> --
> 2.40.1
>

libGL error: glx: failed to create dri2 screen libGL / error: failed to load driver: nouveau

2023-05-25 Thread Mario Marietto

Hello.

I wrote this tutorial some time ago because I wanted that Blender was able
to recognize CUDA and the Nvidia driver directly within the linuxulator :

https://www.reddit.com/r/freebsd/comments/1118eae/how_to_install_the_nvidia_driver_5257801_cuda_12/

I was inspired by this tutorial :
https://gist.github.com/Mostly-BSD/4d3cacc0ee2f045ed8505005fd664c6e

someone found my tutorial and created this github :

https://github.com/spfcraze/Nvidia-Drivers-linux

He says that he created a Python script for updating Nvidia drivers on
CentOS 7 and Ubuntu. That's nice,but it can't work. Why ? please give a
look to an old post created by me some time ago and you will see :

https://www.reddit.com/r/freebsd/comments/11431bi/how_to_blacklist_the_nouveau_driver_within_the/

since the nouveau driver can't be blacklisted within the Linuxulator
because it's impossible to run "sudo update-initramfs -u" inside of it. For
this reason,I would ask if in your opinion the nouveau driver can be
blacklisted directly in FreeBSD or in some other way.

FreeBSD does not contain the nouveau kernel module so there is nothing to
blacklist.

>
https://www.reddit.com/r/freebsd/comments/11431bi/how_to_blacklist_the_nouveau_driver_within_the/

These libGL errors are from Mesa libGL, which is trying to use the
userspace part of nouveau (which is part of the Mesa project),
presumably based on Nvidia GPU's PCI ID being known to Mesa, despite there
being no nouveau kernel interface available.

Since I'm trying to use Nvidia's binary driver (the only one which works on
FreeBSD), Blender should have never loaded Mesa's libGL in the
first place - there is most likely a configuration problem here with
libglvnd, the component responsible for choosing the correct libGL
implementation.

When Blender fails to detect CUDA this has nothing to do with libGL and
absolutely nothing to do with nouveau.

Smplayer behaves the same as blender. I think this is a general behavior.
Check below what happens when I run it within the linuxulator :

root@marietto:/mnt/zroot2/zroot2 # chroot /compat/ubuntulunar /bin/bash

root@marietto:/# smplayer

QStandardPaths: error creating runtime directory '/var/run/user/1001' (No
such file or directory)
This is SMPlayer v. 22.7.0 (revision 10091) running on Linux
libGL error: glx: failed to create dri2 screen
*libGL error: failed to load driver: nouveau*

Can you figure out a method to do what I want to do ? If we are able to
"connect" the nVidia driver to the CG / graphic tool instead of the nouveau
one,a lot of cool features will be unfrozen on FreeBSD. For example we
could try to run Unreal Engine 5 within the linuxulator,Davinci
Resolve,Maya 3D,a lot of cool stuff will use the nVidia driver + CUDA and
it will work great. That's because unfortunately Nouveau does not support
CUDA.

Thanks.

--
Mario.

Re: [PATCH v14 3/9] drm/display/dsc: Add drm_dsc_get_bpp_int helper

2023-05-25 Thread Marijn Suijten

On 2023-05-24 15:38:23, Jessica Zhang wrote:

> >> +  WARN_ON_ONCE(vdsc_cfg->bits_per_pixel & 0xf);
> > 
> > You did not add linux/bug.h back, presumably because Dmitry added
> > another use of WARN_ON_ONCE to this file in a previous series and it
> > compiles fine as the definition trickles in via another header?
> 
> Yep, this compiles fine without any error or warning.

Yes it does, just curious (CC Dmitry) if that is expected/intended: I am
not familiar enough with the current header includes to say for sure.

Dmitry seemed to rely on it already being available in
https://git.kernel.org/torvalds/c/2b470e5531f57c1b9bfa129cca0ee17a2ecd2183
but that could have been an oversight?

- Marijn

Re: [PATCH v6] drm/msm/dp: enable HDP plugin/unplugged interrupts at hpd_enable/disable

2023-05-25 Thread Abhinav Kumar





On 5/23/2023 2:52 PM, Kuogee Hsieh wrote:

The internal_hpd flag is set to true by dp_bridge_hpd_enable() and set to
false by dp_bridge_hpd_disable() to handle GPIO pinmuxed into DP controller
case. HDP related interrupts can not be enabled until internal_hpd is set
to true. At current implementation dp_display_config_hpd() will initialize
DP host controller first followed by enabling HDP related interrupts if
internal_hpd was true at that time. Enable HDP related interrupts depends on
internal_hpd status may leave system with DP driver host is in running state
but without HDP related interrupts being enabled. This will prevent external
display from being detected. Eliminated this dependency by moving HDP related
interrupts enable/disable be done at dp_bridge_hpd_enable/disable() directly
regardless of internal_hpd status.

Changes in V3:
-- dp_catalog_ctrl_hpd_enable() and dp_catalog_ctrl_hpd_disable()
-- rewording ocmmit text

Changes in V4:
-- replace dp_display_config_hpd() with dp_display_host_start()
-- move enable_irq() at dp_display_host_start();

Changes in V5:
-- replace dp_display_host_start() with dp_display_host_init()

Changes in V6:
-- squash remove enable_irq() and disable_irq()

Fixes: cd198caddea7 ("drm/msm/dp: Rely on hpd_enable/disable callbacks")
Signed-off-by: Kuogee Hsieh 
---


Reviewed-by: Abhinav Kumar

Re: [PATCH] drm/amdkfd: remove unused function get_reserved_sdma_queues_bitmap

2023-05-25 Thread Nathan Chancellor

On Thu, May 25, 2023 at 04:07:59PM -0400, Tom Rix wrote:
> clang with W=1 reports
> drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_device_queue_manager.c:122:24: error:
>   unused function 'get_reserved_sdma_queues_bitmap' 
> [-Werror,-Wunused-function]
> static inline uint64_t get_reserved_sdma_queues_bitmap(struct 
> device_queue_manager *dqm)
>^
> This function is not used so remove it.
> 
> Signed-off-by: Tom Rix 

Caused by commit 09a95a85cf3e ("drm/amdkfd: Update SDMA queue management
for GFX9.4.3") it seems.

You can actually go a step farther and remove the
reserved_sdma_queues_bitmap member from 'struct kfd_device_info' because
it is now only assigned, never read.

$ git grep reserved_sdma_queues_bitmap next-20230525
next:20230525:drivers/gpu/drm/amd/amdkfd/kfd_device.c:
kfd->device_info.reserved_sdma_queues_bitmap = 0xFULL;
next:20230525:drivers/gpu/drm/amd/amdkfd/kfd_device.c:
kfd->device_info.reserved_sdma_queues_bitmap = 0x3ULL;
next:20230525:drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c:static 
inline uint64_t get_reserved_sdma_queues_bitmap(struct device_queue_manager 
*dqm)
next:20230525:drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c:return 
dqm->dev->kfd->device_info.reserved_sdma_queues_bitmap;
next:20230525:drivers/gpu/drm/amd/amdkfd/kfd_priv.h:uint64_t 
reserved_sdma_queues_bitmap;

> ---
>  drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 5 -
>  1 file changed, 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c 
> b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> index 493b4b66f180..2fbd0a96424f 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> @@ -119,11 +119,6 @@ unsigned int get_num_xgmi_sdma_queues(struct 
> device_queue_manager *dqm)
>   dqm->dev->kfd->device_info.num_sdma_queues_per_engine;
>  }
>  
> -static inline uint64_t get_reserved_sdma_queues_bitmap(struct 
> device_queue_manager *dqm)
> -{
> - return dqm->dev->kfd->device_info.reserved_sdma_queues_bitmap;
> -}
> -
>  static void init_sdma_bitmaps(struct device_queue_manager *dqm)
>  {
>   bitmap_zero(dqm->sdma_bitmap, KFD_MAX_SDMA_QUEUES);
> -- 
> 2.27.0
>

RE: [Intel-gfx] [PATCH v2 2/7] drm/i915: Expose crtc CTM property on ilk/snb



> -Original Message-
> From: Intel-gfx  On Behalf Of Ville 
> Syrjala
> Sent: Thursday, April 13, 2023 10:19 PM
> To: intel-...@lists.freedesktop.org
> Cc: dri-devel@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v2 2/7] drm/i915: Expose crtc CTM property on 
> ilk/snb
> 
> From: Ville Syrjälä 
> 
> The ilk/snb code is internally fully capable of handling the CTM property, so 
> expose
> it.
> 
> Note that we still choose not to expose DEGAMMA_LUT though.
> The hardware is capable if degamma or gamma, but not both similtanously due to

Nit: Typo in "simultaneously"

Looks Good to me.
Reviewed-by: Uma Shankar 

> lack of the split gamma mode. Exposing both LUTs might encourage userspace to 
> try
> enabling both at the same time.
> 
> Signed-off-by: Ville Syrjälä 
> ---
>  drivers/gpu/drm/i915/display/intel_color.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c
> b/drivers/gpu/drm/i915/display/intel_color.c
> index 07f1afe1d406..4fc16cac052d 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -3473,7 +3473,7 @@ void intel_color_crtc_init(struct intel_crtc *crtc)
> 
>   gamma_lut_size = INTEL_INFO(i915)->display.color.gamma_lut_size;
>   degamma_lut_size = INTEL_INFO(i915)->display.color.degamma_lut_size;
> - has_ctm = degamma_lut_size != 0;
> + has_ctm = DISPLAY_VER(i915) >= 5 && !IS_VALLEYVIEW(i915);
> 
>   /*
>* "DPALETTE_A: NOTE: The 8-bit (non-10-bit) mode is the
> --
> 2.39.2

Re: [PATCH] drm/amd/amdgpu: Fix up locking etc in amdgpu_debugfs_gprwave_ioctl()

2023-05-25 Thread Alex Deucher

Applied.  Thanks!

Alex

On Thu, May 25, 2023 at 4:05 AM Dan Carpenter  wrote:
>
> There are two bugs here.
> 1) Drop the lock if copy_from_user() fails.
> 2) If the copy fails then the correct error code is -EFAULT instead of
>-EINVAL.
>
> I also broke up the long line and changed "sizeof rd->id" to
> "sizeof(rd->id)".
>
> Fixes: 164fb2940933 ("drm/amd/amdgpu: Update debugfs for XCC support (v3)")
> Signed-off-by: Dan Carpenter 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 9 +
>  1 file changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
> index c657bed350ac..56e89e76ff17 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
> @@ -478,15 +478,16 @@ static ssize_t amdgpu_debugfs_gprwave_read(struct file 
> *f, char __user *buf, siz
>  static long amdgpu_debugfs_gprwave_ioctl(struct file *f, unsigned int cmd, 
> unsigned long data)
>  {
> struct amdgpu_debugfs_gprwave_data *rd = f->private_data;
> -   int r;
> +   int r = 0;
>
> mutex_lock(>lock);
>
> switch (cmd) {
> case AMDGPU_DEBUGFS_GPRWAVE_IOC_SET_STATE:
> -   r = copy_from_user(>id, (struct 
> amdgpu_debugfs_gprwave_iocdata *)data, sizeof rd->id);
> -   if (r)
> -   return r ? -EINVAL : 0;
> +   if (copy_from_user(>id,
> +  (struct amdgpu_debugfs_gprwave_iocdata 
> *)data,
> +  sizeof(rd->id)))
> +   r = -EFAULT;
> goto done;
> default:
> r = -EINVAL;
> --
> 2.39.2
>

[PATCH] drm/amdkfd: remove unused function get_reserved_sdma_queues_bitmap

clang with W=1 reports
drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_device_queue_manager.c:122:24: error:
  unused function 'get_reserved_sdma_queues_bitmap' [-Werror,-Wunused-function]
static inline uint64_t get_reserved_sdma_queues_bitmap(struct 
device_queue_manager *dqm)
   ^
This function is not used so remove it.

Signed-off-by: Tom Rix 
---
 drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 5 -
 1 file changed, 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
index 493b4b66f180..2fbd0a96424f 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
@@ -119,11 +119,6 @@ unsigned int get_num_xgmi_sdma_queues(struct 
device_queue_manager *dqm)
dqm->dev->kfd->device_info.num_sdma_queues_per_engine;
 }
 
-static inline uint64_t get_reserved_sdma_queues_bitmap(struct 
device_queue_manager *dqm)
-{
-   return dqm->dev->kfd->device_info.reserved_sdma_queues_bitmap;
-}
-
 static void init_sdma_bitmaps(struct device_queue_manager *dqm)
 {
bitmap_zero(dqm->sdma_bitmap, KFD_MAX_SDMA_QUEUES);
-- 
2.27.0

Re: [Intel-gfx] [PATCH v2 8/8] drm/i915/huc: define HuC FW version for MTL

2023-05-25 Thread John Harrison


On 4/28/2023 11:58, Daniele Ceraolo Spurio wrote:

Follow the same logic as DG2, so just a meu binary with no version number.

Signed-off-by: Daniele Ceraolo Spurio 
Cc: Alan Previn 

Reviewed-by: John Harrison 


---
  drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 1 +
  1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c 
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index 3338dd45e78b..796f54a62eef 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -102,6 +102,7 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw,
fw_def(SKYLAKE,  0, guc_mmp(skl,  70, 1, 1))
  
  #define INTEL_HUC_FIRMWARE_DEFS(fw_def, huc_raw, huc_mmp, huc_gsc) \

+   fw_def(METEORLAKE,   0, huc_gsc(mtl)) \
fw_def(DG2,  0, huc_gsc(dg2)) \
fw_def(ALDERLAKE_P,  0, huc_raw(tgl)) \
fw_def(ALDERLAKE_P,  0, huc_mmp(tgl,  7, 9, 3)) \

Re: [PATCH v2 7/8] drm/i915/mtl/huc: Use the media gt for the HuC getparam

2023-05-25 Thread John Harrison


On 4/28/2023 11:58, Daniele Ceraolo Spurio wrote:

On MTL, for obvious reasons, HuC is only available on the media tile.
We already disable SW support for HuC on the root gt due to the
absence of VCS engines, but we also need to update the getparam to point
to the HuC struct in the media GT.

Signed-off-by: Daniele Ceraolo Spurio 
Cc: John Harrison 
---
  drivers/gpu/drm/i915/i915_getparam.c | 6 +-
  1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_getparam.c 
b/drivers/gpu/drm/i915/i915_getparam.c
index 2238e096c957..7aa47550e4f2 100644
--- a/drivers/gpu/drm/i915/i915_getparam.c
+++ b/drivers/gpu/drm/i915/i915_getparam.c
@@ -98,7 +98,11 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data,
value = sseu->min_eu_in_pool;
break;
case I915_PARAM_HUC_STATUS:
-   value = intel_huc_check_status(_gt(i915)->uc.huc);
+   /* On platform with a media GT, the HuC is on that GT */
+   if (i915->media_gt)
+   value = intel_huc_check_status(>media_gt->uc.huc);
+   else
+   value = intel_huc_check_status(_gt(i915)->uc.huc);
I assume the intention is to ignore multi-tile complications? As in, all 
tiles are guaranteed to be the same so there is no point looking beyond 
the root tile?


Reviewed-by: John Harrison 



if (value < 0)
return value;
break;

Re: [PATCH v6] drm/msm/dp: enable HDP plugin/unplugged interrupts at hpd_enable/disable

2023-05-25 Thread Bjorn Andersson

On Tue, May 23, 2023 at 02:52:36PM -0700, Kuogee Hsieh wrote:
> The internal_hpd flag is set to true by dp_bridge_hpd_enable() and set to
> false by dp_bridge_hpd_disable() to handle GPIO pinmuxed into DP controller
> case. HDP related interrupts can not be enabled until internal_hpd is set
> to true. At current implementation dp_display_config_hpd() will initialize
> DP host controller first followed by enabling HDP related interrupts if
> internal_hpd was true at that time. Enable HDP related interrupts depends on
> internal_hpd status may leave system with DP driver host is in running state
> but without HDP related interrupts being enabled. This will prevent external
> display from being detected. Eliminated this dependency by moving HDP related
> interrupts enable/disable be done at dp_bridge_hpd_enable/disable() directly
> regardless of internal_hpd status.
> 
> Changes in V3:
> -- dp_catalog_ctrl_hpd_enable() and dp_catalog_ctrl_hpd_disable()
> -- rewording ocmmit text
> 
> Changes in V4:
> -- replace dp_display_config_hpd() with dp_display_host_start()
> -- move enable_irq() at dp_display_host_start();
> 
> Changes in V5:
> -- replace dp_display_host_start() with dp_display_host_init()
> 
> Changes in V6:
> -- squash remove enable_irq() and disable_irq()
> 
> Fixes: cd198caddea7 ("drm/msm/dp: Rely on hpd_enable/disable callbacks")

Reviewed-by: Bjorn Andersson 
Tested-by: Bjorn Andersson 

Thank you Kuogee,
Bjorn

> Signed-off-by: Kuogee Hsieh 
> ---
>  drivers/gpu/drm/msm/dp/dp_catalog.c | 15 +++-
>  drivers/gpu/drm/msm/dp/dp_catalog.h |  3 +-
>  drivers/gpu/drm/msm/dp/dp_display.c | 71 
> ++---
>  3 files changed, 35 insertions(+), 54 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c 
> b/drivers/gpu/drm/msm/dp/dp_catalog.c
> index 7a8cf1c..5142aeb 100644
> --- a/drivers/gpu/drm/msm/dp/dp_catalog.c
> +++ b/drivers/gpu/drm/msm/dp/dp_catalog.c
> @@ -620,7 +620,7 @@ void dp_catalog_hpd_config_intr(struct dp_catalog 
> *dp_catalog,
>   config & DP_DP_HPD_INT_MASK);
>  }
>  
> -void dp_catalog_ctrl_hpd_config(struct dp_catalog *dp_catalog)
> +void dp_catalog_ctrl_hpd_enable(struct dp_catalog *dp_catalog)
>  {
>   struct dp_catalog_private *catalog = container_of(dp_catalog,
>   struct dp_catalog_private, dp_catalog);
> @@ -635,6 +635,19 @@ void dp_catalog_ctrl_hpd_config(struct dp_catalog 
> *dp_catalog)
>   dp_write_aux(catalog, REG_DP_DP_HPD_CTRL, DP_DP_HPD_CTRL_HPD_EN);
>  }
>  
> +void dp_catalog_ctrl_hpd_disable(struct dp_catalog *dp_catalog)
> +{
> + struct dp_catalog_private *catalog = container_of(dp_catalog,
> + struct dp_catalog_private, dp_catalog);
> +
> + u32 reftimer = dp_read_aux(catalog, REG_DP_DP_HPD_REFTIMER);
> +
> + reftimer &= ~DP_DP_HPD_REFTIMER_ENABLE;
> + dp_write_aux(catalog, REG_DP_DP_HPD_REFTIMER, reftimer);
> +
> + dp_write_aux(catalog, REG_DP_DP_HPD_CTRL, 0);
> +}
> +
>  static void dp_catalog_enable_sdp(struct dp_catalog_private *catalog)
>  {
>   /* trigger sdp */
> diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.h 
> b/drivers/gpu/drm/msm/dp/dp_catalog.h
> index 82376a2..38786e8 100644
> --- a/drivers/gpu/drm/msm/dp/dp_catalog.h
> +++ b/drivers/gpu/drm/msm/dp/dp_catalog.h
> @@ -104,7 +104,8 @@ bool dp_catalog_ctrl_mainlink_ready(struct dp_catalog 
> *dp_catalog);
>  void dp_catalog_ctrl_enable_irq(struct dp_catalog *dp_catalog, bool enable);
>  void dp_catalog_hpd_config_intr(struct dp_catalog *dp_catalog,
>   u32 intr_mask, bool en);
> -void dp_catalog_ctrl_hpd_config(struct dp_catalog *dp_catalog);
> +void dp_catalog_ctrl_hpd_enable(struct dp_catalog *dp_catalog);
> +void dp_catalog_ctrl_hpd_disable(struct dp_catalog *dp_catalog);
>  void dp_catalog_ctrl_config_psr(struct dp_catalog *dp_catalog);
>  void dp_catalog_ctrl_set_psr(struct dp_catalog *dp_catalog, bool enter);
>  u32 dp_catalog_link_is_connected(struct dp_catalog *dp_catalog);
> diff --git a/drivers/gpu/drm/msm/dp/dp_display.c 
> b/drivers/gpu/drm/msm/dp/dp_display.c
> index 3e13acdf..cb805cf 100644
> --- a/drivers/gpu/drm/msm/dp/dp_display.c
> +++ b/drivers/gpu/drm/msm/dp/dp_display.c
> @@ -615,12 +615,6 @@ static int dp_hpd_plug_handle(struct dp_display_private 
> *dp, u32 data)
>   dp->hpd_state = ST_MAINLINK_READY;
>   }
>  
> - /* enable HDP irq_hpd/replug interrupt */
> - if (dp->dp_display.internal_hpd)
> - dp_catalog_hpd_config_intr(dp->catalog,
> -DP_DP_IRQ_HPD_INT_MASK | 
> DP_DP_HPD_REPLUG_INT_MASK,
> -true);
> -
>   drm_dbg_dp(dp->drm_dev, "After, type=%d hpd_state=%d\n",
>   dp->dp_display.connector_type, state);
>   mutex_unlock(>event_mutex);
> @@ -658,12 +652,6 @@ static int dp_hpd_unplug_handle(struct 
> dp_display_private *dp, u32 data)
>

Re: [1/4] fbdev: imsttfb: Fix error handling in init_imstt()

2023-05-25 Thread Markus Elfring

>> Can it be helpful to distinguish involved error codes better?
>
> No.

I find such a feedback surprising.

May the error code be preserved from a failed call of the function 
“fb_alloc_cmap”?

Regards,
Markus

[PATCH v4 13/13] drm/amd/display: Refactor avi_info_frame colorimetry determination

From: Joshua Ashton 

Replace the messy two if-else chains here that were
on the same value with a switch on the enum.

Signed-off-by: Joshua Ashton 
Signed-off-by: Harry Wentland 
Cc: Pekka Paalanen 
Cc: Sebastian Wick 
Cc: vitaly.pros...@amd.com
Cc: Joshua Ashton 
Cc: Simon Ser 
Cc: Melissa Wen 
Cc: dri-devel@lists.freedesktop.org
Cc: amd-...@lists.freedesktop.org
Reviewed-by: Harry Wentland 
---
 .../gpu/drm/amd/display/dc/core/dc_resource.c | 28 +++
 1 file changed, 17 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 7e1e5532f88f..ac3062abec51 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -3015,23 +3015,29 @@ static void set_avi_info_frame(
hdmi_info.bits.S0_S1 = scan_type;
 
/* C0, C1 : Colorimetry */
-   if (color_space == COLOR_SPACE_YCBCR709 ||
-   color_space == COLOR_SPACE_YCBCR709_LIMITED)
+   switch (color_space) {
+   case COLOR_SPACE_YCBCR709:
+   case COLOR_SPACE_YCBCR709_LIMITED:
hdmi_info.bits.C0_C1 = COLORIMETRY_ITU709;
-   else if (color_space == COLOR_SPACE_YCBCR601 ||
-   color_space == COLOR_SPACE_YCBCR601_LIMITED)
+   break;
+   case COLOR_SPACE_YCBCR601:
+   case COLOR_SPACE_YCBCR601_LIMITED:
hdmi_info.bits.C0_C1 = COLORIMETRY_ITU601;
-   else {
-   hdmi_info.bits.C0_C1 = COLORIMETRY_NO_DATA;
-   }
-   if (color_space == COLOR_SPACE_2020_RGB_FULLRANGE ||
-   color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE ||
-   color_space == COLOR_SPACE_2020_YCBCR) {
+   break;
+   case COLOR_SPACE_2020_RGB_FULLRANGE:
+   case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
+   case COLOR_SPACE_2020_YCBCR:
hdmi_info.bits.EC0_EC2 = COLORIMETRYEX_BT2020RGBYCBCR;
hdmi_info.bits.C0_C1   = COLORIMETRY_EXTENDED;
-   } else if (color_space == COLOR_SPACE_ADOBERGB) {
+   break;
+   case COLOR_SPACE_ADOBERGB:
hdmi_info.bits.EC0_EC2 = COLORIMETRYEX_ADOBERGB;
hdmi_info.bits.C0_C1   = COLORIMETRY_EXTENDED;
+   break;
+   case COLOR_SPACE_SRGB:
+   default:
+   hdmi_info.bits.C0_C1 = COLORIMETRY_NO_DATA;
+   break;
}
 
if (pixel_encoding && color_space == COLOR_SPACE_2020_YCBCR &&
-- 
2.40.1

[PATCH v4 08/13] drm/amd/display: Register Colorspace property for DP and HDMI

We want compositors to be able to set the output
colorspace on DP and HDMI outputs, based on the
caps reported from the receiver via EDID.

Signed-off-by: Harry Wentland 
Cc: Pekka Paalanen 
Cc: Sebastian Wick 
Cc: vitaly.pros...@amd.com
Cc: Joshua Ashton 
Cc: Simon Ser 
Cc: Ville Syrjälä 
Cc: Melissa Wen 
Cc: dri-devel@lists.freedesktop.org
Cc: amd-...@lists.freedesktop.org
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 15 +++
 1 file changed, 15 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index ca093396d1ac..dc99a8ffac70 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -7238,6 +7238,12 @@ static int amdgpu_dm_connector_get_modes(struct 
drm_connector *connector)
return amdgpu_dm_connector->num_modes;
 }
 
+static const u32 supported_colorspaces =
+   BIT(DRM_MODE_COLORIMETRY_BT709_YCC) |
+   BIT(DRM_MODE_COLORIMETRY_OPRGB) |
+   BIT(DRM_MODE_COLORIMETRY_BT2020_RGB) |
+   BIT(DRM_MODE_COLORIMETRY_BT2020_YCC);
+
 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
 struct amdgpu_dm_connector *aconnector,
 int connector_type,
@@ -7318,6 +7324,15 @@ void amdgpu_dm_connector_init_helper(struct 
amdgpu_display_manager *dm,
adev->mode_info.abm_level_property, 0);
}
 
+   if (connector_type == DRM_MODE_CONNECTOR_HDMIA) {
+   if 
(!drm_mode_create_hdmi_colorspace_property(>base, 
supported_colorspaces))
+   
drm_connector_attach_colorspace_property(>base);
+   } else if (connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
+  connector_type == DRM_MODE_CONNECTOR_eDP) {
+   if (!drm_mode_create_dp_colorspace_property(>base, 
supported_colorspaces))
+   
drm_connector_attach_colorspace_property(>base);
+   }
+
if (connector_type == DRM_MODE_CONNECTOR_HDMIA ||
connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
connector_type == DRM_MODE_CONNECTOR_eDP) {
-- 
2.40.1

[PATCH v4 12/13] drm/amd/display: Add debugfs for testing output colorspace

In order to IGT test colorspace we'll want to print
the currently enabled colorspace on a stream. We add
a new debugfs to do so, using the same scheme as
current bpc reporting.

This might also come in handy when debugging display
issues.

v4:
- Fix function doc comment
- Fix sRGB debug print

Signed-off-by: Harry Wentland 
Cc: Pekka Paalanen 
Cc: Sebastian Wick 
Cc: vitaly.pros...@amd.com
Cc: Joshua Ashton 
Cc: Simon Ser 
Cc: Melissa Wen 
Cc: dri-devel@lists.freedesktop.org
Cc: amd-...@lists.freedesktop.org
---
 .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 57 +++
 1 file changed, 57 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
index 827fcb4fb3b3..9a885e2effec 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
@@ -906,6 +906,61 @@ static int amdgpu_current_bpc_show(struct seq_file *m, 
void *data)
 }
 DEFINE_SHOW_ATTRIBUTE(amdgpu_current_bpc);
 
+/*
+ * Returns the current colorspace for the crtc.
+ * Example usage: cat /sys/kernel/debug/dri/0/crtc-0/amdgpu_current_colorspace
+ */
+static int amdgpu_current_colorspace_show(struct seq_file *m, void *data)
+{
+   struct drm_crtc *crtc = m->private;
+   struct drm_device *dev = crtc->dev;
+   struct dm_crtc_state *dm_crtc_state = NULL;
+   int res = -ENODEV;
+
+   mutex_lock(>mode_config.mutex);
+   drm_modeset_lock(>mutex, NULL);
+   if (crtc->state == NULL)
+   goto unlock;
+
+   dm_crtc_state = to_dm_crtc_state(crtc->state);
+   if (dm_crtc_state->stream == NULL)
+   goto unlock;
+
+   switch (dm_crtc_state->stream->output_color_space) {
+   case COLOR_SPACE_SRGB:
+   seq_printf(m, "sRGB");
+   break;
+   case COLOR_SPACE_YCBCR601:
+   case COLOR_SPACE_YCBCR601_LIMITED:
+   seq_printf(m, "BT601_YCC");
+   break;
+   case COLOR_SPACE_YCBCR709:
+   case COLOR_SPACE_YCBCR709_LIMITED:
+   seq_printf(m, "BT709_YCC");
+   break;
+   case COLOR_SPACE_ADOBERGB:
+   seq_printf(m, "opRGB");
+   break;
+   case COLOR_SPACE_2020_RGB_FULLRANGE:
+   seq_printf(m, "BT2020_RGB");
+   break;
+   case COLOR_SPACE_2020_YCBCR:
+   seq_printf(m, "BT2020_YCC");
+   break;
+   default:
+   goto unlock;
+   }
+   res = 0;
+
+unlock:
+   drm_modeset_unlock(>mutex);
+   mutex_unlock(>mode_config.mutex);
+
+   return res;
+}
+DEFINE_SHOW_ATTRIBUTE(amdgpu_current_colorspace);
+
+
 /*
  * Example usage:
  * Disable dsc passthrough, i.e.,: have dsc decoding at converver, not 
external RX
@@ -3246,6 +3301,8 @@ void crtc_debugfs_init(struct drm_crtc *crtc)
 #endif
debugfs_create_file("amdgpu_current_bpc", 0644, crtc->debugfs_entry,
crtc, _current_bpc_fops);
+   debugfs_create_file("amdgpu_current_colorspace", 0644, 
crtc->debugfs_entry,
+   crtc, _current_colorspace_fops);
 }
 
 /*
-- 
2.40.1

[PATCH v4 10/13] drm/amd/display: Send correct DP colorspace infopacket

Look at connector->colorimetry to determine output colorspace.

We don't want to impact current SDR behavior, so
DRM_MODE_COLORIMETRY_DEFAULT preserves current behavior.

Also add support to explicitly set BT601 and BT709.

v4:
- Roll support for BT709 and BT601 into this patch
- Add default case to avoid warnings for unhandled
  enum values

Signed-off-by: Harry Wentland 
Cc: Pekka Paalanen 
Cc: Sebastian Wick 
Cc: vitaly.pros...@amd.com
Cc: Joshua Ashton 
Cc: Simon Ser 
Cc: Melissa Wen 
Cc: dri-devel@lists.freedesktop.org
Cc: amd-...@lists.freedesktop.org
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 48 ---
 1 file changed, 31 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 5c290e6aac46..a8de26f09806 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -5330,21 +5330,44 @@ get_aspect_ratio(const struct drm_display_mode *mode_in)
 }
 
 static enum dc_color_space
-get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing)
+get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing,
+  const struct drm_connector_state *connector_state)
 {
enum dc_color_space color_space = COLOR_SPACE_SRGB;
 
-   switch (dc_crtc_timing->pixel_encoding) {
-   case PIXEL_ENCODING_YCBCR422:
-   case PIXEL_ENCODING_YCBCR444:
-   case PIXEL_ENCODING_YCBCR420:
-   {
+   switch (connector_state->colorspace) {
+   case DRM_MODE_COLORIMETRY_BT601_YCC:
+   if (dc_crtc_timing->flags.Y_ONLY)
+   color_space = COLOR_SPACE_YCBCR601_LIMITED;
+   else
+   color_space = COLOR_SPACE_YCBCR601;
+   break;
+   case DRM_MODE_COLORIMETRY_BT709_YCC:
+   if (dc_crtc_timing->flags.Y_ONLY)
+   color_space = COLOR_SPACE_YCBCR709_LIMITED;
+   else
+   color_space = COLOR_SPACE_YCBCR709;
+   break;
+   case DRM_MODE_COLORIMETRY_OPRGB:
+   color_space = COLOR_SPACE_ADOBERGB;
+   break;
+   case DRM_MODE_COLORIMETRY_BT2020_RGB:
+   case DRM_MODE_COLORIMETRY_BT2020_YCC:
+   if (dc_crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB)
+   color_space = COLOR_SPACE_2020_RGB_FULLRANGE;
+   else
+   color_space = COLOR_SPACE_2020_YCBCR;
+   break;
+   case DRM_MODE_COLORIMETRY_DEFAULT: // ITU601
+   default:
+   if (dc_crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB) {
+   color_space = COLOR_SPACE_SRGB;
/*
 * 27030khz is the separation point between HDTV and SDTV
 * according to HDMI spec, we use YCbCr709 and YCbCr601
 * respectively
 */
-   if (dc_crtc_timing->pix_clk_100hz > 270300) {
+   } else if (dc_crtc_timing->pix_clk_100hz > 270300) {
if (dc_crtc_timing->flags.Y_ONLY)
color_space =
COLOR_SPACE_YCBCR709_LIMITED;
@@ -5357,15 +5380,6 @@ get_output_color_space(const struct dc_crtc_timing 
*dc_crtc_timing)
else
color_space = COLOR_SPACE_YCBCR601;
}
-
-   }
-   break;
-   case PIXEL_ENCODING_RGB:
-   color_space = COLOR_SPACE_SRGB;
-   break;
-
-   default:
-   WARN_ON(1);
break;
}
 
@@ -5504,7 +5518,7 @@ static void fill_stream_properties_from_drm_display_mode(
}
}
 
-   stream->output_color_space = get_output_color_space(timing_out);
+   stream->output_color_space = get_output_color_space(timing_out, 
connector_state);
 }
 
 static void fill_audio_info(struct audio_info *audio_info,
-- 
2.40.1

[PATCH v4 04/13] drm/connector: Use common colorspace_names array

We an use bitfields to track the support ones for HDMI
and DP. This allows us to print colorspaces in a consistent
manner without needing to know whether we're dealing with
DP or HDMI.

v4:
- Rename _MAX to _COUNT and leave comment to indicate
  it's not a valid value
- Fix misplaced function doc

Signed-off-by: Harry Wentland 
Cc: Pekka Paalanen 
Cc: Sebastian Wick 
Cc: vitaly.pros...@amd.com
Cc: Uma Shankar 
Cc: Ville Syrjälä 
Cc: Joshua Ashton 
Cc: Jani Nikula 
Cc: Simon Ser 
Cc: Ville Syrjälä 
Cc: Melissa Wen 
Cc: dri-devel@lists.freedesktop.org
Cc: amd-...@lists.freedesktop.org
---
 drivers/gpu/drm/drm_connector.c | 125 ++--
 include/drm/drm_connector.h |   2 +
 2 files changed, 74 insertions(+), 53 deletions(-)

diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
index 9c087d6f5691..8d24a5da4076 100644
--- a/drivers/gpu/drm/drm_connector.c
+++ b/drivers/gpu/drm/drm_connector.c
@@ -1016,64 +1016,70 @@ static const struct drm_prop_enum_list 
drm_dp_subconnector_enum_list[] = {
 DRM_ENUM_NAME_FN(drm_get_dp_subconnector_name,
 drm_dp_subconnector_enum_list)
 
-static const struct drm_prop_enum_list hdmi_colorspaces[] = {
+
+static const char * const colorspace_names[] = {
/* For Default case, driver will set the colorspace */
-   { DRM_MODE_COLORIMETRY_DEFAULT, "Default" },
+   [DRM_MODE_COLORIMETRY_DEFAULT] = "Default",
/* Standard Definition Colorimetry based on CEA 861 */
-   { DRM_MODE_COLORIMETRY_SMPTE_170M_YCC, "SMPTE_170M_YCC" },
-   { DRM_MODE_COLORIMETRY_BT709_YCC, "BT709_YCC" },
+   [DRM_MODE_COLORIMETRY_SMPTE_170M_YCC] = "SMPTE_170M_YCC",
+   [DRM_MODE_COLORIMETRY_BT709_YCC] = "BT709_YCC",
/* Standard Definition Colorimetry based on IEC 61966-2-4 */
-   { DRM_MODE_COLORIMETRY_XVYCC_601, "XVYCC_601" },
+   [DRM_MODE_COLORIMETRY_XVYCC_601] = "XVYCC_601",
/* High Definition Colorimetry based on IEC 61966-2-4 */
-   { DRM_MODE_COLORIMETRY_XVYCC_709, "XVYCC_709" },
+   [DRM_MODE_COLORIMETRY_XVYCC_709] = "XVYCC_709",
/* Colorimetry based on IEC 61966-2-1/Amendment 1 */
-   { DRM_MODE_COLORIMETRY_SYCC_601, "SYCC_601" },
+   [DRM_MODE_COLORIMETRY_SYCC_601] = "SYCC_601",
/* Colorimetry based on IEC 61966-2-5 [33] */
-   { DRM_MODE_COLORIMETRY_OPYCC_601, "opYCC_601" },
+   [DRM_MODE_COLORIMETRY_OPYCC_601] = "opYCC_601",
/* Colorimetry based on IEC 61966-2-5 */
-   { DRM_MODE_COLORIMETRY_OPRGB, "opRGB" },
+   [DRM_MODE_COLORIMETRY_OPRGB] = "opRGB",
/* Colorimetry based on ITU-R BT.2020 */
-   { DRM_MODE_COLORIMETRY_BT2020_CYCC, "BT2020_CYCC" },
+   [DRM_MODE_COLORIMETRY_BT2020_CYCC] = "BT2020_CYCC",
/* Colorimetry based on ITU-R BT.2020 */
-   { DRM_MODE_COLORIMETRY_BT2020_RGB, "BT2020_RGB" },
+   [DRM_MODE_COLORIMETRY_BT2020_RGB] = "BT2020_RGB",
/* Colorimetry based on ITU-R BT.2020 */
-   { DRM_MODE_COLORIMETRY_BT2020_YCC, "BT2020_YCC" },
+   [DRM_MODE_COLORIMETRY_BT2020_YCC] = "BT2020_YCC",
/* Added as part of Additional Colorimetry Extension in 861.G */
-   { DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65, "DCI-P3_RGB_D65" },
-   { DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER, "DCI-P3_RGB_Theater" },
+   [DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65] = "DCI-P3_RGB_D65",
+   [DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER] = "DCI-P3_RGB_Theater",
+   [DRM_MODE_COLORIMETRY_RGB_WIDE_FIXED] = "RGB_WIDE_FIXED",
+   /* Colorimetry based on scRGB (IEC 61966-2-2) */
+   [DRM_MODE_COLORIMETRY_RGB_WIDE_FLOAT] = "RGB_WIDE_FLOAT",
+   [DRM_MODE_COLORIMETRY_BT601_YCC] = "BT601_YCC",
 };
 
+static const u32 hdmi_colorspaces =
+   BIT(DRM_MODE_COLORIMETRY_SMPTE_170M_YCC) |
+   BIT(DRM_MODE_COLORIMETRY_BT709_YCC) |
+   BIT(DRM_MODE_COLORIMETRY_XVYCC_601) |
+   BIT(DRM_MODE_COLORIMETRY_XVYCC_709) |
+   BIT(DRM_MODE_COLORIMETRY_SYCC_601) |
+   BIT(DRM_MODE_COLORIMETRY_OPYCC_601) |
+   BIT(DRM_MODE_COLORIMETRY_OPRGB) |
+   BIT(DRM_MODE_COLORIMETRY_BT2020_CYCC) |
+   BIT(DRM_MODE_COLORIMETRY_BT2020_RGB) |
+   BIT(DRM_MODE_COLORIMETRY_BT2020_YCC) |
+   BIT(DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65) |
+   BIT(DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER);
+
 /*
  * As per DP 1.4a spec, 2.2.5.7.5 VSC SDP Payload for Pixel 
Encoding/Colorimetry
  * Format Table 2-120
  */
-static const struct drm_prop_enum_list dp_colorspaces[] = {
-   /* For Default case, driver will set the colorspace */
-   { DRM_MODE_COLORIMETRY_DEFAULT, "Default" },
-   { DRM_MODE_COLORIMETRY_RGB_WIDE_FIXED, "RGB_Wide_Gamut_Fixed_Point" },
-   /* Colorimetry based on scRGB (IEC 61966-2-2) */
-   { DRM_MODE_COLORIMETRY_RGB_WIDE_FLOAT, "RGB_Wide_Gamut_Floating_Point" 
},
-   /* Colorimetry based on IEC 61966-2-5 */
-   { DRM_MODE_COLORIMETRY_OPRGB, "opRGB" },
-   /* Colorimetry based on SMPTE RP 431-2 */
-   {

[PATCH v4 09/13] drm/amd/display: Signal mode_changed if colorspace changed

We need to signal mode_changed to make sure we update the output
colorspace.

v2: No need to call drm_hdmi_avi_infoframe_colorimetry as DC does its
own infoframe packing.

Signed-off-by: Harry Wentland 
Cc: Pekka Paalanen 
Cc: Sebastian Wick 
Cc: vitaly.pros...@amd.com
Cc: Uma Shankar 
Cc: Joshua Ashton 
Cc: Simon Ser 
Cc: Melissa Wen 
Cc: dri-devel@lists.freedesktop.org
Cc: amd-...@lists.freedesktop.org
Reviewed-by: Leo Li 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 10 +-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index dc99a8ffac70..5c290e6aac46 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -6691,6 +6691,14 @@ amdgpu_dm_connector_atomic_check(struct drm_connector 
*conn,
if (!crtc)
return 0;
 
+   if (new_con_state->colorspace != old_con_state->colorspace) {
+   new_crtc_state = drm_atomic_get_crtc_state(state, crtc);
+   if (IS_ERR(new_crtc_state))
+   return PTR_ERR(new_crtc_state);
+
+   new_crtc_state->mode_changed = true;
+   }
+
if (!drm_connector_atomic_hdr_metadata_equal(old_con_state, 
new_con_state)) {
struct dc_info_packet hdr_infopacket;
 
@@ -6713,7 +6721,7 @@ amdgpu_dm_connector_atomic_check(struct drm_connector 
*conn,
 * set is permissible, however. So only force a
 * modeset if we're entering or exiting HDR.
 */
-   new_crtc_state->mode_changed =
+   new_crtc_state->mode_changed = new_crtc_state->mode_changed ||
!old_con_state->hdr_output_metadata ||
!new_con_state->hdr_output_metadata;
}
-- 
2.40.1

[PATCH v4 06/13] drm/connector: Allow drivers to pass list of supported colorspaces

Drivers might not support all colorspaces defined in
dp_colorspaces and hdmi_colorspaces. This results in
undefined behavior when userspace is setting an
unsupported colorspace.

Allow drivers to pass the list of supported colorspaces
when creating the colorspace property.

v2:
 - Use 0 to indicate support for all colorspaces (Jani)
 - Print drm_dbg_kms message when drivers pass 0
   to signal that drivers should specify supported
   colorspaecs explicity (Jani)
v3:
 - Move changes to create a common colorspace_names array
   to separate patch

Signed-off-by: Harry Wentland 
Cc: Pekka Paalanen 
Cc: Sebastian Wick 
Cc: vitaly.pros...@amd.com
Cc: Uma Shankar 
Cc: Ville Syrjälä 
Cc: Joshua Ashton 
Cc: Jani Nikula 
Cc: Simon Ser 
Cc: Ville Syrjälä 
Cc: Melissa Wen 
Cc: dri-devel@lists.freedesktop.org
Cc: amd-...@lists.freedesktop.org
---
 drivers/gpu/drm/drm_connector.c| 14 ++
 drivers/gpu/drm/i915/display/intel_connector.c |  4 ++--
 drivers/gpu/drm/vc4/vc4_hdmi.c |  2 +-
 include/drm/drm_connector.h|  7 +--
 4 files changed, 18 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
index 69480385eaf3..b63b3e3168a1 100644
--- a/drivers/gpu/drm/drm_connector.c
+++ b/drivers/gpu/drm/drm_connector.c
@@ -2045,9 +2045,12 @@ static int drm_mode_create_colorspace_property(struct 
drm_connector *connector,
  * Returns:
  * Zero on success, negative errno on failure.
  */
-int drm_mode_create_hdmi_colorspace_property(struct drm_connector *connector)
+int drm_mode_create_hdmi_colorspace_property(struct drm_connector *connector,
+u32 supported_colorspaces)
 {
-   return drm_mode_create_colorspace_property(connector, hdmi_colorspaces);
+   u32 colorspaces = supported_colorspaces & hdmi_colorspaces;
+
+   return drm_mode_create_colorspace_property(connector, colorspaces);
 }
 EXPORT_SYMBOL(drm_mode_create_hdmi_colorspace_property);
 
@@ -2061,9 +2064,12 @@ EXPORT_SYMBOL(drm_mode_create_hdmi_colorspace_property);
  * Returns:
  * Zero on success, negative errno on failure.
  */
-int drm_mode_create_dp_colorspace_property(struct drm_connector *connector)
+int drm_mode_create_dp_colorspace_property(struct drm_connector *connector,
+  u32 supported_colorspaces)
 {
-   return drm_mode_create_colorspace_property(connector, dp_colorspaces);
+   u32 colorspaces = supported_colorspaces & dp_colorspaces;
+
+   return drm_mode_create_colorspace_property(connector, colorspaces);
 }
 EXPORT_SYMBOL(drm_mode_create_dp_colorspace_property);
 
diff --git a/drivers/gpu/drm/i915/display/intel_connector.c 
b/drivers/gpu/drm/i915/display/intel_connector.c
index 6205ddd3ded0..e8b4a352a7a6 100644
--- a/drivers/gpu/drm/i915/display/intel_connector.c
+++ b/drivers/gpu/drm/i915/display/intel_connector.c
@@ -283,14 +283,14 @@ intel_attach_aspect_ratio_property(struct drm_connector 
*connector)
 void
 intel_attach_hdmi_colorspace_property(struct drm_connector *connector)
 {
-   if (!drm_mode_create_hdmi_colorspace_property(connector))
+   if (!drm_mode_create_hdmi_colorspace_property(connector, 0))
drm_connector_attach_colorspace_property(connector);
 }
 
 void
 intel_attach_dp_colorspace_property(struct drm_connector *connector)
 {
-   if (!drm_mode_create_dp_colorspace_property(connector))
+   if (!drm_mode_create_dp_colorspace_property(connector, 0))
drm_connector_attach_colorspace_property(connector);
 }
 
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index 55744216392b..eee53e841701 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
@@ -618,7 +618,7 @@ static int vc4_hdmi_connector_init(struct drm_device *dev,
if (ret)
return ret;
 
-   ret = drm_mode_create_hdmi_colorspace_property(connector);
+   ret = drm_mode_create_hdmi_colorspace_property(connector, 0);
if (ret)
return ret;
 
diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
index ae0b1ee5b99a..abe775e1382f 100644
--- a/include/drm/drm_connector.h
+++ b/include/drm/drm_connector.h
@@ -30,6 +30,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include 
 
@@ -1896,8 +1897,10 @@ int 
drm_connector_attach_hdr_output_metadata_property(struct drm_connector *conn
 bool drm_connector_atomic_hdr_metadata_equal(struct drm_connector_state 
*old_state,
 struct drm_connector_state 
*new_state);
 int drm_mode_create_aspect_ratio_property(struct drm_device *dev);
-int drm_mode_create_hdmi_colorspace_property(struct drm_connector *connector);
-int drm_mode_create_dp_colorspace_property(struct drm_connector *connector);
+int drm_mode_create_hdmi_colorspace_property(struct drm_connector *connector,
+u32

[PATCH v4 07/13] drm/amd/display: Always pass connector_state to stream validation

We need the connector_state for colorspace and scaling information
and can get it from connector->state.

Signed-off-by: Harry Wentland 
Cc: Pekka Paalanen 
Cc: Sebastian Wick 
Cc: vitaly.pros...@amd.com
Cc: Joshua Ashton 
Cc: Simon Ser 
Cc: Melissa Wen 
Cc: dri-devel@lists.freedesktop.org
Cc: amd-...@lists.freedesktop.org
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 9 +
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index a69f4a39d92a..ca093396d1ac 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -5946,15 +5946,14 @@ create_stream_for_sink(struct amdgpu_dm_connector 
*aconnector,
 {
struct drm_display_mode *preferred_mode = NULL;
struct drm_connector *drm_connector;
-   const struct drm_connector_state *con_state =
-   dm_state ? _state->base : NULL;
+   const struct drm_connector_state *con_state = _state->base;
struct dc_stream_state *stream = NULL;
struct drm_display_mode mode;
struct drm_display_mode saved_mode;
struct drm_display_mode *freesync_mode = NULL;
bool native_mode_found = false;
bool recalculate_timing = false;
-   bool scale = dm_state ? (dm_state->scaling != RMX_OFF) : false;
+   bool scale = dm_state->scaling != RMX_OFF;
int mode_refresh;
int preferred_refresh = 0;
enum color_transfer_func tf = TRANSFER_FUNC_UNKNOWN;
@@ -6596,7 +6595,9 @@ enum drm_mode_status 
amdgpu_dm_connector_mode_valid(struct drm_connector *connec
goto fail;
}
 
-   stream = create_validate_stream_for_sink(aconnector, mode, NULL, NULL);
+   stream = create_validate_stream_for_sink(aconnector, mode,
+
to_dm_connector_state(connector->state),
+NULL);
if (stream) {
dc_stream_release(stream);
result = MODE_OK;
-- 
2.40.1

[PATCH v4 11/13] drm/amd/display: Always set crtcinfo from create_stream_for_sink

From: Joshua Ashton 

Given that we always pass dm_state into here now, this won't ever
trigger anymore.

This is needed for we will always fail mode validation with invalid
clocks or link bandwidth errors.

Signed-off-by: Joshua Ashton 
Signed-off-by: Harry Wentland 
Cc: Pekka Paalanen 
Cc: Sebastian Wick 
Cc: vitaly.pros...@amd.com
Cc: Joshua Ashton 
Cc: Simon Ser 
Cc: Melissa Wen 
Cc: dri-devel@lists.freedesktop.org
Cc: amd-...@lists.freedesktop.org
Reviewed-By: Harry Wentland 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index a8de26f09806..4e96a34148cc 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -6046,7 +6046,7 @@ create_stream_for_sink(struct amdgpu_dm_connector 
*aconnector,
 
if (recalculate_timing)
drm_mode_set_crtcinfo(_mode, 0);
-   else if (!dm_state)
+   else
drm_mode_set_crtcinfo(, 0);
 
/*
-- 
2.40.1

[PATCH v4 03/13] drm/connector: Pull out common create_colorspace_property code

Signed-off-by: Harry Wentland 
Cc: Pekka Paalanen 
Cc: Sebastian Wick 
Cc: vitaly.pros...@amd.com
Cc: Uma Shankar 
Cc: Ville Syrjälä 
Cc: Joshua Ashton 
Cc: Jani Nikula 
Cc: Simon Ser 
Cc: Ville Syrjälä 
Cc: Melissa Wen 
Cc: dri-devel@lists.freedesktop.org
Cc: amd-...@lists.freedesktop.org
---
 drivers/gpu/drm/drm_connector.c | 54 -
 1 file changed, 27 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
index 547356e00341..9c087d6f5691 100644
--- a/drivers/gpu/drm/drm_connector.c
+++ b/drivers/gpu/drm/drm_connector.c
@@ -1975,33 +1975,44 @@ EXPORT_SYMBOL(drm_mode_create_aspect_ratio_property);
  * drm_mode_create_dp_colorspace_property() is used for DP connector.
  */
 
-/**
- * drm_mode_create_hdmi_colorspace_property - create hdmi colorspace property
- * @connector: connector to create the Colorspace property on.
- *
- * Called by a driver the first time it's needed, must be attached to desired
- * HDMI connectors.
- *
- * Returns:
- * Zero on success, negative errno on failure.
- */
-int drm_mode_create_hdmi_colorspace_property(struct drm_connector *connector)
+static int drm_mode_create_colorspace_property(struct drm_connector *connector,
+   const struct drm_prop_enum_list 
*colorspaces,
+   int size)
 {
struct drm_device *dev = connector->dev;
 
if (connector->colorspace_property)
return 0;
 
+   if (!colorspaces)
+   return 0;
+
connector->colorspace_property =
drm_property_create_enum(dev, DRM_MODE_PROP_ENUM, "Colorspace",
-hdmi_colorspaces,
-ARRAY_SIZE(hdmi_colorspaces));
+   colorspaces,
+   size);
 
if (!connector->colorspace_property)
return -ENOMEM;
 
return 0;
 }
+/**
+ * drm_mode_create_hdmi_colorspace_property - create hdmi colorspace property
+ * @connector: connector to create the Colorspace property on.
+ *
+ * Called by a driver the first time it's needed, must be attached to desired
+ * HDMI connectors.
+ *
+ * Returns:
+ * Zero on success, negative errno on failure.
+ */
+int drm_mode_create_hdmi_colorspace_property(struct drm_connector *connector)
+{
+   return drm_mode_create_colorspace_property(connector,
+  hdmi_colorspaces,
+  
ARRAY_SIZE(hdmi_colorspaces));
+}
 EXPORT_SYMBOL(drm_mode_create_hdmi_colorspace_property);
 
 /**
@@ -2016,20 +2027,9 @@ EXPORT_SYMBOL(drm_mode_create_hdmi_colorspace_property);
  */
 int drm_mode_create_dp_colorspace_property(struct drm_connector *connector)
 {
-   struct drm_device *dev = connector->dev;
-
-   if (connector->colorspace_property)
-   return 0;
-
-   connector->colorspace_property =
-   drm_property_create_enum(dev, DRM_MODE_PROP_ENUM, "Colorspace",
-dp_colorspaces,
-ARRAY_SIZE(dp_colorspaces));
-
-   if (!connector->colorspace_property)
-   return -ENOMEM;
-
-   return 0;
+   return drm_mode_create_colorspace_property(connector,
+  dp_colorspaces,
+  ARRAY_SIZE(dp_colorspaces));
 }
 EXPORT_SYMBOL(drm_mode_create_dp_colorspace_property);
 
-- 
2.40.1

[PATCH v4 05/13] drm/connector: Print connector colorspace in state debugfs

v3: Fix kerneldocs (kernel test robot)

v4: Avoid returning NULL from drm_get_colorspace_name

Signed-off-by: Harry Wentland 
Cc: Pekka Paalanen 
Cc: Sebastian Wick 
Cc: vitaly.pros...@amd.com
Cc: Uma Shankar 
Cc: Ville Syrjälä 
Cc: Joshua Ashton 
Cc: Jani Nikula 
Cc: Simon Ser 
Cc: Ville Syrjälä 
Cc: Melissa Wen 
Cc: dri-devel@lists.freedesktop.org
Cc: amd-...@lists.freedesktop.org
---
 drivers/gpu/drm/drm_atomic.c|  1 +
 drivers/gpu/drm/drm_connector.c | 15 +++
 include/drm/drm_connector.h |  1 +
 3 files changed, 17 insertions(+)

diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
index c0dc5858a723..d6d04c4ccfc0 100644
--- a/drivers/gpu/drm/drm_atomic.c
+++ b/drivers/gpu/drm/drm_atomic.c
@@ -1071,6 +1071,7 @@ static void drm_atomic_connector_print_state(struct 
drm_printer *p,
drm_printf(p, "\tcrtc=%s\n", state->crtc ? state->crtc->name : 
"(null)");
drm_printf(p, "\tself_refresh_aware=%d\n", state->self_refresh_aware);
drm_printf(p, "\tmax_requested_bpc=%d\n", state->max_requested_bpc);
+   drm_printf(p, "\tcolorspace=%s\n", 
drm_get_colorspace_name(state->colorspace));
 
if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
if (state->writeback_job && state->writeback_job->fb)
diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
index 8d24a5da4076..69480385eaf3 100644
--- a/drivers/gpu/drm/drm_connector.c
+++ b/drivers/gpu/drm/drm_connector.c
@@ -1048,6 +1048,21 @@ static const char * const colorspace_names[] = {
[DRM_MODE_COLORIMETRY_BT601_YCC] = "BT601_YCC",
 };
 
+/**
+ * drm_get_colorspace_name - return a string for color encoding
+ * @colorspace: color space to compute name of
+ *
+ * In contrast to the other drm_get_*_name functions this one here returns a
+ * const pointer and hence is threadsafe.
+ */
+const char *drm_get_colorspace_name(enum drm_colorspace colorspace)
+{
+   if (colorspace < ARRAY_SIZE(colorspace_names) && 
colorspace_names[colorspace])
+   return colorspace_names[colorspace];
+   else
+   return "(null)";
+}
+
 static const u32 hdmi_colorspaces =
BIT(DRM_MODE_COLORIMETRY_SMPTE_170M_YCC) |
BIT(DRM_MODE_COLORIMETRY_BT709_YCC) |
diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
index 565311e194da..ae0b1ee5b99a 100644
--- a/include/drm/drm_connector.h
+++ b/include/drm/drm_connector.h
@@ -1980,6 +1980,7 @@ void drm_connector_list_iter_end(struct 
drm_connector_list_iter *iter);
 
 bool drm_connector_has_possible_encoder(struct drm_connector *connector,
struct drm_encoder *encoder);
+const char *drm_get_colorspace_name(enum drm_colorspace colorspace);
 
 /**
  * drm_for_each_connector_iter - connector_list iterator macro
-- 
2.40.1

[PATCH v4 02/13] drm/connector: Add enum documentation to drm_colorspace

From: Joshua Ashton 

To match the other enums, and add more information about these values.

v2:
 - Specify where an enum entry comes from
 - Clarify DEFAULT and NO_DATA behavior
 - BT.2020 CYCC is "constant luminance"
 - correct type for BT.601

v4:
- drop DP/HDMI clarifications that might create
  more questions than answers

Signed-off-by: Joshua Ashton 
Signed-off-by: Harry Wentland 
Reviewed-by: Harry Wentland 

Cc: Pekka Paalanen 
Cc: Sebastian Wick 
Cc: vitaly.pros...@amd.com
Cc: Uma Shankar 
Cc: Ville Syrjälä 
Cc: Joshua Ashton 
Cc: Simon Ser 
Cc: Ville Syrjälä 
Cc: Melissa Wen 
Cc: dri-devel@lists.freedesktop.org
Cc: amd-...@lists.freedesktop.org
---
 include/drm/drm_connector.h | 62 +++--
 1 file changed, 60 insertions(+), 2 deletions(-)

diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
index 77401e425341..ee597593d7e6 100644
--- a/include/drm/drm_connector.h
+++ b/include/drm/drm_connector.h
@@ -363,13 +363,71 @@ enum drm_privacy_screen_status {
PRIVACY_SCREEN_ENABLED_LOCKED,
 };
 
-/*
- * This is a consolidated colorimetry list supported by HDMI and
+/**
+ * enum drm_colorspace - color space
+ *
+ * This enum is a consolidated colorimetry list supported by HDMI and
  * DP protocol standard. The respective connectors will register
  * a property with the subset of this list (supported by that
  * respective protocol). Userspace will set the colorspace through
  * a colorspace property which will be created and exposed to
  * userspace.
+ *
+ * DP definitions come from the DP v2.0 spec
+ * HDMI definitions come from the CTA-861-H spec
+ *
+ * @DRM_MODE_COLORIMETRY_DEFAULT:
+ *   Driver specific behavior.
+ * @DRM_MODE_COLORIMETRY_NO_DATA:
+ *   Driver specific behavior.
+ * @DRM_MODE_COLORIMETRY_SMPTE_170M_YCC:
+ *   (HDMI)
+ *   SMPTE ST 170M colorimetry format
+ * @DRM_MODE_COLORIMETRY_BT709_YCC:
+ *   (HDMI, DP)
+ *   ITU-R BT.709 colorimetry format
+ * @DRM_MODE_COLORIMETRY_XVYCC_601:
+ *   (HDMI, DP)
+ *   xvYCC601 colorimetry format
+ * @DRM_MODE_COLORIMETRY_XVYCC_709:
+ *   (HDMI, DP)
+ *   xvYCC709 colorimetry format
+ * @DRM_MODE_COLORIMETRY_SYCC_601:
+ *   (HDMI, DP)
+ *   sYCC601 colorimetry format
+ * @DRM_MODE_COLORIMETRY_OPYCC_601:
+ *   (HDMI, DP)
+ *   opYCC601 colorimetry format
+ * @DRM_MODE_COLORIMETRY_OPRGB:
+ *   (HDMI, DP)
+ *   opRGB colorimetry format
+ * @DRM_MODE_COLORIMETRY_BT2020_CYCC:
+ *   (HDMI, DP)
+ *   ITU-R BT.2020 Y'c C'bc C'rc (constant luminance) colorimetry format
+ * @DRM_MODE_COLORIMETRY_BT2020_RGB:
+ *   (HDMI, DP)
+ *   ITU-R BT.2020 R' G' B' colorimetry format
+ * @DRM_MODE_COLORIMETRY_BT2020_YCC:
+ *   (HDMI, DP)
+ *   ITU-R BT.2020 Y' C'b C'r colorimetry format
+ * @DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
+ *   (HDMI)
+ *   SMPTE ST 2113 P3D65 colorimetry format
+ * @DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
+ *   (HDMI)
+ *   SMPTE ST 2113 P3DCI colorimetry format
+ * @DRM_MODE_COLORIMETRY_RGB_WIDE_FIXED:
+ *   (DP)
+ *   RGB wide gamut fixed point colorimetry format
+ * @DRM_MODE_COLORIMETRY_RGB_WIDE_FLOAT:
+ *   (DP)
+ *   RGB wide gamut floating point
+ *   (scRGB (IEC 61966-2-2)) colorimetry format
+ * @DRM_MODE_COLORIMETRY_BT601_YCC:
+ *   (DP)
+ *   ITU-R BT.601 colorimetry format
+ *   The DP spec does not say whether this is the 525 or the 625
+ *   line version.
  */
 enum drm_colorspace {
/* For Default case, driver will set the colorspace */
-- 
2.40.1

[PATCH v4 01/13] drm/connector: Convert DRM_MODE_COLORIMETRY to enum

This allows us to use strongly typed arguments.

v2:
 - Bring NO_DATA back
 - Provide explicit enum values

v3:
- Drop unnecessary '&' from kerneldoc (emersion)

v4:
- Fix Normal Colorimetry comment

Signed-off-by: Harry Wentland 
Reviewed-by: Simon Ser 

Cc: Pekka Paalanen 
Cc: Sebastian Wick 
Cc: vitaly.pros...@amd.com
Cc: Uma Shankar 
Cc: Ville Syrjälä 
Cc: Joshua Ashton 
Cc: Simon Ser 
Cc: Ville Syrjälä 
Cc: Melissa Wen 
Cc: dri-devel@lists.freedesktop.org
Cc: amd-...@lists.freedesktop.org
Reviewed-by: Pekka Paalanen 
---
 include/drm/display/drm_dp.h |  2 +-
 include/drm/drm_connector.h  | 49 ++--
 2 files changed, 26 insertions(+), 25 deletions(-)

diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
index f1be179c5f1f..7f858352cb43 100644
--- a/include/drm/display/drm_dp.h
+++ b/include/drm/display/drm_dp.h
@@ -1626,7 +1626,7 @@ enum dp_pixelformat {
  *
  * This enum is used to indicate DP VSC SDP Colorimetry formats.
  * It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through
- * DB18] and a name of enum member follows DRM_MODE_COLORIMETRY definition.
+ * DB18] and a name of enum member follows enum drm_colorimetry definition.
  *
  * @DP_COLORIMETRY_DEFAULT: sRGB (IEC 61966-2-1) or
  *  ITU-R BT.601 colorimetry format
diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
index 565cf9d3c550..77401e425341 100644
--- a/include/drm/drm_connector.h
+++ b/include/drm/drm_connector.h
@@ -371,29 +371,30 @@ enum drm_privacy_screen_status {
  * a colorspace property which will be created and exposed to
  * userspace.
  */
-
-/* For Default case, driver will set the colorspace */
-#define DRM_MODE_COLORIMETRY_DEFAULT   0
-/* CEA 861 Normal Colorimetry options */
-#define DRM_MODE_COLORIMETRY_NO_DATA   0
-#define DRM_MODE_COLORIMETRY_SMPTE_170M_YCC1
-#define DRM_MODE_COLORIMETRY_BT709_YCC 2
-/* CEA 861 Extended Colorimetry Options */
-#define DRM_MODE_COLORIMETRY_XVYCC_601 3
-#define DRM_MODE_COLORIMETRY_XVYCC_709 4
-#define DRM_MODE_COLORIMETRY_SYCC_601  5
-#define DRM_MODE_COLORIMETRY_OPYCC_601 6
-#define DRM_MODE_COLORIMETRY_OPRGB 7
-#define DRM_MODE_COLORIMETRY_BT2020_CYCC   8
-#define DRM_MODE_COLORIMETRY_BT2020_RGB9
-#define DRM_MODE_COLORIMETRY_BT2020_YCC10
-/* Additional Colorimetry extension added as part of CTA 861.G */
-#define DRM_MODE_COLORIMETRY_DCI_P3_RGB_D6511
-#define DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER12
-/* Additional Colorimetry Options added for DP 1.4a VSC Colorimetry Format */
-#define DRM_MODE_COLORIMETRY_RGB_WIDE_FIXED13
-#define DRM_MODE_COLORIMETRY_RGB_WIDE_FLOAT14
-#define DRM_MODE_COLORIMETRY_BT601_YCC 15
+enum drm_colorspace {
+   /* For Default case, driver will set the colorspace */
+   DRM_MODE_COLORIMETRY_DEFAULT= 0,
+   /* CEA 861 Normal Colorimetry options */
+   DRM_MODE_COLORIMETRY_NO_DATA= 0,
+   DRM_MODE_COLORIMETRY_SMPTE_170M_YCC = 1,
+   DRM_MODE_COLORIMETRY_BT709_YCC  = 2,
+   /* CEA 861 Extended Colorimetry Options */
+   DRM_MODE_COLORIMETRY_XVYCC_601  = 3,
+   DRM_MODE_COLORIMETRY_XVYCC_709  = 4,
+   DRM_MODE_COLORIMETRY_SYCC_601   = 5,
+   DRM_MODE_COLORIMETRY_OPYCC_601  = 6,
+   DRM_MODE_COLORIMETRY_OPRGB  = 7,
+   DRM_MODE_COLORIMETRY_BT2020_CYCC= 8,
+   DRM_MODE_COLORIMETRY_BT2020_RGB = 9,
+   DRM_MODE_COLORIMETRY_BT2020_YCC = 10,
+   /* Additional Colorimetry extension added as part of CTA 861.G */
+   DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65 = 11,
+   DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER = 12,
+   /* Additional Colorimetry Options added for DP 1.4a VSC Colorimetry 
Format */
+   DRM_MODE_COLORIMETRY_RGB_WIDE_FIXED = 13,
+   DRM_MODE_COLORIMETRY_RGB_WIDE_FLOAT = 14,
+   DRM_MODE_COLORIMETRY_BT601_YCC  = 15,
+};
 
 /**
  * enum drm_bus_flags - bus_flags info for _display_info
@@ -828,7 +829,7 @@ struct drm_connector_state {
 * colorspace change on Sink. This is most commonly used to switch
 * to wider color gamuts like BT2020.
 */
-   u32 colorspace;
+   enum drm_colorspace colorspace;
 
/**
 * @writeback_job: Writeback job for writeback connectors
-- 
2.40.1

[PATCH v4 00/13] Enable Colorspace connector property in amdgpu

This patchset is based on Joshua's previous patchset [1], as well
as my previous patchset [2].

It is
- enabling support for the colorspace property in amdgpu, as well as
- allowing drivers to specify the supported set of colorspaces, and

Colorspace, Infoframes, and YCbCr matrix
---

Even though the initial intent of the colorspace property was to set the
colorspace field in the respective HDMI AVI and DP SDP infoframes that
is not sufficient in all scenarios. For DP the colorspace information
also affects the MSA (main stream attribute) packet. For YUV output the
colorspace affects the RGB-to-YCbCr conversion matrix. The colorspace
field of the infopackets also depends on the encoding used, which is
something that is decided by the driver and not known to userspace.

For these reasons a driver will need to be able to select the supported
colorspaces at property creation.

Note: There seems to be an understanding that the colorspace property
should ONLY modify the infoframe. While this is current behavior and
sufficient in some cases it is nowhere specified that this should be the
only use of this property. As outlined above this limitation is not
going to work in all cases.

This patchset does not affect current behavior for the drivers that
implement this property: i915 and vc4.

In the future we might want to give userspace control over the encoding
format on the wire, in particular to avoid use of YUV420 when image
fidelity is important. This work would likely go hand in hand with a
min_bpc property and wouldn't conflict with the work done in this
patchset. I would expect this future work to tag along with a drm_crtc
or drm_connector's Color Pipeline, similar to the one propsed for
drm_plane [3].

Colorspace on crtc or connector?


There have been suggestions of programming 'colorspace' on the drm_crtc
but I don't think the crtc is the right place for this property. The
drm_plane and drm_crtc will be used to offload color processing that
would normally be done via the GFX or other pipelines. The drm_connector
controls the signalling with the display and ensures the wire format is
appropriate for the encoding by programming the RGB-to-YCbCr matrix.

[1] https://patchwork.freedesktop.org/series/113632/
[2] https://patchwork.freedesktop.org/series/111865/
[3] https://lists.freedesktop.org/archives/dri-devel/2023-May/403173.html

v2:
- Tested with DP and HDMI analyzers
- Confirmed driver will fallback to lower bpc when needed
- Dropped hunk to set HDMI AVI infoframe as it was a no-op
- Fixed BT.2020 YCbCr colorimetry (JoshuaAshton)
- Simplify initialization of supported colorspaces (Jani)
- Fix kerneldoc (kernel test robot)

v3:
- Added documentation for colorspaces (Pekka, Joshua)
- Split 'Allow drivers to pass list of supported colorspaces' patch
  to pull out code to create common colorspace array and keep it separate
  from change to create only supported colorspaces

v4:
- Don't "deprecate" existing enum values
- Fixes based on review comments throughout
- Dropped Josh's RBs

Cc: Pekka Paalanen 
Cc: Sebastian Wick 
Cc: vitaly.pros...@amd.com
Cc: Uma Shankar 
Cc: Ville Syrjälä 
Cc: Joshua Ashton 
Cc: Jani Nikula 
Cc: Michel Dänzer 
Cc: Simon Ser 
Cc: Melissa Wen 
Cc: dri-devel@lists.freedesktop.org
Cc: amd-...@lists.freedesktop.org

Harry Wentland (10):
  drm/connector: Convert DRM_MODE_COLORIMETRY to enum
  drm/connector: Pull out common create_colorspace_property code
  drm/connector: Use common colorspace_names array
  drm/connector: Print connector colorspace in state debugfs
  drm/connector: Allow drivers to pass list of supported colorspaces
  drm/amd/display: Always pass connector_state to stream validation
  drm/amd/display: Register Colorspace property for DP and HDMI
  drm/amd/display: Signal mode_changed if colorspace changed
  drm/amd/display: Send correct DP colorspace infopacket
  drm/amd/display: Add debugfs for testing output colorspace

Joshua Ashton (3):
  drm/connector: Add enum documentation to drm_colorspace
  drm/amd/display: Always set crtcinfo from create_stream_for_sink
  drm/amd/display: Refactor avi_info_frame colorimetry determination

 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  84 ++---
 .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c |  57 ++
 .../gpu/drm/amd/display/dc/core/dc_resource.c |  28 +--
 drivers/gpu/drm/drm_atomic.c  |   1 +
 drivers/gpu/drm/drm_connector.c   | 176 +++---
 .../gpu/drm/i915/display/intel_connector.c|   4 +-
 drivers/gpu/drm/vc4/vc4_hdmi.c|   2 +-
 include/drm/display/drm_dp.h  |   2 +-
 include/drm/drm_connector.h   | 121 +---
 9 files changed, 341 insertions(+), 134 deletions(-)

--
2.40.1

[PATCH AUTOSEL 5.10 29/31] drm/msm: Be more shouty if per-process pgtables aren't working

From: Rob Clark 

[ Upstream commit 5c054db54c43a5fcb5cc81012361f5e3fac37637 ]

Otherwise it is not always obvious if a dt or iommu change is causing us
to fall back to global pgtable.

Signed-off-by: Rob Clark 
Reviewed-by: Dmitry Baryshkov 
Patchwork: https://patchwork.freedesktop.org/patch/537359/
Link: https://lore.kernel.org/r/20230516222039.907690-2-robdcl...@gmail.com
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/msm/msm_iommu.c | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/msm_iommu.c b/drivers/gpu/drm/msm/msm_iommu.c
index ecab6287c1c39..b81390d6ebd38 100644
--- a/drivers/gpu/drm/msm/msm_iommu.c
+++ b/drivers/gpu/drm/msm/msm_iommu.c
@@ -155,7 +155,12 @@ struct msm_mmu *msm_iommu_pagetable_create(struct msm_mmu 
*parent)
/* Get the pagetable configuration from the domain */
if (adreno_smmu->cookie)
ttbr1_cfg = adreno_smmu->get_ttbr1_cfg(adreno_smmu->cookie);
-   if (!ttbr1_cfg)
+
+   /*
+* If you hit this WARN_ONCE() you are probably missing an entry in
+* qcom_smmu_impl_of_match[] in arm-smmu-qcom.c
+*/
+   if (WARN_ONCE(!ttbr1_cfg, "No per-process page tables"))
return ERR_PTR(-ENODEV);
 
pagetable = kzalloc(sizeof(*pagetable), GFP_KERNEL);
-- 
2.39.2

[PATCH AUTOSEL 5.15 42/43] drm/amdgpu: skip disabling fence driver src_irqs when device is unplugged

From: Guchun Chen 

[ Upstream commit c1a322a7a4a96cd0a3dde32ce37af437a78bf8cd ]

When performing device unbind or halt, we have disabled all irqs at the
very begining like amdgpu_pci_remove or amdgpu_device_halt. So
amdgpu_irq_put for irqs stored in fence driver should not be called
any more, otherwise, below calltrace will arrive.

[  139.114088] WARNING: CPU: 2 PID: 1550 at 
drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c:616 amdgpu_irq_put+0xf6/0x110 [amdgpu]
[  139.114655] Call Trace:
[  139.114655]  
[  139.114657]  amdgpu_fence_driver_hw_fini+0x93/0x130 [amdgpu]
[  139.114836]  amdgpu_device_fini_hw+0xb6/0x350 [amdgpu]
[  139.114955]  amdgpu_driver_unload_kms+0x51/0x70 [amdgpu]
[  139.115075]  amdgpu_pci_remove+0x63/0x160 [amdgpu]
[  139.115193]  ? __pm_runtime_resume+0x64/0x90
[  139.115195]  pci_device_remove+0x3a/0xb0
[  139.115197]  device_remove+0x43/0x70
[  139.115198]  device_release_driver_internal+0xbd/0x140

Signed-off-by: Guchun Chen 
Acked-by: Alex Deucher 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
index bbd6f7a123033..8599e0ffa8292 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
@@ -561,7 +561,8 @@ void amdgpu_fence_driver_hw_fini(struct amdgpu_device *adev)
if (r)
amdgpu_fence_driver_force_completion(ring);
 
-   if (ring->fence_drv.irq_src)
+   if (!drm_dev_is_unplugged(adev_to_drm(adev)) &&
+   ring->fence_drv.irq_src)
amdgpu_irq_put(adev, ring->fence_drv.irq_src,
   ring->fence_drv.irq_type);
 
-- 
2.39.2

[PATCH AUTOSEL 5.15 39/43] drm/msm: Be more shouty if per-process pgtables aren't working

From: Rob Clark 

[ Upstream commit 5c054db54c43a5fcb5cc81012361f5e3fac37637 ]

Otherwise it is not always obvious if a dt or iommu change is causing us
to fall back to global pgtable.

Signed-off-by: Rob Clark 
Reviewed-by: Dmitry Baryshkov 
Patchwork: https://patchwork.freedesktop.org/patch/537359/
Link: https://lore.kernel.org/r/20230516222039.907690-2-robdcl...@gmail.com
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/msm/msm_iommu.c | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/msm_iommu.c b/drivers/gpu/drm/msm/msm_iommu.c
index a54ed354578b5..ef4da3f0cd22d 100644
--- a/drivers/gpu/drm/msm/msm_iommu.c
+++ b/drivers/gpu/drm/msm/msm_iommu.c
@@ -157,7 +157,12 @@ struct msm_mmu *msm_iommu_pagetable_create(struct msm_mmu 
*parent)
/* Get the pagetable configuration from the domain */
if (adreno_smmu->cookie)
ttbr1_cfg = adreno_smmu->get_ttbr1_cfg(adreno_smmu->cookie);
-   if (!ttbr1_cfg)
+
+   /*
+* If you hit this WARN_ONCE() you are probably missing an entry in
+* qcom_smmu_impl_of_match[] in arm-smmu-qcom.c
+*/
+   if (WARN_ONCE(!ttbr1_cfg, "No per-process page tables"))
return ERR_PTR(-ENODEV);
 
/*
-- 
2.39.2

[PATCH AUTOSEL 6.1 54/57] drm/amdgpu: skip disabling fence driver src_irqs when device is unplugged

From: Guchun Chen 

[ Upstream commit c1a322a7a4a96cd0a3dde32ce37af437a78bf8cd ]

When performing device unbind or halt, we have disabled all irqs at the
very begining like amdgpu_pci_remove or amdgpu_device_halt. So
amdgpu_irq_put for irqs stored in fence driver should not be called
any more, otherwise, below calltrace will arrive.

[  139.114088] WARNING: CPU: 2 PID: 1550 at 
drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c:616 amdgpu_irq_put+0xf6/0x110 [amdgpu]
[  139.114655] Call Trace:
[  139.114655]  
[  139.114657]  amdgpu_fence_driver_hw_fini+0x93/0x130 [amdgpu]
[  139.114836]  amdgpu_device_fini_hw+0xb6/0x350 [amdgpu]
[  139.114955]  amdgpu_driver_unload_kms+0x51/0x70 [amdgpu]
[  139.115075]  amdgpu_pci_remove+0x63/0x160 [amdgpu]
[  139.115193]  ? __pm_runtime_resume+0x64/0x90
[  139.115195]  pci_device_remove+0x3a/0xb0
[  139.115197]  device_remove+0x43/0x70
[  139.115198]  device_release_driver_internal+0xbd/0x140

Signed-off-by: Guchun Chen 
Acked-by: Alex Deucher 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
index 3cc1929285fc0..ed6878d5b3ce3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
@@ -528,7 +528,8 @@ void amdgpu_fence_driver_hw_fini(struct amdgpu_device *adev)
if (r)
amdgpu_fence_driver_force_completion(ring);
 
-   if (ring->fence_drv.irq_src)
+   if (!drm_dev_is_unplugged(adev_to_drm(adev)) &&
+   ring->fence_drv.irq_src)
amdgpu_irq_put(adev, ring->fence_drv.irq_src,
   ring->fence_drv.irq_type);
 
-- 
2.39.2

[PATCH AUTOSEL 6.1 50/57] drm/msm: Be more shouty if per-process pgtables aren't working

From: Rob Clark 

[ Upstream commit 5c054db54c43a5fcb5cc81012361f5e3fac37637 ]

Otherwise it is not always obvious if a dt or iommu change is causing us
to fall back to global pgtable.

Signed-off-by: Rob Clark 
Reviewed-by: Dmitry Baryshkov 
Patchwork: https://patchwork.freedesktop.org/patch/537359/
Link: https://lore.kernel.org/r/20230516222039.907690-2-robdcl...@gmail.com
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/msm/msm_iommu.c | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/msm_iommu.c b/drivers/gpu/drm/msm/msm_iommu.c
index 5577cea7c0092..d12ba47b37c4f 100644
--- a/drivers/gpu/drm/msm/msm_iommu.c
+++ b/drivers/gpu/drm/msm/msm_iommu.c
@@ -227,7 +227,12 @@ struct msm_mmu *msm_iommu_pagetable_create(struct msm_mmu 
*parent)
/* Get the pagetable configuration from the domain */
if (adreno_smmu->cookie)
ttbr1_cfg = adreno_smmu->get_ttbr1_cfg(adreno_smmu->cookie);
-   if (!ttbr1_cfg)
+
+   /*
+* If you hit this WARN_ONCE() you are probably missing an entry in
+* qcom_smmu_impl_of_match[] in arm-smmu-qcom.c
+*/
+   if (WARN_ONCE(!ttbr1_cfg, "No per-process page tables"))
return ERR_PTR(-ENODEV);
 
/*
-- 
2.39.2

[PATCH AUTOSEL 6.3 64/67] drm/amdgpu: skip disabling fence driver src_irqs when device is unplugged

From: Guchun Chen 

[ Upstream commit c1a322a7a4a96cd0a3dde32ce37af437a78bf8cd ]

When performing device unbind or halt, we have disabled all irqs at the
very begining like amdgpu_pci_remove or amdgpu_device_halt. So
amdgpu_irq_put for irqs stored in fence driver should not be called
any more, otherwise, below calltrace will arrive.

[  139.114088] WARNING: CPU: 2 PID: 1550 at 
drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c:616 amdgpu_irq_put+0xf6/0x110 [amdgpu]
[  139.114655] Call Trace:
[  139.114655]  
[  139.114657]  amdgpu_fence_driver_hw_fini+0x93/0x130 [amdgpu]
[  139.114836]  amdgpu_device_fini_hw+0xb6/0x350 [amdgpu]
[  139.114955]  amdgpu_driver_unload_kms+0x51/0x70 [amdgpu]
[  139.115075]  amdgpu_pci_remove+0x63/0x160 [amdgpu]
[  139.115193]  ? __pm_runtime_resume+0x64/0x90
[  139.115195]  pci_device_remove+0x3a/0xb0
[  139.115197]  device_remove+0x43/0x70
[  139.115198]  device_release_driver_internal+0xbd/0x140

Signed-off-by: Guchun Chen 
Acked-by: Alex Deucher 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
index f52d0ba91a770..a7d250809da99 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
@@ -582,7 +582,8 @@ void amdgpu_fence_driver_hw_fini(struct amdgpu_device *adev)
if (r)
amdgpu_fence_driver_force_completion(ring);
 
-   if (ring->fence_drv.irq_src)
+   if (!drm_dev_is_unplugged(adev_to_drm(adev)) &&
+   ring->fence_drv.irq_src)
amdgpu_irq_put(adev, ring->fence_drv.irq_src,
   ring->fence_drv.irq_type);
 
-- 
2.39.2

[PATCH AUTOSEL 6.3 60/67] drm/msm: Be more shouty if per-process pgtables aren't working

From: Rob Clark 

[ Upstream commit 5c054db54c43a5fcb5cc81012361f5e3fac37637 ]

Otherwise it is not always obvious if a dt or iommu change is causing us
to fall back to global pgtable.

Signed-off-by: Rob Clark 
Reviewed-by: Dmitry Baryshkov 
Patchwork: https://patchwork.freedesktop.org/patch/537359/
Link: https://lore.kernel.org/r/20230516222039.907690-2-robdcl...@gmail.com
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/msm/msm_iommu.c | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/msm_iommu.c b/drivers/gpu/drm/msm/msm_iommu.c
index c2507582ecf34..0d6a69cd6f7a5 100644
--- a/drivers/gpu/drm/msm/msm_iommu.c
+++ b/drivers/gpu/drm/msm/msm_iommu.c
@@ -234,7 +234,12 @@ struct msm_mmu *msm_iommu_pagetable_create(struct msm_mmu 
*parent)
/* Get the pagetable configuration from the domain */
if (adreno_smmu->cookie)
ttbr1_cfg = adreno_smmu->get_ttbr1_cfg(adreno_smmu->cookie);
-   if (!ttbr1_cfg)
+
+   /*
+* If you hit this WARN_ONCE() you are probably missing an entry in
+* qcom_smmu_impl_of_match[] in arm-smmu-qcom.c
+*/
+   if (WARN_ONCE(!ttbr1_cfg, "No per-process page tables"))
return ERR_PTR(-ENODEV);
 
/*
-- 
2.39.2

Re: [PATCH v6] drm/msm/dp: enable HDP plugin/unplugged interrupts at hpd_enable/disable

2023-05-25 Thread Dmitry Baryshkov


On 24/05/2023 00:52, Kuogee Hsieh wrote:

The internal_hpd flag is set to true by dp_bridge_hpd_enable() and set to
false by dp_bridge_hpd_disable() to handle GPIO pinmuxed into DP controller
case. HDP related interrupts can not be enabled until internal_hpd is set
to true. At current implementation dp_display_config_hpd() will initialize
DP host controller first followed by enabling HDP related interrupts if
internal_hpd was true at that time. Enable HDP related interrupts depends on
internal_hpd status may leave system with DP driver host is in running state
but without HDP related interrupts being enabled. This will prevent external
display from being detected. Eliminated this dependency by moving HDP related
interrupts enable/disable be done at dp_bridge_hpd_enable/disable() directly
regardless of internal_hpd status.

Changes in V3:
-- dp_catalog_ctrl_hpd_enable() and dp_catalog_ctrl_hpd_disable()
-- rewording ocmmit text

Changes in V4:
-- replace dp_display_config_hpd() with dp_display_host_start()
-- move enable_irq() at dp_display_host_start();

Changes in V5:
-- replace dp_display_host_start() with dp_display_host_init()

Changes in V6:
-- squash remove enable_irq() and disable_irq()

Fixes: cd198caddea7 ("drm/msm/dp: Rely on hpd_enable/disable callbacks")
Signed-off-by: Kuogee Hsieh 
---
  drivers/gpu/drm/msm/dp/dp_catalog.c | 15 +++-
  drivers/gpu/drm/msm/dp/dp_catalog.h |  3 +-
  drivers/gpu/drm/msm/dp/dp_display.c | 71 ++---
  3 files changed, 35 insertions(+), 54 deletions(-)


Reviewed-by: Dmitry Baryshkov 

--
With best wishes
Dmitry

Re: [Freedreno] [PATCH] Revert "drm/msm/dp: Remove INIT_SETUP delay"

2023-05-25 Thread Abhinav Kumar





On 5/25/2023 10:57 AM, Kuogee Hsieh wrote:


On 5/24/2023 5:58 AM, Leonard Lausen wrote:

[  275.025497] [drm:dpu_encoder_phys_vid_wait_for_commit_done:488]
[dpu error]vblank timeout
[  275.025514] [drm:dpu_kms_wait_for_commit_done:510] [dpu 
error]wait

for commit done returned -110
[  275.064141] [drm:dpu_encoder_frame_done_timeout:2382] [dpu
error]enc33 frame done timeout
This is a different crash but the root-cause of both the issues is 
the

bridge hpd_enable/disable series.

https://patchwork.freedesktop.org/patch/514414/

Yes, the new patch to fix this issue is here

https://patchwork.freedesktop.org/patch/538601/?series=118148=3

Apologies if you were not CCed on this, if a next version is CCed,
will ask kuogee to cc you.

Meanwhile, will be great if you can verify if it works for you and
provide Tested-by tags.

Hi Leonard,

I had  cc you with v5 patches.

Would you please verify it.

Hi Kuogee,

thank you. Verified the v6 patch fixes the regression when ported to
6.3.3. One non-fatal issue remains: Suspending and resuming the system
while USB-C DP monitor is connected triggers an error, though the system
recovers within a second without the need to unplug the cable.

[drm:drm_mode_config_helper_resume] *ERROR* Failed to resume (-107)


dmesg snippet related to the suspend below


[  197.845110] usb 2-1.4.4: reset SuperSpeed USB device number 12 
using xhci-hcd
[  198.235191] [drm:drm_mode_config_helper_resume] *ERROR* Failed to 
resume (-107)


Hi Leonard,

I did not see this problem at my setup (Kodiak) during suspend/resume.

Will investigate more on Trogdor device.

Thanks,



Hi Leonard

Feel free to open a bug for this and assign to me, we can check this and 
ask more info if needed on that bug.


Thanks

Abhinav




[  198.528638] OOM killer enabled.
[  198.531866] Restarting tasks ...
[  198.531994] usb 1-1.4.4.1: USB disconnect, device number 27
[  198.532223] usb 1-1.4.3: USB disconnect, device number 23
[  198.532509] usb 1-1.4.2.1: USB disconnect, device number 29
[  198.534805] r8152-cfgselector 2-1.4.4.2: USB disconnect, device 
number 13

[  198.535444] done.
[  198.535536] usb 1-1.1: USB disconnect, device number 15
[  198.567811] random: crng reseeded on system resumption
[  198.583431] PM: suspend exit

Re: [Freedreno] [PATCH] Revert "drm/msm/dp: Remove INIT_SETUP delay"




On 5/24/2023 5:58 AM, Leonard Lausen wrote:

[  275.025497] [drm:dpu_encoder_phys_vid_wait_for_commit_done:488]
[dpu error]vblank timeout
[  275.025514] [drm:dpu_kms_wait_for_commit_done:510] [dpu error]wait
for commit done returned -110
[  275.064141] [drm:dpu_encoder_frame_done_timeout:2382] [dpu
error]enc33 frame done timeout

This is a different crash but the root-cause of both the issues is the
bridge hpd_enable/disable series.

https://patchwork.freedesktop.org/patch/514414/

Yes, the new patch to fix this issue is here

https://patchwork.freedesktop.org/patch/538601/?series=118148=3

Apologies if you were not CCed on this, if a next version is CCed,
will ask kuogee to cc you.

Meanwhile, will be great if you can verify if it works for you and
provide Tested-by tags.

Hi Leonard,

I had  cc you with v5 patches.

Would you please verify it.

Hi Kuogee,

thank you. Verified the v6 patch fixes the regression when ported to
6.3.3. One non-fatal issue remains: Suspending and resuming the system
while USB-C DP monitor is connected triggers an error, though the system
recovers within a second without the need to unplug the cable.

[drm:drm_mode_config_helper_resume] *ERROR* Failed to resume (-107)


dmesg snippet related to the suspend below


[  197.845110] usb 2-1.4.4: reset SuperSpeed USB device number 12 using xhci-hcd
[  198.235191] [drm:drm_mode_config_helper_resume] *ERROR* Failed to resume 
(-107)


Hi Leonard,

I did not see this problem at my setup (Kodiak) during suspend/resume.

Will investigate more on Trogdor device.

Thanks,



[  198.528638] OOM killer enabled.
[  198.531866] Restarting tasks ...
[  198.531994] usb 1-1.4.4.1: USB disconnect, device number 27
[  198.532223] usb 1-1.4.3: USB disconnect, device number 23
[  198.532509] usb 1-1.4.2.1: USB disconnect, device number 29
[  198.534805] r8152-cfgselector 2-1.4.4.2: USB disconnect, device number 13
[  198.535444] done.
[  198.535536] usb 1-1.1: USB disconnect, device number 15
[  198.567811] random: crng reseeded on system resumption
[  198.583431] PM: suspend exit

[PATCH v14 07/10] drm/msm/dpu: always clear every individual pending flush mask

There are two tiers of pending flush control, top level and
individual hardware block. Currently only the top level of
flush mask is reset to 0 but the individual pending flush masks
of particular hardware blocks are left at their previous values,
eventually accumulating all possible bit values and typically
flushing more than necessary.
Reset all individual hardware block flush masks to 0 to avoid
accidentally flushing them.

Changes in V13:
-- rewording commit text
-- add an empty space line as suggested

Changes in V14:
-- add Fixes tag

Fixes: 73bfb790ac78 ("msm:disp:dpu1: setup display datapath for SC7180 target")
Signed-off-by: Kuogee Hsieh 
Reviewed-by: Dmitry Baryshkov 
Reviewed-by: Marijn Suijten 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
index 69d0ea2..64c21e0 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
@@ -100,6 +100,9 @@ static inline void dpu_hw_ctl_clear_pending_flush(struct 
dpu_hw_ctl *ctx)
trace_dpu_hw_ctl_clear_pending_flush(ctx->pending_flush_mask,
 dpu_hw_ctl_get_flush_register(ctx));
ctx->pending_flush_mask = 0x0;
+   ctx->pending_intf_flush_mask = 0;
+   ctx->pending_wb_flush_mask = 0;
+   ctx->pending_merge_3d_flush_mask = 0;
 
memset(ctx->pending_dspp_flush_mask, 0,
sizeof(ctx->pending_dspp_flush_mask));
-- 
2.7.4

[PATCH v14 05/10] drm/msm/dpu: Introduce PINGPONG_NONE to disconnect DSC from PINGPONG

Disabling the crossbar mux between DSC and PINGPONG currently
requires a bogus enum dpu_pingpong value to be passed when calling
dsc_bind_pingpong_blk() with enable=false, even though the register
value written is independent of the current PINGPONG block.  Replace
that `bool enable` parameter with a new PINGPONG_NONE dpu_pingpong
flag that triggers the write of the "special" 0xF "crossbar
disabled" value to the register instead.

Changes in v4:
-- more details to commit text

Changes in v5:
-- rewording commit text suggested by Marijn
-- add DRM_DEBUG_KMS for DSC unbinding case

Changes in v8:
-- fix checkpatch warning

Signed-off-by: Kuogee Hsieh 
Reviewed-by: Dmitry Baryshkov 
Reviewed-by: Marijn Suijten 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c |  2 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c  | 14 +++---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h  |  1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h |  3 ++-
 4 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index cf1de5d..ffa6f04 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -1850,7 +1850,7 @@ static void dpu_encoder_dsc_pipe_cfg(struct dpu_hw_dsc 
*hw_dsc,
hw_pp->ops.setup_dsc(hw_pp);
 
if (hw_dsc->ops.dsc_bind_pingpong_blk)
-   hw_dsc->ops.dsc_bind_pingpong_blk(hw_dsc, true, hw_pp->idx);
+   hw_dsc->ops.dsc_bind_pingpong_blk(hw_dsc, hw_pp->idx);
 
if (hw_pp->ops.enable_dsc)
hw_pp->ops.enable_dsc(hw_pp);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
index 8deedeae..509dbaa 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
@@ -157,7 +157,6 @@ static void dpu_hw_dsc_config_thresh(struct dpu_hw_dsc 
*hw_dsc,
 
 static void dpu_hw_dsc_bind_pingpong_blk(
struct dpu_hw_dsc *hw_dsc,
-   bool enable,
const enum dpu_pingpong pp)
 {
struct dpu_hw_blk_reg_map *c = _dsc->hw;
@@ -166,14 +165,15 @@ static void dpu_hw_dsc_bind_pingpong_blk(
 
dsc_ctl_offset = DSC_CTL(hw_dsc->idx);
 
-   if (enable)
+   if (pp)
mux_cfg = (pp - PINGPONG_0) & 0x7;
 
-   DRM_DEBUG_KMS("%s dsc:%d %s pp:%d\n",
-   enable ? "Binding" : "Unbinding",
-   hw_dsc->idx - DSC_0,
-   enable ? "to" : "from",
-   pp - PINGPONG_0);
+   if (pp)
+   DRM_DEBUG_KMS("Binding dsc:%d to pp:%d\n",
+ hw_dsc->idx - DSC_0, pp - PINGPONG_0);
+   else
+   DRM_DEBUG_KMS("Unbinding dsc:%d from any pp\n",
+ hw_dsc->idx - DSC_0);
 
DPU_REG_WRITE(c, dsc_ctl_offset, mux_cfg);
 }
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h
index 287ec5f..138080a 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h
@@ -44,7 +44,6 @@ struct dpu_hw_dsc_ops {
  struct drm_dsc_config *dsc);
 
void (*dsc_bind_pingpong_blk)(struct dpu_hw_dsc *hw_dsc,
- bool enable,
  enum dpu_pingpong pp);
 };
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
index 1913a19..02a0f48 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
@@ -191,7 +191,8 @@ enum dpu_dsc {
 };
 
 enum dpu_pingpong {
-   PINGPONG_0 = 1,
+   PINGPONG_NONE,
+   PINGPONG_0,
PINGPONG_1,
PINGPONG_2,
PINGPONG_3,
-- 
2.7.4

[PATCH v14 09/10] drm/msm/dpu: add DSC 1.2 hw blocks for relevant chipsets

From: Abhinav Kumar 

Add DSC 1.2 hardware blocks to the catalog with necessary sub-block and
feature flag information.  Each display compression engine (DCE) contains
dual DSC encoders so both share same base address but with its own
different sub block address.

changes in v4:
-- delete DPU_DSC_HW_REV_1_1
-- re arrange sc8280xp_dsc[]

changes in v4:
-- fix checkpatch warning

changes in v10:
-- remove hard slice from commit text
-- replace DPU_DSC_NATIVE_422_EN with DPU_DSC_NATIVE_42x_EN
-- change DSC_BLK_1_2 .len from 0x100 to 0x29c

changes in v11:
-- remove comment at DSC_BLK_1_2 marco

Signed-off-by: Abhinav Kumar 
Signed-off-by: Kuogee Hsieh 
Reviewed-by: Dmitry Baryshkov 
Reviewed-by: Marijn Suijten 
---
 .../gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h   | 14 ++
 .../gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h   |  7 +++
 .../gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 16 
 .../gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h   | 14 ++
 .../gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h   | 14 ++
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c   | 20 +++-
 6 files changed, 84 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h 
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
index 500cfd0..d90486f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
@@ -153,6 +153,18 @@ static const struct dpu_merge_3d_cfg sm8350_merge_3d[] = {
MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x5),
 };
 
+/*
+ * NOTE: Each display compression engine (DCE) contains dual hard
+ * slice DSC encoders so both share same base address but with
+ * its own different sub block address.
+ */
+static const struct dpu_dsc_cfg sm8350_dsc[] = {
+   DSC_BLK_1_2("dce_0_0", DSC_0, 0x8, 0x29c, 0, dsc_sblk_0),
+   DSC_BLK_1_2("dce_0_1", DSC_1, 0x8, 0x29c, 0, dsc_sblk_1),
+   DSC_BLK_1_2("dce_1_0", DSC_2, 0x81000, 0x29c, 
BIT(DPU_DSC_NATIVE_42x_EN), dsc_sblk_0),
+   DSC_BLK_1_2("dce_1_1", DSC_3, 0x81000, 0x29c, 
BIT(DPU_DSC_NATIVE_42x_EN), dsc_sblk_1),
+};
+
 static const struct dpu_intf_cfg sm8350_intf[] = {
INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, 
MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK,
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
@@ -215,6 +227,8 @@ const struct dpu_mdss_cfg dpu_sm8350_cfg = {
.dspp = sm8350_dspp,
.pingpong_count = ARRAY_SIZE(sm8350_pp),
.pingpong = sm8350_pp,
+   .dsc_count = ARRAY_SIZE(sm8350_dsc),
+   .dsc = sm8350_dsc,
.merge_3d_count = ARRAY_SIZE(sm8350_merge_3d),
.merge_3d = sm8350_merge_3d,
.intf_count = ARRAY_SIZE(sm8350_intf),
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h 
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
index 5646713..52609b8 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
@@ -93,6 +93,11 @@ static const struct dpu_pingpong_cfg sc7280_pp[] = {
PP_BLK_DITHER("pingpong_3", PINGPONG_3, 0x6c000, 0, sc7280_pp_sblk, -1, 
-1),
 };
 
+/* NOTE: sc7280 only has one DSC hard slice encoder */
+static const struct dpu_dsc_cfg sc7280_dsc[] = {
+   DSC_BLK_1_2("dce_0_0", DSC_0, 0x8, 0x29c, 
BIT(DPU_DSC_NATIVE_42x_EN), dsc_sblk_0),
+};
+
 static const struct dpu_intf_cfg sc7280_intf[] = {
INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, 
MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK,
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
@@ -149,6 +154,8 @@ const struct dpu_mdss_cfg dpu_sc7280_cfg = {
.mixer = sc7280_lm,
.pingpong_count = ARRAY_SIZE(sc7280_pp),
.pingpong = sc7280_pp,
+   .dsc_count = ARRAY_SIZE(sc7280_dsc),
+   .dsc = sc7280_dsc,
.intf_count = ARRAY_SIZE(sc7280_intf),
.intf = sc7280_intf,
.vbif_count = ARRAY_SIZE(sdm845_vbif),
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h 
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
index 808aacd..a84cf36 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
@@ -141,6 +141,20 @@ static const struct dpu_merge_3d_cfg sc8280xp_merge_3d[] = 
{
MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x5),
 };
 
+/*
+ * NOTE: Each display compression engine (DCE) contains dual hard
+ * slice DSC encoders so both share same base address but with
+ * its own different sub block address.
+ */
+static const struct dpu_dsc_cfg sc8280xp_dsc[] = {
+   DSC_BLK_1_2("dce_0_0", DSC_0, 0x8, 0x29c, 0, dsc_sblk_0),
+   DSC_BLK_1_2("dce_0_1", DSC_1, 0x8, 0x29c, 0, dsc_sblk_1),
+   DSC_BLK_1_2("dce_1_0", DSC_2, 0x81000, 0x29c, 
BIT(DPU_DSC_NATIVE_42x_EN), dsc_sblk_0),
+   DSC_BLK_1_2("dce_1_1", DSC_3, 0x81000,

[PATCH v14 06/10] drm/msm/dpu: add support for DSC encoder v1.2 engine

Add support for DSC 1.2 by providing the necessary hooks to program
the DPU DSC 1.2 encoder.

Changes in v3:
-- fixed kernel test rebot report that "__iomem *off" is declared but not
   used at dpu_hw_dsc_config_1_2()
-- unrolling thresh loops

Changes in v4:
-- delete DPU_DSC_HW_REV_1_1
-- delete off and used real register name directly

Changes in v7:
-- replace offset with sblk->enc.base
-- replace ss with slice

Changes in v8:
-- fixed checkpatch warning

Changes in v9:
-- replaced __dsc_calc_ob_max_addr() with __dsc_calc_output_buf_max_addr()
-- replaced variable num_ss with num_softslice
-- remove inline from function  declaration

changes in v10:
-- rewording text of changes in v9
-- replace DPU_DSC_NATIVE_422_EN with DPU_DSC_NATIVE_42x_EN
-- replace drm_dsc_calculate_flatness_det_thresh() with 
drm_dsc_flatness_det_thresh()

Signed-off-by: Kuogee Hsieh 
Reviewed-by: Dmitry Baryshkov 
---
 drivers/gpu/drm/msm/Makefile   |   1 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h |  31 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h |  14 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c | 387 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c |   7 +-
 5 files changed, 436 insertions(+), 4 deletions(-)
 create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index 7274c412..4c7195af2 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -65,6 +65,7 @@ msm-$(CONFIG_DRM_MSM_DPU) += \
disp/dpu1/dpu_hw_catalog.o \
disp/dpu1/dpu_hw_ctl.o \
disp/dpu1/dpu_hw_dsc.o \
+   disp/dpu1/dpu_hw_dsc_1_2.o \
disp/dpu1/dpu_hw_interrupts.o \
disp/dpu1/dpu_hw_intf.o \
disp/dpu1/dpu_hw_lm.o \
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 83854e8..11610f7 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
- * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights 
reserved.
  * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
  */
 
@@ -244,12 +244,18 @@ enum {
 };
 
 /**
- * DSC features
+ * DSC sub-blocks/features
  * @DPU_DSC_OUTPUT_CTRL   Configure which PINGPONG block gets
  *the pixel output from this DSC.
+ * @DPU_DSC_HW_REV_1_2DSC block supports DSC 1.1 and 1.2
+ * @DPU_DSC_NATIVE_42x_EN Supports NATIVE_422_EN and NATIVE_420_EN encoding
+ * @DPU_DSC_MAX
  */
 enum {
DPU_DSC_OUTPUT_CTRL = 0x1,
+   DPU_DSC_HW_REV_1_2,
+   DPU_DSC_NATIVE_42x_EN,
+   DPU_DSC_MAX
 };
 
 /**
@@ -306,6 +312,14 @@ struct dpu_pp_blk {
 };
 
 /**
+ * struct dpu_dsc_blk - DSC Encoder sub-blk information
+ * @info:   HW register and features supported by this sub-blk
+ */
+struct dpu_dsc_blk {
+   DPU_HW_SUBBLK_INFO;
+};
+
+/**
  * enum dpu_qos_lut_usage - define QoS LUT use cases
  */
 enum dpu_qos_lut_usage {
@@ -452,6 +466,16 @@ struct dpu_pingpong_sub_blks {
 };
 
 /**
+ * struct dpu_dsc_sub_blks - DSC sub-blks
+ * @enc: DSC encoder sub-block
+ * @ctl: DSC controller sub-block
+ */
+struct dpu_dsc_sub_blks {
+   struct dpu_dsc_blk enc;
+   struct dpu_dsc_blk ctl;
+};
+
+/**
  * dpu_clk_ctrl_type - Defines top level clock control signals
  */
 enum dpu_clk_ctrl_type {
@@ -605,10 +629,13 @@ struct dpu_merge_3d_cfg  {
  * struct dpu_dsc_cfg - information of DSC blocks
  * @id enum identifying this block
  * @base   register offset of this block
+ * @len:   length of hardware block
  * @features   bit mask identifying sub-blocks/features
+ * @sblk:  sub-blocks information
  */
 struct dpu_dsc_cfg {
DPU_HW_BLK_INFO;
+   const struct dpu_dsc_sub_blks *sblk;
 };
 
 /**
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h
index 138080a..d5b597a 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h
@@ -1,5 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
-/* Copyright (c) 2020-2022, Linaro Limited */
+/*
+ * Copyright (c) 2020-2022, Linaro Limited
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved
+ */
 
 #ifndef _DPU_HW_DSC_H
 #define _DPU_HW_DSC_H
@@ -69,6 +72,15 @@ struct dpu_hw_dsc *dpu_hw_dsc_init(const struct dpu_dsc_cfg 
*cfg,
void __iomem *addr);
 
 /**
+ * dpu_hw_dsc_init_1_2() - initializes the v1.2 DSC hw driver object
+ * @cfg:  DSC catalog entry for which driver object is required
+ * @addr: Mapped register io address of MDP
+ * Returns: Error code or allocated dpu_hw_dsc context
+ */
+struct dpu_hw_dsc *dpu_hw_dsc_init_1_2(const struct

[PATCH v14 08/10] drm/msm/dpu: separate DSC flush update out of interface

Currently DSC flushing happens during interface configuration at
dpu_hw_ctl_intf_cfg_v1(). Separate DSC flush away from
dpu_hw_ctl_intf_cfg_v1() by adding dpu_hw_ctl_update_pending_flush_dsc_v1()
to handle both per-DSC engine and DSC flush bits at same time to make it
consistent with the location of flush programming of other DPU sub-blocks.

Changes in v10:
-- rewording commit text
-- pass ctl directly instead of dpu_enc to dsc_pipe_cfg()
-- ctx->pending_dsc_flush_mask = 0;

Changes in v11:
-- add Fixes tag

Changes in v12:
-- move dsc parameter to next line at dpu_encoder_dsc_pipe_cfg()

Changes in v14:
-- Fixes tag had been move to 1st patch of this series

Signed-off-by: Kuogee Hsieh 
Reviewed-by: Dmitry Baryshkov 
Reviewed-by: Marijn Suijten 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 10 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c  | 23 +--
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h  | 11 +++
 3 files changed, 36 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index ffa6f04..7fca09e 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -1834,7 +1834,8 @@ dpu_encoder_dsc_initial_line_calc(struct drm_dsc_config 
*dsc,
return DIV_ROUND_UP(total_pixels, dsc->slice_width);
 }
 
-static void dpu_encoder_dsc_pipe_cfg(struct dpu_hw_dsc *hw_dsc,
+static void dpu_encoder_dsc_pipe_cfg(struct dpu_hw_ctl *ctl,
+struct dpu_hw_dsc *hw_dsc,
 struct dpu_hw_pingpong *hw_pp,
 struct drm_dsc_config *dsc,
 u32 common_mode,
@@ -1854,6 +1855,9 @@ static void dpu_encoder_dsc_pipe_cfg(struct dpu_hw_dsc 
*hw_dsc,
 
if (hw_pp->ops.enable_dsc)
hw_pp->ops.enable_dsc(hw_pp);
+
+   if (ctl->ops.update_pending_flush_dsc)
+   ctl->ops.update_pending_flush_dsc(ctl, hw_dsc->idx);
 }
 
 static void dpu_encoder_prep_dsc(struct dpu_encoder_virt *dpu_enc,
@@ -1861,6 +1865,7 @@ static void dpu_encoder_prep_dsc(struct dpu_encoder_virt 
*dpu_enc,
 {
/* coding only for 2LM, 2enc, 1 dsc config */
struct dpu_encoder_phys *enc_master = dpu_enc->cur_master;
+   struct dpu_hw_ctl *ctl = enc_master->hw_ctl;
struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC];
struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
int this_frame_slices;
@@ -1898,7 +1903,8 @@ static void dpu_encoder_prep_dsc(struct dpu_encoder_virt 
*dpu_enc,
initial_lines = dpu_encoder_dsc_initial_line_calc(dsc, enc_ip_w);
 
for (i = 0; i < MAX_CHANNELS_PER_ENC; i++)
-   dpu_encoder_dsc_pipe_cfg(hw_dsc[i], hw_pp[i], dsc, 
dsc_common_mode, initial_lines);
+   dpu_encoder_dsc_pipe_cfg(ctl, hw_dsc[i], hw_pp[i],
+dsc, dsc_common_mode, initial_lines);
 }
 
 void dpu_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
index 64c21e0..ad6983e 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
@@ -103,6 +103,7 @@ static inline void dpu_hw_ctl_clear_pending_flush(struct 
dpu_hw_ctl *ctx)
ctx->pending_intf_flush_mask = 0;
ctx->pending_wb_flush_mask = 0;
ctx->pending_merge_3d_flush_mask = 0;
+   ctx->pending_dsc_flush_mask = 0;
 
memset(ctx->pending_dspp_flush_mask, 0,
sizeof(ctx->pending_dspp_flush_mask));
@@ -142,6 +143,11 @@ static inline void dpu_hw_ctl_trigger_flush_v1(struct 
dpu_hw_ctl *ctx)
CTL_DSPP_n_FLUSH(dspp - DSPP_0),
ctx->pending_dspp_flush_mask[dspp - DSPP_0]);
}
+
+   if (ctx->pending_flush_mask & BIT(DSC_IDX))
+   DPU_REG_WRITE(>hw, CTL_DSC_FLUSH,
+ ctx->pending_dsc_flush_mask);
+
DPU_REG_WRITE(>hw, CTL_FLUSH, ctx->pending_flush_mask);
 }
 
@@ -288,6 +294,13 @@ static void 
dpu_hw_ctl_update_pending_flush_merge_3d_v1(struct dpu_hw_ctl *ctx,
ctx->pending_flush_mask |= BIT(MERGE_3D_IDX);
 }
 
+static void dpu_hw_ctl_update_pending_flush_dsc_v1(struct dpu_hw_ctl *ctx,
+  enum dpu_dsc dsc_num)
+{
+   ctx->pending_dsc_flush_mask |= BIT(dsc_num - DSC_0);
+   ctx->pending_flush_mask |= BIT(DSC_IDX);
+}
+
 static void dpu_hw_ctl_update_pending_flush_dspp(struct dpu_hw_ctl *ctx,
enum dpu_dspp dspp, u32 dspp_sub_blk)
 {
@@ -505,9 +518,6 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx,
if ((test_bit(DPU_CTL_VM_CFG, >caps->features)))
mode_sel = CTL_DEFAULT_GROUP_ID  << 28;
 
-   if (cfg->dsc)
-   DPU_REG_WRITE(>hw, CTL_DSC_FLUSH,

[PATCH v14 10/10] drm/msm/dpu: Tear down DSC datapath on encoder cleanup

Unset DSC_ACTIVE bit at dpu_hw_ctl_reset_intf_cfg_v1(),
dpu_encoder_unprep_dsc() and dpu_encoder_dsc_pipe_clr() functions
to tear down DSC data path if DSC data path was setup previous.

Changes in V10:
-- pass ctl directly instead of dpu_enc to dsc_pipe_cfg()
-- move both dpu_encoder_unprep_dsc() and dpu_encoder_dsc_pipe_clr() to above 
phys_cleanup()

Signed-off-by: Kuogee Hsieh 
Reviewed-by: Dmitry Baryshkov 
Reviewed-by: Marijn Suijten 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 39 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c  |  7 ++
 2 files changed, 46 insertions(+)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 7fca09e..3b416e1 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -2036,6 +2036,41 @@ static void dpu_encoder_helper_reset_mixers(struct 
dpu_encoder_phys *phys_enc)
}
 }
 
+static void dpu_encoder_dsc_pipe_clr(struct dpu_hw_ctl *ctl,
+struct dpu_hw_dsc *hw_dsc,
+struct dpu_hw_pingpong *hw_pp)
+{
+   if (hw_dsc->ops.dsc_disable)
+   hw_dsc->ops.dsc_disable(hw_dsc);
+
+   if (hw_pp->ops.disable_dsc)
+   hw_pp->ops.disable_dsc(hw_pp);
+
+   if (hw_dsc->ops.dsc_bind_pingpong_blk)
+   hw_dsc->ops.dsc_bind_pingpong_blk(hw_dsc, PINGPONG_NONE);
+
+   if (ctl->ops.update_pending_flush_dsc)
+   ctl->ops.update_pending_flush_dsc(ctl, hw_dsc->idx);
+}
+
+static void dpu_encoder_unprep_dsc(struct dpu_encoder_virt *dpu_enc)
+{
+   /* coding only for 2LM, 2enc, 1 dsc config */
+   struct dpu_encoder_phys *enc_master = dpu_enc->cur_master;
+   struct dpu_hw_ctl *ctl = enc_master->hw_ctl;
+   struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC];
+   struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
+   int i;
+
+   for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
+   hw_pp[i] = dpu_enc->hw_pp[i];
+   hw_dsc[i] = dpu_enc->hw_dsc[i];
+
+   if (hw_pp[i] && hw_dsc[i])
+   dpu_encoder_dsc_pipe_clr(ctl, hw_dsc[i], hw_pp[i]);
+   }
+}
+
 void dpu_encoder_helper_phys_cleanup(struct dpu_encoder_phys *phys_enc)
 {
struct dpu_hw_ctl *ctl = phys_enc->hw_ctl;
@@ -2086,8 +2121,12 @@ void dpu_encoder_helper_phys_cleanup(struct 
dpu_encoder_phys *phys_enc)
phys_enc->hw_pp->merge_3d->idx);
}
 
+   if (dpu_enc->dsc)
+   dpu_encoder_unprep_dsc(dpu_enc);
+
intf_cfg.stream_sel = 0; /* Don't care value for video mode */
intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc);
+   intf_cfg.dsc = dpu_encoder_helper_get_dsc(phys_enc);
 
if (phys_enc->hw_intf)
intf_cfg.intf = phys_enc->hw_intf->idx;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
index ad6983e..e28e8f8 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
@@ -582,6 +582,7 @@ static void dpu_hw_ctl_reset_intf_cfg_v1(struct dpu_hw_ctl 
*ctx,
u32 intf_active = 0;
u32 wb_active = 0;
u32 merge3d_active = 0;
+   u32 dsc_active;
 
/*
 * This API resets each portion of the CTL path namely,
@@ -611,6 +612,12 @@ static void dpu_hw_ctl_reset_intf_cfg_v1(struct dpu_hw_ctl 
*ctx,
wb_active &= ~BIT(cfg->wb - WB_0);
DPU_REG_WRITE(c, CTL_WB_ACTIVE, wb_active);
}
+
+   if (cfg->dsc) {
+   dsc_active = DPU_REG_READ(c, CTL_DSC_ACTIVE);
+   dsc_active &= ~cfg->dsc;
+   DPU_REG_WRITE(c, CTL_DSC_ACTIVE, dsc_active);
+   }
 }
 
 static void dpu_hw_ctl_set_fetch_pipe_active(struct dpu_hw_ctl *ctx,
-- 
2.7.4

[PATCH v14 04/10] drm/msm/dpu: Guard PINGPONG DSC ops behind DPU_PINGPONG_DSC bit

DPU < 7.0.0 has DPU_PINGPONG_DSC feature bit set to indicate it requires
both dpu_hw_pp_setup_dsc() and dpu_hw_pp_dsc_{enable,disable}() to be
executed to complete DSC configuration if DSC hardware block is present.
Hence test DPU_PINGPONG_DSC feature bit and assign DSC related functions
to the ops of PINGPONG block accordingly if DPU_PINGPONG_DSC bit is set.

Changes in v6:
-- split patches, this patch has function handles DPU_PINGPONG_DSC bit

Changes in v9:
-- the original code of assigning dsc related functions to the ops of
   pingpong block without testing the DPU_PINGPONG_DSC feature bit was
   restored back due to rebase error which defeat the purpose of this
   patch. Remove those error code.

Changes in v10:
-- change commit title
-- correct texts at changes in v9

Changes in v12:
-- fixed length too long at Changes in v9

Signed-off-by: Kuogee Hsieh 
Reviewed-by: Dmitry Baryshkov 
Reviewed-by: Marijn Suijten 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c | 9 ++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
index 79e4576..437d9e6 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
@@ -291,9 +291,12 @@ static void _setup_pingpong_ops(struct dpu_hw_pingpong *c,
c->ops.get_line_count = dpu_hw_pp_get_line_count;
c->ops.disable_autorefresh = dpu_hw_pp_disable_autorefresh;
}
-   c->ops.setup_dsc = dpu_hw_pp_setup_dsc;
-   c->ops.enable_dsc = dpu_hw_pp_dsc_enable;
-   c->ops.disable_dsc = dpu_hw_pp_dsc_disable;
+
+   if (test_bit(DPU_PINGPONG_DSC, )) {
+   c->ops.setup_dsc = dpu_hw_pp_setup_dsc;
+   c->ops.enable_dsc = dpu_hw_pp_dsc_enable;
+   c->ops.disable_dsc = dpu_hw_pp_dsc_disable;
+   }
 
if (test_bit(DPU_PINGPONG_DITHER, ))
c->ops.setup_dither = dpu_hw_pp_setup_dither;
-- 
2.7.4

[PATCH v14 01/10] drm/msm/dpu: set DSC flush bit correctly at MDP CTL flush register

The CTL_FLUSH register should be programmed with the 22th bit
(DSC_IDX) to flush the DSC hardware blocks, not the literal value of
22 (which corresponds to flushing VIG1, VIG2 and RGB1 instead).

Changes in V12:
-- split this patch out of "separate DSC flush update out of interface"

Changes in V13:
-- rewording the commit text

Changes in V14:
-- drop 'DSC" from "The DSC CTL_FLUSH register" at commit text

Fixes: 77f6da90487c ("drm/msm/disp/dpu1: Add DSC support in hw_ctl")
Signed-off-by: Kuogee Hsieh 
Reviewed-by: Marijn Suijten 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
index 4f7cfa9..69d0ea2 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
@@ -525,7 +525,7 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx,
DPU_REG_WRITE(c, CTL_MERGE_3D_ACTIVE,
  BIT(cfg->merge_3d - MERGE_3D_0));
if (cfg->dsc) {
-   DPU_REG_WRITE(>hw, CTL_FLUSH, DSC_IDX);
+   DPU_REG_WRITE(>hw, CTL_FLUSH, BIT(DSC_IDX));
DPU_REG_WRITE(c, CTL_DSC_ACTIVE, cfg->dsc);
}
 }
-- 
2.7.4

[PATCH v14 02/10] drm/msm/dpu: add DSC blocks to the catalog of MSM8998 and SC8180X

From: Abhinav Kumar 

Some platforms have DSC blocks which have not been declared in the catalog.
Complete DSC 1.1 support for all platforms by adding the missing blocks to
MSM8998 and SC8180X.

Changes in v9:
-- add MSM8998 and SC8180x to commit title

Changes in v10:
-- fix grammar at commit text

Changes in v12:
-- fix "titil" with "title" at changes in v9

Changes in v14:
-- "dsc" tp "DSC" at commit title

Signed-off-by: Abhinav Kumar 
Reviewed-by: Dmitry Baryshkov 
Reviewed-by: Marijn Suijten 
---
 drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h |  7 +++
 drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 11 +++
 2 files changed, 18 insertions(+)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h 
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
index c0dd477..521cfd5 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
@@ -126,6 +126,11 @@ static const struct dpu_pingpong_cfg msm8998_pp[] = {
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)),
 };
 
+static const struct dpu_dsc_cfg msm8998_dsc[] = {
+   DSC_BLK("dsc_0", DSC_0, 0x8, 0),
+   DSC_BLK("dsc_1", DSC_1, 0x80400, 0),
+};
+
 static const struct dpu_dspp_cfg msm8998_dspp[] = {
DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_MSM8998_MASK,
 _dspp_sblk),
@@ -199,6 +204,8 @@ const struct dpu_mdss_cfg dpu_msm8998_cfg = {
.dspp = msm8998_dspp,
.pingpong_count = ARRAY_SIZE(msm8998_pp),
.pingpong = msm8998_pp,
+   .dsc_count = ARRAY_SIZE(msm8998_dsc),
+   .dsc = msm8998_dsc,
.intf_count = ARRAY_SIZE(msm8998_intf),
.intf = msm8998_intf,
.vbif_count = ARRAY_SIZE(msm8998_vbif),
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h 
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
index e8057a1..fec1665 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
@@ -142,6 +142,15 @@ static const struct dpu_merge_3d_cfg sc8180x_merge_3d[] = {
MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x83200),
 };
 
+static const struct dpu_dsc_cfg sc8180x_dsc[] = {
+   DSC_BLK("dsc_0", DSC_0, 0x8, BIT(DPU_DSC_OUTPUT_CTRL)),
+   DSC_BLK("dsc_1", DSC_1, 0x80400, BIT(DPU_DSC_OUTPUT_CTRL)),
+   DSC_BLK("dsc_2", DSC_2, 0x80800, BIT(DPU_DSC_OUTPUT_CTRL)),
+   DSC_BLK("dsc_3", DSC_3, 0x80c00, BIT(DPU_DSC_OUTPUT_CTRL)),
+   DSC_BLK("dsc_4", DSC_4, 0x81000, BIT(DPU_DSC_OUTPUT_CTRL)),
+   DSC_BLK("dsc_5", DSC_5, 0x81400, BIT(DPU_DSC_OUTPUT_CTRL)),
+};
+
 static const struct dpu_intf_cfg sc8180x_intf[] = {
INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, 
MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK,
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
@@ -206,6 +215,8 @@ const struct dpu_mdss_cfg dpu_sc8180x_cfg = {
.mixer = sc8180x_lm,
.pingpong_count = ARRAY_SIZE(sc8180x_pp),
.pingpong = sc8180x_pp,
+   .dsc_count = ARRAY_SIZE(sc8180x_dsc),
+   .dsc = sc8180x_dsc,
.merge_3d_count = ARRAY_SIZE(sc8180x_merge_3d),
.merge_3d = sc8180x_merge_3d,
.intf_count = ARRAY_SIZE(sc8180x_intf),
-- 
2.7.4

[PATCH v14 03/10] drm/msm/dpu: add DPU_PINGPONG_DSC feature bit for DPU < 7.0.0

DPU < 7.0.0 requires the PINGPONG block to be involved during
DSC setting up. Since DPU >= 7.0.0, enabling and starting the DSC
encoder engine was moved to INTF with the help of the flush mechanism.
Add a DPU_PINGPONG_DSC feature bit to restrict the availability of
dpu_hw_pp_setup_dsc() and dpu_hw_pp_dsc_{enable,disable}() on the
PINGPONG block to DPU < 7.0.0 hardware, as the registers are not
available on DPU 7.0.0 and higher anymore.
Add DPU_PINGPONG_DSC to PINGPONG_SDM845_MASK, PINGPONG_SDM845_TE2_MASK
and PINGPONG_SM8150_MASK which is used for all DPU < 7.0 chipsets.

changes in v6:
-- split patches and rearrange to keep catalog related files at this patch

changes in v7:
-- rewording commit text as suggested at review comments

changes in v9:
-- delete BIT(DPU_PINGPONG_DSC) from PINGPONG_SDM845_TE2_MASK

changes in v10:
-- correct order of commit text

Signed-off-by: Kuogee Hsieh 
Reviewed-by: Dmitry Baryshkov 
Reviewed-by: Marijn Suijten 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 4 ++--
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 4 +++-
 2 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 82b58c6..f2a1535 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -76,13 +76,13 @@
(BIT(DPU_DIM_LAYER) | BIT(DPU_MIXER_COMBINED_ALPHA))
 
 #define PINGPONG_SDM845_MASK \
-   (BIT(DPU_PINGPONG_DITHER) | BIT(DPU_PINGPONG_TE))
+   (BIT(DPU_PINGPONG_DITHER) | BIT(DPU_PINGPONG_TE) | 
BIT(DPU_PINGPONG_DSC))
 
 #define PINGPONG_SDM845_TE2_MASK \
(PINGPONG_SDM845_MASK | BIT(DPU_PINGPONG_TE2))
 
 #define PINGPONG_SM8150_MASK \
-   (BIT(DPU_PINGPONG_DITHER))
+   (BIT(DPU_PINGPONG_DITHER) | BIT(DPU_PINGPONG_DSC))
 
 #define CTL_SC7280_MASK \
(BIT(DPU_CTL_ACTIVE_CFG) | \
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 6ee48f0..83854e8 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -144,7 +144,8 @@ enum {
  * @DPU_PINGPONG_TE2Additional tear check block for split pipes
  * @DPU_PINGPONG_SPLIT  PP block supports split fifo
  * @DPU_PINGPONG_SLAVE  PP block is a suitable slave for split fifo
- * @DPU_PINGPONG_DITHER,Dither blocks
+ * @DPU_PINGPONG_DITHER Dither blocks
+ * @DPU_PINGPONG_DSCPP block supports DSC
  * @DPU_PINGPONG_MAX
  */
 enum {
@@ -153,6 +154,7 @@ enum {
DPU_PINGPONG_SPLIT,
DPU_PINGPONG_SLAVE,
DPU_PINGPONG_DITHER,
+   DPU_PINGPONG_DSC,
DPU_PINGPONG_MAX
 };
 
-- 
2.7.4

[PATCH v14 00/10] add DSC 1.2 dpu supports

This series adds the DPU side changes to support DSC 1.2 encoder. This
was validated with both DSI DSC 1.2 panel and DP DSC 1.2 monitor.
The DSI and DP parts will be pushed later on top of this change.
This seriel is rebase on [1], [2] and catalog fixes from rev-4 of [3].

[1]: https://patchwork.freedesktop.org/series/116851/
[2]: https://patchwork.freedesktop.org/series/116615/
[3]: https://patchwork.freedesktop.org/series/112332/

Abhinav Kumar (2):
  drm/msm/dpu: add DSC blocks to the catalog of MSM8998 and SC8180X
  drm/msm/dpu: add DSC 1.2 hw blocks for relevant chipsets

Kuogee Hsieh (8):
  drm/msm/dpu: set DSC flush bit correctly at MDP CTL flush register
  drm/msm/dpu: add DPU_PINGPONG_DSC feature bit for DPU < 7.0.0
  drm/msm/dpu: Guard PINGPONG DSC ops behind DPU_PINGPONG_DSC bit
  drm/msm/dpu: Introduce PINGPONG_NONE to disconnect DSC from PINGPONG
  drm/msm/dpu: add support for DSC encoder v1.2 engine
  drm/msm/dpu: always clear every individual pending flush mask
  drm/msm/dpu: separate DSC flush update out of interface
  drm/msm/dpu: Tear down DSC datapath on encoder cleanup

 drivers/gpu/drm/msm/Makefile   |   1 +
 .../drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h|   7 +
 .../drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h|  11 +
 .../gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h |  14 +
 .../gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h |   7 +
 .../drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h   |  16 +
 .../gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h |  14 +
 .../gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h |  14 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c|  51 ++-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c |  24 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h |  35 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c |  33 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h |  11 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c |  14 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h |  15 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c | 387 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h|   3 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c|   9 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c |   7 +-
 19 files changed, 644 insertions(+), 29 deletions(-)
 create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

-- 
2.7.4

Re: [PATCH 1/4] fbdev: imsttfb: Fix error handling in init_imstt()

2023-05-25 Thread Helge Deller


On 5/25/23 07:33, Markus Elfring wrote:

The return value was overlooked from a call of
the function “fb_alloc_cmap”.

* Thus use a corresponding error check.

* Add two jump targets so that a bit of exception handling
    can be better reused at the end of this function.

…

+++ b/drivers/video/fbdev/imsttfb.c

…

@@ -1452,17 +1452,25 @@ static int init_imstt(struct fb_info *info)
     FBINFO_HWACCEL_FILLRECT |
     FBINFO_HWACCEL_YPAN;

-    fb_alloc_cmap(>cmap, 0, 0);
+    ret = fb_alloc_cmap(>cmap, 0, 0);
+    if (ret)
+    goto release_framebuffer;

   if (register_framebuffer(info) < 0) {
-    framebuffer_release(info);
-    return -ENODEV;
+    fb_dealloc_cmap(>cmap);
+    goto e_nodev;
   }

   tmp = (read_reg_le32(par->dc_regs, SSTATUS) & 0x0f00) >> 8;
   fb_info(info, "%s frame buffer; %uMB vram; chip version %u\n",
   info->fix.id, info->fix.smem_len >> 20, tmp);
   return 0;
+
+e_nodev:
+    ret = -ENODEV;


I think the return value isn't checked at all, so you could
simply return below "-ENODEV" for all cases (instead of "return ret").
Then you don't need the e_nodev label and can simplify the flow.


Can it be helpful to distinguish involved error codes better?


No.

Helge

Re: [PATCH v2 2/6] drm/msm/a6xx: Explain CP_PROTECT_CNTL writes in a6xx_set_cp_protect

2023-05-25 Thread Rob Clark

On Fri, May 19, 2023 at 6:29 AM Konrad Dybcio  wrote:
>
> We have the necessary information, so explain which bit does what.
>
> Signed-off-by: Konrad Dybcio 
> ---
>  drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 7 ---
>  1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c 
> b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> index 9fb214f150dd..deed42675fe2 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> @@ -771,9 +771,10 @@ static void a6xx_set_cp_protect(struct msm_gpu *gpu)
> }
>
> /*
> -* Enable access protection to privileged registers, fault on an 
> access
> -* protect violation and select the last span to protect from the 
> start
> -* address all the way to the end of the register address space
> +* BIT(0) - Enable access protection to privileged registers
> +* BIT(1) - Enable fault on an access protect violation
> +* BIT(3) - Select the last span to protect from the start
> +*  address all the way to the end of the register address 
> space

Even better would be to give these bitfields names in the xml, which
also gets you more meaningful decoding.  We've been better about not
open-coding a lot of stuff on the mesa side, but it is a bit easier
with header generation integrated into the build..  but less
open-coding on the kernel side is still a noble goal

BR,
-R

>  */
> gpu_write(gpu, REG_A6XX_CP_PROTECT_CNTL, BIT(0) | BIT(1) | BIT(3));
>
>
> --
> 2.40.1
>

[PATCH 21/33] drm/amdkfd: add debug trap enabled flag to tma

From: Jay Cornwall 

Trap handler behavior will differ when a debugger is attached.

Make the debug trap flag available in the trap handler TMA.
Update it when the debug trap ioctl is invoked.

Signed-off-by: Jay Cornwall 
Reviewed-by: Felix Kuehling 
Signed-off-by: Jonathan Kim 
Reviewed-by: Felix Kuehling 
---
 drivers/gpu/drm/amd/amdkfd/kfd_debug.c   | 11 +++
 drivers/gpu/drm/amd/amdkfd/kfd_priv.h|  2 ++
 drivers/gpu/drm/amd/amdkfd/kfd_process.c | 15 +++
 3 files changed, 28 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_debug.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_debug.c
index a19c21d04438..17e8e9edccbf 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_debug.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_debug.c
@@ -256,6 +256,8 @@ void kfd_dbg_trap_deactivate(struct kfd_process *target, 
bool unwind, int unwind
if (unwind && i == unwind_count)
break;
 
+   kfd_process_set_trap_debug_flag(>qpd, false);
+
/* GFX off is already disabled by debug activate if not RLC 
restore supported. */
if (kfd_dbg_is_rlc_restore_supported(pdd->dev))
amdgpu_gfx_off_ctrl(pdd->dev->adev, false);
@@ -351,6 +353,15 @@ int kfd_dbg_trap_activate(struct kfd_process *target)
if (kfd_dbg_is_rlc_restore_supported(pdd->dev))
amdgpu_gfx_off_ctrl(pdd->dev->adev, true);
 
+   /*
+* Setting the debug flag in the trap handler requires that the 
TMA has been
+* allocated, which occurs during CWSR initialization.
+* In the event that CWSR has not been initialized at this 
point, setting the
+* flag will be called again during CWSR initialization if the 
target process
+* is still debug enabled.
+*/
+   kfd_process_set_trap_debug_flag(>qpd, true);
+
if (!pdd->dev->kfd->shared_resources.enable_mes)
r = debug_refresh_runlist(pdd->dev->dqm);
else
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h 
b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
index 4b80f74b9de0..a02fb939614a 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
@@ -1157,6 +1157,8 @@ int kfd_init_apertures(struct kfd_process *process);
 void kfd_process_set_trap_handler(struct qcm_process_device *qpd,
  uint64_t tba_addr,
  uint64_t tma_addr);
+void kfd_process_set_trap_debug_flag(struct qcm_process_device *qpd,
+bool enabled);
 
 /* CWSR initialization */
 int kfd_process_init_cwsr_apu(struct kfd_process *process, struct file *filep);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
index 8bfd0c91fb92..2a60c630ab5d 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
@@ -1309,6 +1309,8 @@ int kfd_process_init_cwsr_apu(struct kfd_process *p, 
struct file *filep)
 
memcpy(qpd->cwsr_kaddr, dev->kfd->cwsr_isa, 
dev->kfd->cwsr_isa_size);
 
+   kfd_process_set_trap_debug_flag(qpd, p->debug_trap_enabled);
+
qpd->tma_addr = qpd->tba_addr + KFD_CWSR_TMA_OFFSET;
pr_debug("set tba :0x%llx, tma:0x%llx, cwsr_kaddr:%p for 
pqm.\n",
qpd->tba_addr, qpd->tma_addr, qpd->cwsr_kaddr);
@@ -1345,6 +1347,9 @@ static int kfd_process_device_init_cwsr_dgpu(struct 
kfd_process_device *pdd)
 
memcpy(qpd->cwsr_kaddr, dev->kfd->cwsr_isa, dev->kfd->cwsr_isa_size);
 
+   kfd_process_set_trap_debug_flag(>qpd,
+   pdd->process->debug_trap_enabled);
+
qpd->tma_addr = qpd->tba_addr + KFD_CWSR_TMA_OFFSET;
pr_debug("set tba :0x%llx, tma:0x%llx, cwsr_kaddr:%p for pqm.\n",
 qpd->tba_addr, qpd->tma_addr, qpd->cwsr_kaddr);
@@ -1431,6 +1436,16 @@ bool kfd_process_xnack_mode(struct kfd_process *p, bool 
supported)
return true;
 }
 
+void kfd_process_set_trap_debug_flag(struct qcm_process_device *qpd,
+bool enabled)
+{
+   if (qpd->cwsr_kaddr) {
+   uint64_t *tma =
+   (uint64_t *)(qpd->cwsr_kaddr + KFD_CWSR_TMA_OFFSET);
+   tma[2] = enabled;
+   }
+}
+
 /*
  * On return the kfd_process is fully operational and will be freed when the
  * mm is released
-- 
2.25.1

[PATCH 30/33] drm/amdkfd: add debug query exception info operation

Allow the debugger to query additional info based on an exception code.
For device exceptions, it's currently only memory violation information.
For process exceptions, it's currently only runtime information.
Queue exception only report the queue exception status.

The debugger has the option of clearing the target exception on query.

Signed-off-by: Jonathan Kim 
Reviewed-by: Felix Kuehling 
---
 drivers/gpu/drm/amd/amdkfd/kfd_chardev.c |   7 ++
 drivers/gpu/drm/amd/amdkfd/kfd_debug.c   | 120 +++
 drivers/gpu/drm/amd/amdkfd/kfd_debug.h   |   6 ++
 3 files changed, 133 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
index ebb2088d12fa..00aa844762b0 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
@@ -3045,6 +3045,13 @@ static int kfd_ioctl_set_debug_trap(struct file *filep, 
struct kfd_process *p, v
>query_debug_event.exception_mask);
break;
case KFD_IOC_DBG_TRAP_QUERY_EXCEPTION_INFO:
+   r = kfd_dbg_trap_query_exception_info(target,
+   args->query_exception_info.source_id,
+   args->query_exception_info.exception_code,
+   args->query_exception_info.clear_exception,
+   (void __user 
*)args->query_exception_info.info_ptr,
+   >query_exception_info.info_size);
+   break;
case KFD_IOC_DBG_TRAP_GET_QUEUE_SNAPSHOT:
case KFD_IOC_DBG_TRAP_GET_DEVICE_SNAPSHOT:
pr_warn("Debug op %i not supported yet\n", args->op);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_debug.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_debug.c
index e9530e682e85..24e2b285448a 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_debug.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_debug.c
@@ -890,6 +890,126 @@ int kfd_dbg_trap_set_wave_launch_mode(struct kfd_process 
*target,
return r;
 }
 
+int kfd_dbg_trap_query_exception_info(struct kfd_process *target,
+   uint32_t source_id,
+   uint32_t exception_code,
+   bool clear_exception,
+   void __user *info,
+   uint32_t *info_size)
+{
+   bool found = false;
+   int r = 0;
+   uint32_t copy_size, actual_info_size = 0;
+   uint64_t *exception_status_ptr = NULL;
+
+   if (!target)
+   return -EINVAL;
+
+   if (!info || !info_size)
+   return -EINVAL;
+
+   mutex_lock(>event_mutex);
+
+   if (KFD_DBG_EC_TYPE_IS_QUEUE(exception_code)) {
+   /* Per queue exceptions */
+   struct queue *queue = NULL;
+   int i;
+
+   for (i = 0; i < target->n_pdds; i++) {
+   struct kfd_process_device *pdd = target->pdds[i];
+   struct qcm_process_device *qpd = >qpd;
+
+   list_for_each_entry(queue, >queues_list, list) {
+   if (!found && queue->properties.queue_id == 
source_id) {
+   found = true;
+   break;
+   }
+   }
+   if (found)
+   break;
+   }
+
+   if (!found) {
+   r = -EINVAL;
+   goto out;
+   }
+
+   if (!(queue->properties.exception_status & 
KFD_EC_MASK(exception_code))) {
+   r = -ENODATA;
+   goto out;
+   }
+   exception_status_ptr = >properties.exception_status;
+   } else if (KFD_DBG_EC_TYPE_IS_DEVICE(exception_code)) {
+   /* Per device exceptions */
+   struct kfd_process_device *pdd = NULL;
+   int i;
+
+   for (i = 0; i < target->n_pdds; i++) {
+   pdd = target->pdds[i];
+   if (pdd->dev->id == source_id) {
+   found = true;
+   break;
+   }
+   }
+
+   if (!found) {
+   r = -EINVAL;
+   goto out;
+   }
+
+   if (!(pdd->exception_status & KFD_EC_MASK(exception_code))) {
+   r = -ENODATA;
+   goto out;
+   }
+
+   if (exception_code == EC_DEVICE_MEMORY_VIOLATION) {
+   copy_size = min((size_t)(*info_size), 
pdd->vm_fault_exc_data_size);
+
+   if (copy_to_user(info, pdd->vm_fault_exc_data, 
copy_size)) {
+   r = -EFAULT;
+   goto out;
+   }
+   actual_info_size = pdd->vm_fault_exc_data_size;
+   if

[PATCH 33/33] drm/amdkfd: bump kfd ioctl minor version for debug api availability

Bump the minor version to declare debugging capability is now
available.

Signed-off-by: Jonathan Kim 
Reviewed-by: Felix Kuehling 
---
 drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 1 -
 include/uapi/linux/kfd_ioctl.h   | 3 ++-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
index f522325b409b..56f55da482e2 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
@@ -2984,7 +2984,6 @@ static int kfd_ioctl_set_debug_trap(struct file *filep, 
struct kfd_process *p, v
if (!r)
target->exception_enable_mask = 
args->enable.exception_mask;
 
-   pr_warn("Debug functions limited\n");
break;
case KFD_IOC_DBG_TRAP_DISABLE:
r = kfd_dbg_trap_disable(target);
diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h
index dfe745ee427e..ea0d50955eac 100644
--- a/include/uapi/linux/kfd_ioctl.h
+++ b/include/uapi/linux/kfd_ioctl.h
@@ -38,9 +38,10 @@
  * - 1.10 - Add SMI profiler event log
  * - 1.11 - Add unified memory for ctx save/restore area
  * - 1.12 - Add DMA buf export ioctl
+ * - 1.13 - Add debugger API
  */
 #define KFD_IOCTL_MAJOR_VERSION 1
-#define KFD_IOCTL_MINOR_VERSION 12
+#define KFD_IOCTL_MINOR_VERSION 13
 
 struct kfd_ioctl_get_version_args {
__u32 major_version;/* from KFD */
-- 
2.25.1

[PATCH 20/33] drm/amdkfd: add runtime enable operation

The debugger can attach to a process prior to HSA enablement (i.e.
inferior is spawned by the debugger and attached to immediately before
target process has been enabled for HSA dispatches) or it
can attach to a running target that is already HSA enabled.  Either
way, the debugger needs to know the enablement status to know when
it can inspect queues.

For the scenario where the debugger spawns the target process,
it will have to wait for ROCr's runtime enable request from the target.
The runtime enable request will be able to see that its process has been
debug attached.  ROCr raises an EC_PROCESS_RUNTIME signal to the
debugger then blocks the target process while waiting the debugger's
response. Once the debugger has received the runtime signal, it will
unblock the target process.

For the scenario where the debugger attaches to a running target
process, ROCr will set the target process' runtime status as enabled so
that on an attach request, the debugger will be able to see this
status and will continue with debug enablement as normal.

A secondary requirement is to conditionally enable the trap tempories only
if the user requests it (env var HSA_ENABLE_DEBUG=1) or if the debugger
attaches with HSA runtime enabled.  This is because setting up the trap
temporaries incurs a performance overhead that is unacceptable for
microbench performance in normal mode for certain customers.

In the scenario where the debugger spawns the target process, when ROCr
detects that the debugger has attached during the runtime enable
request, it will enable the trap temporaries before it blocks the target
process while waiting for the debugger to respond.

In the scenario where the debugger attaches to a running target process,
it will enable to trap temporaries itself.

Finally, there is an additional restriction that is required to be
enforced with runtime enable and HW debug mode setting. The debugger must
first ensure that HW debug mode has been enabled before permitting HW debug
mode operations.

With single process debug devices, allowing the debugger to set debug
HW modes prior to trap activation means that debug HW mode setting can
occur before the KFD has reserved the debug VMID (0xf) from the hardware
scheduler's VMID allocation resource pool.  This can result in the
hardware scheduler assigning VMID 0xf to a non-debugged process and
having that process inherit debug HW mode settings intended for the
debugged target process instead, which is both incorrect and potentially
fatal for normal mode operation.

With multi process debug devices, allowing the debugger to set debug
HW modes prior to trap activation means that non-debugged processes
migrating to a new VMID could inherit unintended debug settings.

All debug operations that touch HW settings must require trap activation
where trap activation is triggered by both debug attach and runtime
enablement (target has KFD opened and is ready to dispatch work).

v2: fixup with new kfd_node struct reference

Signed-off-by: Jonathan Kim 
---
 drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 143 ++-
 drivers/gpu/drm/amd/amdkfd/kfd_debug.c   |   6 +-
 drivers/gpu/drm/amd/amdkfd/kfd_debug.h   |   4 +
 drivers/gpu/drm/amd/amdkfd/kfd_priv.h|   1 +
 4 files changed, 150 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
index ec5a85454192..73cb5abce431 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
@@ -2738,11 +2738,140 @@ static int kfd_ioctl_criu(struct file *filep, struct 
kfd_process *p, void *data)
return ret;
 }
 
-static int kfd_ioctl_runtime_enable(struct file *filep, struct kfd_process *p, 
void *data)
+static int runtime_enable(struct kfd_process *p, uint64_t r_debug,
+   bool enable_ttmp_setup)
+{
+   int i = 0, ret = 0;
+
+   if (p->is_runtime_retry)
+   goto retry;
+
+   if (p->runtime_info.runtime_state != DEBUG_RUNTIME_STATE_DISABLED)
+   return -EBUSY;
+
+   for (i = 0; i < p->n_pdds; i++) {
+   struct kfd_process_device *pdd = p->pdds[i];
+
+   if (pdd->qpd.queue_count)
+   return -EEXIST;
+   }
+
+   p->runtime_info.runtime_state = DEBUG_RUNTIME_STATE_ENABLED;
+   p->runtime_info.r_debug = r_debug;
+   p->runtime_info.ttmp_setup = enable_ttmp_setup;
+
+   if (p->runtime_info.ttmp_setup) {
+   for (i = 0; i < p->n_pdds; i++) {
+   struct kfd_process_device *pdd = p->pdds[i];
+
+   if (!kfd_dbg_is_rlc_restore_supported(pdd->dev)) {
+   amdgpu_gfx_off_ctrl(pdd->dev->adev, false);
+   pdd->dev->kfd2kgd->enable_debug_trap(
+   pdd->dev->adev,
+   true,
+

[PATCH 28/33] drm/amdkfd: add debug set flags operation

Allow the debugger to set single memory and single ALU operations.

Some exceptions are imprecise (memory violations, address watch) in the
sense that a trap occurs only when the exception interrupt occurs and
not at the non-halting faulty instruction.  Trap temporaries 0 & 1 save
the program counter address, which means that these values will not point
to the faulty instruction address but to whenever the interrupt was
raised.

Setting the Single Memory Operations flag will inject an automatic wait
on every memory operation instruction forcing imprecise memory exceptions
to become precise at the cost of performance.  This setting is not
permitted on debug devices that support only a global setting of this
option.

Return the previous set flags to the debugger as well.

v2: fixup with new kfd_node struct reference mes checks

Signed-off-by: Jonathan Kim 
---
 drivers/gpu/drm/amd/amdkfd/kfd_chardev.c |  2 +
 drivers/gpu/drm/amd/amdkfd/kfd_debug.c   | 58 
 drivers/gpu/drm/amd/amdkfd/kfd_debug.h   |  1 +
 3 files changed, 61 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
index e88be582d44d..e5d95b144dcd 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
@@ -3035,6 +3035,8 @@ static int kfd_ioctl_set_debug_trap(struct file *filep, 
struct kfd_process *p, v
args->clear_node_address_watch.id);
break;
case KFD_IOC_DBG_TRAP_SET_FLAGS:
+   r = kfd_dbg_trap_set_flags(target, >set_flags.flags);
+   break;
case KFD_IOC_DBG_TRAP_QUERY_DEBUG_EVENT:
case KFD_IOC_DBG_TRAP_QUERY_EXCEPTION_INFO:
case KFD_IOC_DBG_TRAP_GET_QUEUE_SNAPSHOT:
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_debug.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_debug.c
index 4b36cc8b5fb7..43c3170998d3 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_debug.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_debug.c
@@ -23,6 +23,7 @@
 #include "kfd_debug.h"
 #include "kfd_device_queue_manager.h"
 #include 
+#include 
 
 #define MAX_WATCH_ADDRESSES4
 
@@ -423,6 +424,59 @@ static void kfd_dbg_clear_process_address_watch(struct 
kfd_process *target)
kfd_dbg_trap_clear_dev_address_watch(target->pdds[i], 
j);
 }
 
+int kfd_dbg_trap_set_flags(struct kfd_process *target, uint32_t *flags)
+{
+   uint32_t prev_flags = target->dbg_flags;
+   int i, r = 0, rewind_count = 0;
+
+   for (i = 0; i < target->n_pdds; i++) {
+   if (!kfd_dbg_is_per_vmid_supported(target->pdds[i]->dev) &&
+   (*flags & KFD_DBG_TRAP_FLAG_SINGLE_MEM_OP)) {
+   *flags = prev_flags;
+   return -EACCES;
+   }
+   }
+
+   target->dbg_flags = *flags & KFD_DBG_TRAP_FLAG_SINGLE_MEM_OP;
+   *flags = prev_flags;
+   for (i = 0; i < target->n_pdds; i++) {
+   struct kfd_process_device *pdd = target->pdds[i];
+
+   if (!kfd_dbg_is_per_vmid_supported(pdd->dev))
+   continue;
+
+   if (!pdd->dev->kfd->shared_resources.enable_mes)
+   r = debug_refresh_runlist(pdd->dev->dqm);
+   else
+   r = kfd_dbg_set_mes_debug_mode(pdd);
+
+   if (r) {
+   target->dbg_flags = prev_flags;
+   break;
+   }
+
+   rewind_count++;
+   }
+
+   /* Rewind flags */
+   if (r) {
+   target->dbg_flags = prev_flags;
+
+   for (i = 0; i < rewind_count; i++) {
+   struct kfd_process_device *pdd = target->pdds[i];
+
+   if (!kfd_dbg_is_per_vmid_supported(pdd->dev))
+   continue;
+
+   if (!pdd->dev->kfd->shared_resources.enable_mes)
+   debug_refresh_runlist(pdd->dev->dqm);
+   else
+   kfd_dbg_set_mes_debug_mode(pdd);
+   }
+   }
+
+   return r;
+}
 
 /* kfd_dbg_trap_deactivate:
  * target: target process
@@ -437,9 +491,13 @@ void kfd_dbg_trap_deactivate(struct kfd_process *target, 
bool unwind, int unwind
int i;
 
if (!unwind) {
+   uint32_t flags = 0;
+
cancel_work_sync(>debug_event_workarea);
kfd_dbg_clear_process_address_watch(target);
kfd_dbg_trap_set_wave_launch_mode(target, 0);
+
+   kfd_dbg_trap_set_flags(target, );
}
 
for (i = 0; i < target->n_pdds; i++) {
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_debug.h 
b/drivers/gpu/drm/amd/amdkfd/kfd_debug.h
index 7f0757c2af2c..ef8e9f7f1716 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_debug.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_debug.h
@@ -57,6 +57,7 @@ int kfd_dbg_trap_set_dev_address_watch(struct 
kfd_process_device *pdd,

[PATCH 25/33] drm/amdkfd: add debug wave launch mode operation

Allow the debugger to set wave behaviour on to either normally operate,
halt at launch, trap on every instruction, terminate immediately or
stall on allocation.

v2: fixup with new kfd_node struct reference for mes check

Signed-off-by: Jonathan Kim 
---
 .../drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c  | 12 +++
 .../drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c   |  1 +
 .../drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c| 25 +
 .../drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.h|  3 ++
 .../drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c  |  3 +-
 .../drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c| 14 +++-
 .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 25 +
 .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h |  3 ++
 drivers/gpu/drm/amd/amdkfd/kfd_chardev.c  |  3 ++
 drivers/gpu/drm/amd/amdkfd/kfd_debug.c| 36 ++-
 drivers/gpu/drm/amd/amdkfd/kfd_debug.h|  2 ++
 11 files changed, 124 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c
index d7881bbd828d..774ecfc3451a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c
@@ -107,6 +107,17 @@ static uint32_t 
kgd_aldebaran_set_wave_launch_trap_override(struct amdgpu_device
return data;
 }
 
+static uint32_t kgd_aldebaran_set_wave_launch_mode(struct amdgpu_device *adev,
+   uint8_t wave_launch_mode,
+   uint32_t vmid)
+{
+   uint32_t data = 0;
+
+   data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, LAUNCH_MODE, 
wave_launch_mode);
+
+   return data;
+}
+
 const struct kfd2kgd_calls aldebaran_kfd2kgd = {
.program_sh_mem_settings = kgd_gfx_v9_program_sh_mem_settings,
.set_pasid_vmid_mapping = kgd_gfx_v9_set_pasid_vmid_mapping,
@@ -129,6 +140,7 @@ const struct kfd2kgd_calls aldebaran_kfd2kgd = {
.disable_debug_trap = kgd_aldebaran_disable_debug_trap,
.validate_trap_override_request = 
kgd_aldebaran_validate_trap_override_request,
.set_wave_launch_trap_override = 
kgd_aldebaran_set_wave_launch_trap_override,
+   .set_wave_launch_mode = kgd_aldebaran_set_wave_launch_mode,
.get_iq_wait_times = kgd_gfx_v9_get_iq_wait_times,
.build_grace_period_packet_info = 
kgd_gfx_v9_build_grace_period_packet_info,
.program_trap_handler_settings = 
kgd_gfx_v9_program_trap_handler_settings,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
index ec2587664001..fbdc1b7b1e42 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
@@ -412,6 +412,7 @@ const struct kfd2kgd_calls arcturus_kfd2kgd = {
.disable_debug_trap = kgd_arcturus_disable_debug_trap,
.validate_trap_override_request = 
kgd_gfx_v9_validate_trap_override_request,
.set_wave_launch_trap_override = 
kgd_gfx_v9_set_wave_launch_trap_override,
+   .set_wave_launch_mode = kgd_gfx_v9_set_wave_launch_mode,
.get_iq_wait_times = kgd_gfx_v9_get_iq_wait_times,
.build_grace_period_packet_info = 
kgd_gfx_v9_build_grace_period_packet_info,
.get_cu_occupancy = kgd_gfx_v9_get_cu_occupancy,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
index 7ea0362dcab3..a7a6edda557f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
@@ -856,6 +856,30 @@ uint32_t kgd_gfx_v10_set_wave_launch_trap_override(struct 
amdgpu_device *adev,
return 0;
 }
 
+uint32_t kgd_gfx_v10_set_wave_launch_mode(struct amdgpu_device *adev,
+   uint8_t wave_launch_mode,
+   uint32_t vmid)
+{
+   uint32_t data = 0;
+   bool is_mode_set = !!wave_launch_mode;
+
+   mutex_lock(>grbm_idx_mutex);
+
+   kgd_gfx_v10_set_wave_launch_stall(adev, vmid, true);
+
+   data = REG_SET_FIELD(data, SPI_GDBG_WAVE_CNTL2,
+   VMID_MASK, is_mode_set ? 1 << vmid : 0);
+   data = REG_SET_FIELD(data, SPI_GDBG_WAVE_CNTL2,
+   MODE, is_mode_set ? wave_launch_mode : 0);
+   WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL2), data);
+
+   kgd_gfx_v10_set_wave_launch_stall(adev, vmid, false);
+
+   mutex_unlock(>grbm_idx_mutex);
+
+   return 0;
+}
+
 /* kgd_gfx_v10_get_iq_wait_times: Returns the mmCP_IQ_WAIT_TIME1/2 values
  * The values read are:
  * ib_offload_wait_time -- Wait Count for Indirect Buffer Offloads.
@@ -944,6 +968,7 @@ const struct kfd2kgd_calls gfx_v10_kfd2kgd = {
.disable_debug_trap = kgd_gfx_v10_disable_debug_trap,
.validate_trap_override_request = 
kgd_gfx_v10_validate_trap_override_request,

[PATCH 22/33] drm/amdkfd: update process interrupt handling for debug events

The debugger must be notified by any debugger subscribed exception
that comes from hardware interrupts.

If a debugger session exits, any exceptions it subscribed to may still
have interrupts in the interrupt ring buffer or KGD/KFD pipeline.
To prevent a new session from inheriting stale interrupts, when a new
queue is created, open an interrupt drain and allow the IH ring to drain
from a timestamped checkpoint.  Then inject a custom IV so that once
the custom IV is picked up by the KFD, it's safe to close the drain
and proceed with queue creation.

The drain must also be on debug disable as SW interrupts may still
be processed.  Drain at this time and clear all the exception status.

The debugger may also not be attached nor subscibed to certain
exceptions so forward them directly to the runtime.

GFX10 also requires its own IV processing, hence the creation of
kfd_int_process_v10.c.  This is because the IV from SQ interrupts are
packed into a new continguous format unlike GFX9. To make this clear,
a separate interrupting handling code file was created.

v2: use new kfd_node struct in prototypes.

Signed-off-by: Jonathan Kim 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c|  16 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h|   2 +
 drivers/gpu/drm/amd/amdkfd/Makefile   |   1 +
 drivers/gpu/drm/amd/amdkfd/kfd_debug.c|  84 
 drivers/gpu/drm/amd/amdkfd/kfd_debug.h|   6 +
 drivers/gpu/drm/amd/amdkfd/kfd_device.c   |   4 +-
 .../gpu/drm/amd/amdkfd/kfd_int_process_v10.c  | 405 ++
 .../gpu/drm/amd/amdkfd/kfd_int_process_v11.c  |  21 +-
 .../gpu/drm/amd/amdkfd/kfd_int_process_v9.c   |  98 -
 drivers/gpu/drm/amd/amdkfd/kfd_priv.h |  12 +
 drivers/gpu/drm/amd/amdkfd/kfd_process.c  |  47 ++
 .../amd/amdkfd/kfd_process_queue_manager.c|   4 +
 12 files changed, 680 insertions(+), 20 deletions(-)
 create mode 100644 drivers/gpu/drm/amd/amdkfd/kfd_int_process_v10.c

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index 66f80b9ab0c5..98cd52bb005f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -777,6 +777,22 @@ void amdgpu_amdkfd_ras_poison_consumption_handler(struct 
amdgpu_device *adev, bo
amdgpu_umc_poison_handler(adev, reset);
 }
 
+int amdgpu_amdkfd_send_close_event_drain_irq(struct amdgpu_device *adev,
+   uint32_t *payload)
+{
+   int ret;
+
+   /* Device or IH ring is not ready so bail. */
+   ret = amdgpu_ih_wait_on_checkpoint_process_ts(adev, >irq.ih);
+   if (ret)
+   return ret;
+
+   /* Send payload to fence KFD interrupts */
+   amdgpu_amdkfd_interrupt(adev, payload);
+
+   return 0;
+}
+
 bool amdgpu_amdkfd_ras_query_utcl2_poison_status(struct amdgpu_device *adev)
 {
if (adev->gfx.ras && adev->gfx.ras->query_utcl2_poison_status)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
index 94cc456761e5..dd740e64e6e1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
@@ -250,6 +250,8 @@ int amdgpu_amdkfd_get_xgmi_bandwidth_mbytes(struct 
amdgpu_device *dst,
struct amdgpu_device *src,
bool is_min);
 int amdgpu_amdkfd_get_pcie_bandwidth_mbytes(struct amdgpu_device *adev, bool 
is_min);
+int amdgpu_amdkfd_send_close_event_drain_irq(struct amdgpu_device *adev,
+   uint32_t *payload);
 
 /* Read user wptr from a specified user address space with page fault
  * disabled. The memory must be pinned and mapped to the hardware when
diff --git a/drivers/gpu/drm/amd/amdkfd/Makefile 
b/drivers/gpu/drm/amd/amdkfd/Makefile
index 747754428073..2ec8f27c5366 100644
--- a/drivers/gpu/drm/amd/amdkfd/Makefile
+++ b/drivers/gpu/drm/amd/amdkfd/Makefile
@@ -53,6 +53,7 @@ AMDKFD_FILES  := $(AMDKFD_PATH)/kfd_module.o \
$(AMDKFD_PATH)/kfd_events.o \
$(AMDKFD_PATH)/cik_event_interrupt.o \
$(AMDKFD_PATH)/kfd_int_process_v9.o \
+   $(AMDKFD_PATH)/kfd_int_process_v10.o \
$(AMDKFD_PATH)/kfd_int_process_v11.o \
$(AMDKFD_PATH)/kfd_smi_events.o \
$(AMDKFD_PATH)/kfd_crat.o \
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_debug.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_debug.c
index 17e8e9edccbf..68b657398d41 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_debug.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_debug.c
@@ -125,6 +125,64 @@ bool kfd_dbg_ev_raise(uint64_t event_mask,
return is_subscribed;
 }
 
+/* set pending event queue entry from ring entry  */
+bool kfd_set_dbg_ev_from_interrupt(struct kfd_node *dev,
+  unsigned int pasid,
+  uint32_t doorbell_id,
+

[PATCH 26/33] drm/amdkfd: add debug suspend and resume process queues operation

In order to inspect waves from the saved context at any point during a
debug session, the debugger must be able to preempt queues to trigger
context save by suspending them.

On queue suspend, the KFD will copy the context save header information
so that the debugger can correctly crawl the appropriate size of the saved
context. The debugger must then also be allowed to resume suspended queues.

A queue that is newly created cannot be suspended because queue ids are
recycled after destruction so the debugger needs to know that this has
occurred.  Query functions will be later added that will clear a given
queue of its new queue status.

A queue cannot be destroyed while it is suspended to preserve its saved
context during debugger inspection.  Have queue destruction block while
a queue is suspended and unblocked when it is resumed.  Likewise, if a
queue is about to be destroyed, it cannot be suspended.

Return the number of queues successfully suspended or resumed along with
a per queue status array where the upper bits per queue status show that
the request was invalid (new/destroyed queue suspend request, missing
queue) or an error occurred (HWS in a fatal state so it can't suspend or
resume queues).

v2: fixup new kfd_node struct reference for mes fw check.
also fixup missing EC_QUEUE_NEW flagging on newly created queue.

Signed-off-by: Jonathan Kim 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c|   5 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h|   1 +
 drivers/gpu/drm/amd/amdkfd/kfd_chardev.c  |  11 +
 drivers/gpu/drm/amd/amdkfd/kfd_debug.c|   7 +
 .../drm/amd/amdkfd/kfd_device_queue_manager.c | 447 +-
 .../drm/amd/amdkfd/kfd_device_queue_manager.h |  10 +
 .../gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c  |  10 +
 .../gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c  |  15 +-
 .../gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c   |  14 +-
 drivers/gpu/drm/amd/amdkfd/kfd_priv.h |   5 +-
 .../amd/amdkfd/kfd_process_queue_manager.c|   1 +
 11 files changed, 512 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index 98cd52bb005f..b4fcad0e62f7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -772,6 +772,11 @@ bool amdgpu_amdkfd_have_atomics_support(struct 
amdgpu_device *adev)
return adev->have_atomics_support;
 }
 
+void amdgpu_amdkfd_debug_mem_fence(struct amdgpu_device *adev)
+{
+   amdgpu_device_flush_hdp(adev, NULL);
+}
+
 void amdgpu_amdkfd_ras_poison_consumption_handler(struct amdgpu_device *adev, 
bool reset)
 {
amdgpu_umc_poison_handler(adev, reset);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
index dd740e64e6e1..2d0406bff84e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
@@ -322,6 +322,7 @@ int amdgpu_amdkfd_gpuvm_import_dmabuf(struct amdgpu_device 
*adev,
  uint64_t *mmap_offset);
 int amdgpu_amdkfd_gpuvm_export_dmabuf(struct kgd_mem *mem,
  struct dma_buf **dmabuf);
+void amdgpu_amdkfd_debug_mem_fence(struct amdgpu_device *adev);
 int amdgpu_amdkfd_get_tile_config(struct amdgpu_device *adev,
struct tile_config *config);
 void amdgpu_amdkfd_ras_poison_consumption_handler(struct amdgpu_device *adev,
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
index 4b45d4539d48..adda60273456 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
@@ -410,6 +410,7 @@ static int kfd_ioctl_create_queue(struct file *filep, 
struct kfd_process *p,
pr_debug("Write ptr address   == 0x%016llX\n",
args->write_pointer_address);
 
+   kfd_dbg_ev_raise(KFD_EC_MASK(EC_QUEUE_NEW), p, dev, queue_id, false, 
NULL, 0);
return 0;
 
 err_create_queue:
@@ -2996,7 +2997,17 @@ static int kfd_ioctl_set_debug_trap(struct file *filep, 
struct kfd_process *p, v
args->launch_mode.launch_mode);
break;
case KFD_IOC_DBG_TRAP_SUSPEND_QUEUES:
+   r = suspend_queues(target,
+   args->suspend_queues.num_queues,
+   args->suspend_queues.grace_period,
+   args->suspend_queues.exception_mask,
+   (uint32_t 
*)args->suspend_queues.queue_array_ptr);
+
+   break;
case KFD_IOC_DBG_TRAP_RESUME_QUEUES:
+   r = resume_queues(target, args->resume_queues.num_queues,
+   (uint32_t 
*)args->resume_queues.queue_array_ptr);
+   break;
case KFD_IOC_DBG_TRAP_SET_NODE_ADDRESS_WATCH:
case KFD_IOC_DBG_TRAP_CLEAR_NODE_ADDRESS_WATCH:
case

[PATCH 23/33] drm/amdkfd: add debug set exceptions enabled operation

The debugger subscibes to nofication for requested exceptions on attach.
Allow the debugger to change its subsciption later on.

Signed-off-by: Jonathan Kim 
Reviewed-by: Felix Kuehling 
---
 drivers/gpu/drm/amd/amdkfd/kfd_chardev.c |  3 ++
 drivers/gpu/drm/amd/amdkfd/kfd_debug.c   | 36 
 drivers/gpu/drm/amd/amdkfd/kfd_debug.h   |  2 ++
 3 files changed, 41 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
index 73cb5abce431..80d354eade35 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
@@ -2980,6 +2980,9 @@ static int kfd_ioctl_set_debug_trap(struct file *filep, 
struct kfd_process *p, v
args->send_runtime_event.exception_mask);
break;
case KFD_IOC_DBG_TRAP_SET_EXCEPTIONS_ENABLED:
+   kfd_dbg_set_enabled_debug_exception_mask(target,
+   args->set_exceptions_enabled.exception_mask);
+   break;
case KFD_IOC_DBG_TRAP_SET_WAVE_LAUNCH_OVERRIDE:
case KFD_IOC_DBG_TRAP_SET_WAVE_LAUNCH_MODE:
case KFD_IOC_DBG_TRAP_SUSPEND_QUEUES:
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_debug.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_debug.c
index 68b657398d41..48a4e3cc2234 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_debug.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_debug.c
@@ -521,3 +521,39 @@ int kfd_dbg_trap_enable(struct kfd_process *target, 
uint32_t fd,
 
return r;
 }
+
+void kfd_dbg_set_enabled_debug_exception_mask(struct kfd_process *target,
+   uint64_t exception_set_mask)
+{
+   uint64_t found_mask = 0;
+   struct process_queue_manager *pqm;
+   struct process_queue_node *pqn;
+   static const char write_data = '.';
+   loff_t pos = 0;
+   int i;
+
+   mutex_lock(>event_mutex);
+
+   found_mask |= target->exception_status;
+
+   pqm = >pqm;
+   list_for_each_entry(pqn, >queues, process_queue_list) {
+   if (!pqn)
+   continue;
+
+   found_mask |= pqn->q->properties.exception_status;
+   }
+
+   for (i = 0; i < target->n_pdds; i++) {
+   struct kfd_process_device *pdd = target->pdds[i];
+
+   found_mask |= pdd->exception_status;
+   }
+
+   if (exception_set_mask & found_mask)
+   kernel_write(target->dbg_ev_file, _data, 1, );
+
+   target->exception_enable_mask = exception_set_mask;
+
+   mutex_unlock(>event_mutex);
+}
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_debug.h 
b/drivers/gpu/drm/amd/amdkfd/kfd_debug.h
index 5153ccbd7fd1..6c1054a08872 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_debug.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_debug.h
@@ -56,6 +56,8 @@ static inline bool kfd_dbg_is_per_vmid_supported(struct 
kfd_node *dev)
 
 void debug_event_write_work_handler(struct work_struct *work);
 
+void kfd_dbg_set_enabled_debug_exception_mask(struct kfd_process *target,
+   uint64_t exception_set_mask);
 /*
  * If GFX off is enabled, chips that do not support RLC restore for the debug
  * registers will disable GFX off temporarily for the entire debug session.
-- 
2.25.1

[PATCH 31/33] drm/amdkfd: add debug queue snapshot operation

Allow the debugger to get a snapshot of a specified number of queues
containing various queue property information that is copied to the
debugger.

Since the debugger doesn't know how many queues exist at any given time,
allow the debugger to pass the requested number of snapshots as 0 to get
the actual number of potential snapshots to use for a subsequent snapshot
request for actual information.

To prevent future ABI breakage, pass in the requested entry_size.
The KFD will return it's own entry_size in case the debugger still wants
log the information in a core dump on sizing failure.

Also allow the debugger to clear exceptions when doing a snapshot.

Signed-off-by: Jonathan Kim 
Reviewed-by: Felix Kuehling 
---
 drivers/gpu/drm/amd/amdkfd/kfd_chardev.c  |  6 +++
 .../drm/amd/amdkfd/kfd_device_queue_manager.c | 36 +
 .../drm/amd/amdkfd/kfd_device_queue_manager.h |  3 ++
 drivers/gpu/drm/amd/amdkfd/kfd_priv.h |  5 +++
 .../amd/amdkfd/kfd_process_queue_manager.c| 40 +++
 5 files changed, 90 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
index 00aa844762b0..b24a73fd53af 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
@@ -3053,6 +3053,12 @@ static int kfd_ioctl_set_debug_trap(struct file *filep, 
struct kfd_process *p, v
>query_exception_info.info_size);
break;
case KFD_IOC_DBG_TRAP_GET_QUEUE_SNAPSHOT:
+   r = pqm_get_queue_snapshot(>pqm,
+   args->queue_snapshot.exception_mask,
+   (void __user 
*)args->queue_snapshot.snapshot_buf_ptr,
+   >queue_snapshot.num_queues,
+   >queue_snapshot.entry_size);
+   break;
case KFD_IOC_DBG_TRAP_GET_DEVICE_SNAPSHOT:
pr_warn("Debug op %i not supported yet\n", args->op);
r = -EACCES;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
index 03fabe6e9cdb..9f52f8426ed1 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
@@ -3040,6 +3040,42 @@ int suspend_queues(struct kfd_process *p,
return total_suspended;
 }
 
+static uint32_t set_queue_type_for_user(struct queue_properties *q_props)
+{
+   switch (q_props->type) {
+   case KFD_QUEUE_TYPE_COMPUTE:
+   return q_props->format == KFD_QUEUE_FORMAT_PM4
+   ? KFD_IOC_QUEUE_TYPE_COMPUTE
+   : KFD_IOC_QUEUE_TYPE_COMPUTE_AQL;
+   case KFD_QUEUE_TYPE_SDMA:
+   return KFD_IOC_QUEUE_TYPE_SDMA;
+   case KFD_QUEUE_TYPE_SDMA_XGMI:
+   return KFD_IOC_QUEUE_TYPE_SDMA_XGMI;
+   default:
+   WARN_ONCE(true, "queue type not recognized!");
+   return 0x;
+   };
+}
+
+void set_queue_snapshot_entry(struct queue *q,
+ uint64_t exception_clear_mask,
+ struct kfd_queue_snapshot_entry *qss_entry)
+{
+   qss_entry->ring_base_address = q->properties.queue_address;
+   qss_entry->write_pointer_address = (uint64_t)q->properties.write_ptr;
+   qss_entry->read_pointer_address = (uint64_t)q->properties.read_ptr;
+   qss_entry->ctx_save_restore_address =
+   q->properties.ctx_save_restore_area_address;
+   qss_entry->ctx_save_restore_area_size =
+   q->properties.ctx_save_restore_area_size;
+   qss_entry->exception_status = q->properties.exception_status;
+   qss_entry->queue_id = q->properties.queue_id;
+   qss_entry->gpu_id = q->device->id;
+   qss_entry->ring_size = (uint32_t)q->properties.queue_size;
+   qss_entry->queue_type = set_queue_type_for_user(>properties);
+   q->properties.exception_status &= ~exception_clear_mask;
+}
+
 int debug_lock_and_unmap(struct device_queue_manager *dqm)
 {
int r;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h 
b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h
index d4e6dbffe8c2..7dd4b177219d 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h
@@ -300,6 +300,9 @@ int suspend_queues(struct kfd_process *p,
 int resume_queues(struct kfd_process *p,
uint32_t num_queues,
uint32_t *usr_queue_id_array);
+void set_queue_snapshot_entry(struct queue *q,
+ uint64_t exception_clear_mask,
+ struct kfd_queue_snapshot_entry *qss_entry);
 int debug_lock_and_unmap(struct device_queue_manager *dqm);
 int debug_map_and_unlock(struct device_queue_manager *dqm);
 int

[PATCH 24/33] drm/amdkfd: add debug wave launch override operation

This operation allows the debugger to override the enabled HW
exceptions on the device.

On debug devices that only support the debugging of a single process,
the HW exceptions are global and set through the SPI_GDBG_TRAP_MASK
register.
Because they are global, only address watch exceptions are allowed to
be enabled.  In other words, the debugger must preserve all non-address
watch exception states in normal mode operation by barring a full
replacement override or a non-address watch override request.

For multi-process debugging, all HW exception overrides are per-VMID so
all exceptions can be overridden or fully replaced.

In order for the debugger to know what is permissible, returned the
supported override mask back to the debugger along with the previously
enable overrides.

v2: fixup with new kfd_node struct reference for mes check

Signed-off-by: Jonathan Kim 
---
 .../drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c  | 47 ++
 .../drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c   |  2 +
 .../drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c| 55 
 .../drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.h| 10 +++
 .../drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c  |  5 +-
 .../drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c| 87 ++-
 .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 55 
 .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h | 10 +++
 drivers/gpu/drm/amd/amdkfd/kfd_chardev.c  |  7 ++
 drivers/gpu/drm/amd/amdkfd/kfd_debug.c| 69 +++
 drivers/gpu/drm/amd/amdkfd/kfd_debug.h|  6 ++
 11 files changed, 351 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c
index b811a0985050..d7881bbd828d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c
@@ -25,6 +25,7 @@
 #include "amdgpu_amdkfd_gfx_v9.h"
 #include "gc/gc_9_4_2_offset.h"
 #include "gc/gc_9_4_2_sh_mask.h"
+#include 
 
 /*
  * Returns TRAP_EN, EXCP_EN and EXCP_REPLACE.
@@ -62,6 +63,50 @@ static uint32_t kgd_aldebaran_disable_debug_trap(struct 
amdgpu_device *adev,
return data;
 }
 
+static int kgd_aldebaran_validate_trap_override_request(struct amdgpu_device 
*adev,
+   uint32_t trap_override,
+   uint32_t 
*trap_mask_supported)
+{
+   *trap_mask_supported &= KFD_DBG_TRAP_MASK_FP_INVALID |
+   KFD_DBG_TRAP_MASK_FP_INPUT_DENORMAL |
+   KFD_DBG_TRAP_MASK_FP_DIVIDE_BY_ZERO |
+   KFD_DBG_TRAP_MASK_FP_OVERFLOW |
+   KFD_DBG_TRAP_MASK_FP_UNDERFLOW |
+   KFD_DBG_TRAP_MASK_FP_INEXACT |
+   KFD_DBG_TRAP_MASK_INT_DIVIDE_BY_ZERO |
+   KFD_DBG_TRAP_MASK_DBG_ADDRESS_WATCH |
+   KFD_DBG_TRAP_MASK_DBG_MEMORY_VIOLATION;
+
+   if (trap_override != KFD_DBG_TRAP_OVERRIDE_OR &&
+   trap_override != KFD_DBG_TRAP_OVERRIDE_REPLACE)
+   return -EPERM;
+
+   return 0;
+}
+
+/* returns TRAP_EN, EXCP_EN and EXCP_RPLACE. */
+static uint32_t kgd_aldebaran_set_wave_launch_trap_override(struct 
amdgpu_device *adev,
+   uint32_t vmid,
+   uint32_t trap_override,
+   uint32_t trap_mask_bits,
+   uint32_t trap_mask_request,
+   uint32_t *trap_mask_prev,
+   uint32_t kfd_dbg_trap_cntl_prev)
+
+{
+   uint32_t data = 0;
+
+   *trap_mask_prev = REG_GET_FIELD(kfd_dbg_trap_cntl_prev, 
SPI_GDBG_PER_VMID_CNTL, EXCP_EN);
+   trap_mask_bits = (trap_mask_bits & trap_mask_request) |
+   (*trap_mask_prev & ~trap_mask_request);
+
+   data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1);
+   data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_EN, 
trap_mask_bits);
+   data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_REPLACE, 
trap_override);
+
+   return data;
+}
+
 const struct kfd2kgd_calls aldebaran_kfd2kgd = {
.program_sh_mem_settings = kgd_gfx_v9_program_sh_mem_settings,
.set_pasid_vmid_mapping = kgd_gfx_v9_set_pasid_vmid_mapping,
@@ -82,6 +127,8 @@ const struct kfd2kgd_calls aldebaran_kfd2kgd = {
.get_cu_occupancy = kgd_gfx_v9_get_cu_occupancy,
.enable_debug_trap = kgd_aldebaran_enable_debug_trap,
.disable_debug_trap = kgd_aldebaran_disable_debug_trap,
+   .validate_trap_override_request = 
kgd_aldebaran_validate_trap_override_request,
+   .set_wave_launch_trap_override = 
kgd_aldebaran_set_wave_launch_trap_override,
.get_iq_wait_times = kgd_gfx_v9_get_iq_wait_times,

[PATCH 27/33] drm/amdkfd: add debug set and clear address watch points operation

Shader read, write and atomic memory operations can be alerted to the
debugger as an address watch exception.

Allow the debugger to pass in a watch point to a particular memory
address per device.

Note that there exists only 4 watch points per devices to date, so have
the KFD keep track of what watch points are allocated or not.

v2: fixup with new kfd_node struct reference for mes and watch point
checks

Signed-off-by: Jonathan Kim 
---
 .../drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c  |  51 +++
 .../drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c   |   2 +
 .../drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c|  78 ++
 .../drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.h|   8 ++
 .../drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c  |   5 +-
 .../drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c|  52 ++-
 .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c |  77 ++
 .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h |   8 ++
 drivers/gpu/drm/amd/amdkfd/kfd_chardev.c  |  24 
 drivers/gpu/drm/amd/amdkfd/kfd_debug.c| 136 ++
 drivers/gpu/drm/amd/amdkfd/kfd_debug.h|   8 +-
 drivers/gpu/drm/amd/amdkfd/kfd_device.c   |   2 +
 drivers/gpu/drm/amd/amdkfd/kfd_priv.h |   6 +-
 13 files changed, 452 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c
index 774ecfc3451a..efd6a72aab4e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c
@@ -118,6 +118,55 @@ static uint32_t kgd_aldebaran_set_wave_launch_mode(struct 
amdgpu_device *adev,
return data;
 }
 
+#define TCP_WATCH_STRIDE (regTCP_WATCH1_ADDR_H - regTCP_WATCH0_ADDR_H)
+static uint32_t kgd_gfx_aldebaran_set_address_watch(
+   struct amdgpu_device *adev,
+   uint64_t watch_address,
+   uint32_t watch_address_mask,
+   uint32_t watch_id,
+   uint32_t watch_mode,
+   uint32_t debug_vmid)
+{
+   uint32_t watch_address_high;
+   uint32_t watch_address_low;
+   uint32_t watch_address_cntl;
+
+   watch_address_cntl = 0;
+   watch_address_low = lower_32_bits(watch_address);
+   watch_address_high = upper_32_bits(watch_address) & 0x;
+
+   watch_address_cntl = REG_SET_FIELD(watch_address_cntl,
+   TCP_WATCH0_CNTL,
+   MODE,
+   watch_mode);
+
+   watch_address_cntl = REG_SET_FIELD(watch_address_cntl,
+   TCP_WATCH0_CNTL,
+   MASK,
+   watch_address_mask >> 6);
+
+   watch_address_cntl = REG_SET_FIELD(watch_address_cntl,
+   TCP_WATCH0_CNTL,
+   VALID,
+   1);
+
+   WREG32_RLC((SOC15_REG_OFFSET(GC, 0, regTCP_WATCH0_ADDR_H) +
+   (watch_id * TCP_WATCH_STRIDE)),
+   watch_address_high);
+
+   WREG32_RLC((SOC15_REG_OFFSET(GC, 0, regTCP_WATCH0_ADDR_L) +
+   (watch_id * TCP_WATCH_STRIDE)),
+   watch_address_low);
+
+   return watch_address_cntl;
+}
+
+uint32_t kgd_gfx_aldebaran_clear_address_watch(struct amdgpu_device *adev,
+   uint32_t watch_id)
+{
+   return 0;
+}
+
 const struct kfd2kgd_calls aldebaran_kfd2kgd = {
.program_sh_mem_settings = kgd_gfx_v9_program_sh_mem_settings,
.set_pasid_vmid_mapping = kgd_gfx_v9_set_pasid_vmid_mapping,
@@ -141,6 +190,8 @@ const struct kfd2kgd_calls aldebaran_kfd2kgd = {
.validate_trap_override_request = 
kgd_aldebaran_validate_trap_override_request,
.set_wave_launch_trap_override = 
kgd_aldebaran_set_wave_launch_trap_override,
.set_wave_launch_mode = kgd_aldebaran_set_wave_launch_mode,
+   .set_address_watch = kgd_gfx_aldebaran_set_address_watch,
+   .clear_address_watch = kgd_gfx_aldebaran_clear_address_watch,
.get_iq_wait_times = kgd_gfx_v9_get_iq_wait_times,
.build_grace_period_packet_info = 
kgd_gfx_v9_build_grace_period_packet_info,
.program_trap_handler_settings = 
kgd_gfx_v9_program_trap_handler_settings,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
index fbdc1b7b1e42..6df215aba4c4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
@@ -413,6 +413,8 @@ const struct kfd2kgd_calls arcturus_kfd2kgd = {
.validate_trap_override_request = 
kgd_gfx_v9_validate_trap_override_request,
.set_wave_launch_trap_override = 
kgd_gfx_v9_set_wave_launch_trap_override,
.set_wave_launch_mode = kgd_gfx_v9_set_wave_launch_mode,
+   .set_address_watch

[PATCH 32/33] drm/amdkfd: add debug device snapshot operation