On 6/14/23 10:49 AM, Wang Ming wrote:
Identify issues that arise by using the tests/doubletest.cocci
semantic patch.Need to remove duplicate expression in if statement.
Signed-off-by: Wang Ming
Reviewed-by: Ammar Faizi
--
Ammar Faizi
Hi
Am 14.06.23 um 04:06 schrieb Sui Jingfeng:
On 2023/6/14 01:27, Sui Jingfeng wrote:
Wow, so many drivers get nuked!
On 2023/6/13 22:51, Thomas Zimmermann wrote:
All drivers initialize this field with drm_gem_prime_mmap(). Call
the function directly and remove the field. Simplifies the
Hi
Am 14.06.23 um 03:30 schrieb Sui Jingfeng:
The assignment "dst = map;" in the drm_fbdev_generic_damage_blit() function
is redundant because it has already been copied when the call to
drm_client_buffer_vmap() is finished. Therefore, this patch saves a useless
copy. No functional change.
On Tue, 13 Jun 2023, David Hildenbrand wrote:
> On 13.06.23 10:26, Kasireddy, Vivek wrote:
> >> On 12.06.23 09:10, Kasireddy, Vivek wrote:
> >>> Sorry for the late reply; I just got back from vacation.
> >>> If it is unsafe to directly use the subpages of a hugetlb page, then
> >>> reverting
> >>>
From: Sui Jingfeng
This patch adds PCI driver support on top of what we already have. Take
the GC1000 in LS7A1000/LS2K1000 as the first instance of the PCI device
driver. There is only one GPU core for the GC1000 in the LS7A1000 and
LS2K1000. Therefore, component frameworks can be avoided.
Cc:
From: Sui Jingfeng
Add a dedicate function to do the DMA configuration to the virtual master.
Also replace the >dev with dev.
Signed-off-by: Sui Jingfeng
---
drivers/gpu/drm/etnaviv/etnaviv_drv.c | 65 +++
1 file changed, 36 insertions(+), 29 deletions(-)
diff --git
From: Sui Jingfeng
Adding additional code path to allow bypass component frameworks, A
platform with a single GPU core could probably try the non-component
code path. This patch is for code sharing, no functional change.
Cc: Lucas Stach
Cc: Christian Gmeiner
Cc: Philipp Zabel
Cc: Bjorn
From: Sui Jingfeng
After introducing the etnaviv_of_first_available_node() helper, the
creation of the virtual master platform device can also be simplified.
So, switch to etnaviv_create_virtual_master() function.
Cc: Lucas Stach
Cc: Christian Gmeiner
Cc: Philipp Zabel
Cc: Bjorn Helgaas
Cc:
From: Sui Jingfeng
Also rename the virtual master platform device as etnaviv_platform_device,
for better reflection that it is a platform device, not a DRM device.
Another benefit is that we no longer need to call of_node_put() for three
different cases, Instead, we only need to call it once.
From: Sui Jingfeng
struct etnaviv_drm_private contains a lot of common resources that are
shared by all GPUs. This patch introduces two dedicated functions, which
is for the construction and destruction of instances of this structure.
The idea is to avoid leaking its members outside. The
From: Sui Jingfeng
Because it is also platform-dependent, there are environments where don't
have CLK subsystem support, for example, discreted PCI GPUs. So don't rage
quit if there is no CLK subsystem support.
For the GPU in LS7A1000 and LS2K1000, the working frequency of the GPU is
tuned by
From: Sui Jingfeng
Loongson CPUs maintain cache coherency by hardware, which means that the
data in the CPU cache is identical to the data in main system memory. As
for the peripheral device, most of Loongson chips chose to define the
peripherals as DMA coherent by default, device drivers do not
From: Sui Jingfeng
There is a Vivante GC1000 (v5037) in LS2K1000 and LS7A1000, this GPU is a
PCI device, and it has 2D and 3D cores in the same core. This series is
trying to add PCI device driver support to etnaviv.
v6:
* Fix build issue on system without CONFIG_PCI enabled
v7:
From: Sui Jingfeng
Because getting IRQ from a device is platform-dependent, PCI devices have
different methods for getting an IRQ. This patch is a preparation patch to
extend the driver for the PCI device support.
Cc: Lucas Stach
Cc: Christian Gmeiner
Cc: Philipp Zabel
Cc: Bjorn Helgaas
Cc:
On Fri, 09 Jun 2023 15:02:52 -0700, Vinay Belgaumkar wrote:
>
Hi Vinay,
> We were skipping when min_softlimit was equal to RPn. We need to apply
> it rergardless as efficient frequency will push the SLPC min to RPe.
regardless
> This will break scenarios where user sets a min softlimit < RPe
On 2023/6/14 01:27, Sui Jingfeng wrote:
Wow, so many drivers get nuked!
On 2023/6/13 22:51, Thomas Zimmermann wrote:
All drivers initialize this field with drm_gem_prime_mmap(). Call
the function directly and remove the field. Simplifies the code and
resolves a long-standing TODO item.
Use memdup_user() rather than duplicating its implementation. This is a
little bit restricted to reduce false positives.
./drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c:2813:13-20: WARNING
opportunity for memdup_user.
Reported-by: Abaci Robot
Closes:
DSI 6G v2.5.x+ supports a data-bus widen mode that allows DSI to send
48 bits of compressed data per pclk instead of 24.
For all chipsets that support this mode, enable it whenever DSC is
enabled as recommend by the hardware programming guide.
Only enable this for command mode as we are
Add a DPU INTF op to set the DATABUS_WIDEN register to enable the
databus-widen mode datapath.
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 3 +++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 12
DPU 5.x+ supports a databus widen mode that allows more data to be sent
per pclk. Enable this feature flag on all relevant chipsets.
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 ++-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 ++
2 files changed, 4
DPU 5.x+ and DSI 6G 2.5.x+ support a databus-widen mode that allows for
more compressed data to be transferred per pclk.
This series adds support for enabling this feature for both DPU and DSI
by doing the following:
1. Add a DPU_INTF_DATABUS_WIDEN feature flag
2. Add a DPU INTF op to set the
The assignment "dst = map;" in the drm_fbdev_generic_damage_blit() function
is redundant because it has already been copied when the call to
drm_client_buffer_vmap() is finished. Therefore, this patch saves a useless
copy. No functional change.
Signed-off-by: Sui Jingfeng
---
* Danilo Krummrich [230606 18:32]:
> Provide the driver indirection iterating over all DRM GPU VA spaces to
> enable the common 'gpuvas' debugfs file for dumping DRM GPU VA spaces.
>
> Signed-off-by: Danilo Krummrich
> ---
> drivers/gpu/drm/nouveau/nouveau_debugfs.c | 39
* Danilo Krummrich [230606 18:32]:
> Add infrastructure to keep track of GPU virtual address (VA) mappings
> with a decicated VA space manager implementation.
>
> New UAPIs, motivated by Vulkan sparse memory bindings graphics drivers
> start implementing, allow userspace applications to request
On 6/12/2023 5:09 PM, Dmitry Baryshkov wrote:
In several catalog entries we did not use existing MSM_DP_CONTROLLER_n
constants. Fill them in. Also use freshly defined MSM_DSI_CONTROLLER_n
for DSI interfaces.
Signed-off-by: Dmitry Baryshkov
---
On 6/13/2023 3:19 PM, Kuogee Hsieh wrote:
ince struct drm_dsc_config is stored at atomic_enable() instead
S got cut off in since
of display setup time during boot up, saving struct drm_dsc_config
at struct msm_display_info is not necessary. Lets drop the dsc member
from struct
On 6/13/2023 3:19 PM, Kuogee Hsieh wrote:
moving retrieving struct drm_dsc_cofnig from setup_display to
atomic_enable() and delete struct drm_dsc_config from
struct msm_display_info.
This needs re-wording.
Currently, struct drm_dsc_config is retrieved from DSI driver in
Alright, managed to figure out my MST woes! Just tested with nouveau and I see
no regressions :)
Reviewed-by: Lyude Paul
On Fri, 2023-06-09 at 18:49 +0800, Wayne Lin wrote:
> [Why]
> The sequence for collecting down_reply from source perspective should
> be:
>
> Request_n->repeat (get partial
On Tue, 13 Jun 2023 09:30:11 +0200, Neil Armstrong wrote:
> The DP output is shared with the USB3 SuperSpeed lanes and is
> usually connected to an USB-C port which Altmode is controlled
> by the PMIC Glink infrastructure.
>
> DT changes tying the DP controller to the USB-C port on the QRD
>
On Fri, 19 May 2023 20:07:24 +0200, Artur Weber wrote:
> Convert TI LP855X backlight controller bindings from TXT to YAML and,
> while we're at it, rework some of the code related to PWM handling.
> Also correct existing DTS files to avoid introducing new dtb_check
> errors.
>
> Signed-off-by:
moving retrieving struct drm_dsc_cofnig from setup_display to
atomic_enable() and delete struct drm_dsc_config from
struct msm_display_info.
Kuogee Hsieh (2):
drm/msm/dpu: retrieve DSI DSC struct through priv->dsi[0]
drm/msm/dpu: remove struct drm_dsc_config from struct msm_display_info
ince struct drm_dsc_config is stored at atomic_enable() instead
of display setup time during boot up, saving struct drm_dsc_config
at struct msm_display_info is not necessary. Lets drop the dsc member
from struct msm_display_info.
Signed-off-by: Kuogee Hsieh
---
Currently struct drm_dsc_config for DSI is populated at display
setup during system boot up. This mechanism works fine with
embedded display but not for pluggable displays as the
struct drm_dsc_config will become stale once external display
is unplugged.
Move storing of DSI DSC struct to
On 6/12/2023 5:09 PM, Dmitry Baryshkov wrote:
Follow the DP example and define MSM_DSI_CONTROLLER_n enumeration.
Signed-off-by: Dmitry Baryshkov
---
Reviewed-by: Abhinav Kumar
On 6/12/2023 5:09 PM, Dmitry Baryshkov wrote:
sm6115 and qcm2290 do not have INTF_0. Drop corresponding interface
definitions.
And sm6375 as you are touching that too
Signed-off-by: Dmitry Baryshkov
---
You can fix that while applying.
Reviewed-by: Abhinav Kumar
On 6/12/2023 5:09 PM, Dmitry Baryshkov wrote:
Each MERGE_3D block has just two registers. Correct the block length
accordingly.
Fixes: 4369c93cf36b ("drm/msm/dpu: initial support for merge3D hardware block")
Signed-off-by: Dmitry Baryshkov
---
LGTM,
Reviewed-by: Abhinav Kumar
On 6/12/2023 5:09 PM, Dmitry Baryshkov wrote:
During IRQ conversion we have lost the PP_DONE interrupts for sc7280
platform. This was left unnoticed, because this interrupt is only used
for CMD outputs and probably no sc7[12]80 systems use DSI CMD panels.
Fixes: 667e9985ee24 ("drm/msm/dpu:
On Tue, Jun 13, 2023 at 11:05 PM Lyude Paul wrote:
>
> We changed the semantics for this in:
>
> e761cc20946a ("drm/display/dp_mst: Handle old/new payload states in
> drm_dp_remove_payload()")
>
> But I totally forgot to update this properly in nouveau. So, let's do that.
>
> Signed-off-by:
[added Dmitry to Cc, since he suggested doing this in [1]]
On Tue, Jun 13, 2023 at 12:36:52AM +0100, Caleb Connolly wrote:
> The commit 007ac0262b0d ("drm/msm/dsi: switch to DRM_PANEL_BRIDGE")
> breaks panels which send DSI commands in their .unprepare callbacks.
> Migrate to using .disable for
On Tue, Jun 13, 2023 at 02:11:14PM -0600, Rob Herring wrote:
> A couple of display bridge properties are missing a type definition. Add
> the types to them.
>
> Signed-off-by: Rob Herring
Reviewed-by: Conor Dooley
Cheers,
Conor.
signature.asc
Description: PGP signature
We changed the semantics for this in:
e761cc20946a ("drm/display/dp_mst: Handle old/new payload states in
drm_dp_remove_payload()")
But I totally forgot to update this properly in nouveau. So, let's do that.
Signed-off-by: Lyude Paul
---
drivers/gpu/drm/nouveau/dispnv50/disp.c | 8 ++--
On Tue, Jun 13, 2023 at 02:10:22PM -0600, Rob Herring wrote:
> "current-num-sinks" is missing a type, add it.
>
> Signed-off-by: Rob Herring
Reviewed-by: Conor Dooley
Cheers,
Conor.
signature.asc
Description: PGP signature
Nice catch!
Reviewed-by: Lyude Paul
Will push upstream
On Fri, 2023-05-12 at 13:33 +0300, Natalia Petrova wrote:
> Pointer nv_encoder could be dereferenced at nouveau_connector.c
> in case it's equal to NULL by jumping to goto label.
> This patch adds a NULL-check to avoid it.
>
> Found by
Hi Doug
On 6/13/2023 12:33 PM, Doug Anderson wrote:
Hi,
On Mon, Jun 12, 2023 at 3:40 PM Dmitry Baryshkov
wrote:
On 13/06/2023 01:01, Bjorn Andersson wrote:
Using devres to depopulate the aux bus made sure that upon a probe
deferral the EDP panel device would be destroyed and recreated upon
Reviewed-by: Lyude Paul
Will push upstream in a bit
On Fri, 2023-05-12 at 14:15 +0300, Natalia Petrova wrote:
> Add checking for NULL before calling nouveau_connector_detect_depth() in
> nouveau_connector_get_modes() function because nv_connector->native_mode
> could be dereferenced there since
A couple of display bridge properties are missing a type definition. Add
the types to them.
Signed-off-by: Rob Herring
---
.../devicetree/bindings/display/bridge/analogix,dp.yaml | 1 +
.../devicetree/bindings/display/bridge/nxp,tda998x.yaml | 1 +
2 files changed, 2
"current-num-sinks" is missing a type, add it.
Signed-off-by: Rob Herring
---
.../devicetree/bindings/leds/backlight/kinetic,ktz8866.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git
a/Documentation/devicetree/bindings/leds/backlight/kinetic,ktz8866.yaml
Hi,
On Mon, Jun 12, 2023 at 3:40 PM Dmitry Baryshkov
wrote:
>
> On 13/06/2023 01:01, Bjorn Andersson wrote:
> > Using devres to depopulate the aux bus made sure that upon a probe
> > deferral the EDP panel device would be destroyed and recreated upon next
> > attempt.
> >
> > But the struct
Hi Wolfram,
> Subject: RE: [PATCH v5 01/11] i2c: Enhance i2c_new_ancillary_device API
>
> Hi Wolfram,
>
> Thanks for the feedback.
>
> > Subject: RE: [PATCH v5 01/11] i2c: Enhance i2c_new_ancillary_device
> > API
> >
> > Hi Wolfram,
> >
> > Thanks for the feedback.
> >
> > > Subject: Re:
syzbot suspects this issue was fixed by commit:
commit a5b44c4adb1699661d22e5152fb26885f30a2e4c
Author: Thomas Zimmermann
Date: Mon Mar 20 15:07:44 2023 +
drm/fbdev-generic: Always use shadow buffering
bisection log: https://syzkaller.appspot.com/x/bisect.txt?x=1025ee0728
start
Add a check to mtk_drm_mode_fb_create() that rejects any modifier that
is not the AFBC mode supported by MT8195's display overlays.
Tested by booting ChromeOS and verifying the UI works, and by running
the ChromeOS kms_addfb_basic binary, which has a test called
"addfb25-bad-modifier" that
On 2023-06-09 15:57:16, Jessica Zhang wrote:
> Add a DPU INTF op to set the DCE_DATA_COMPRESS bit to enable the
> DCE/DSC 1.2 datapath
>
> Note: For now, this op is called for command mode encoders only. Changes to
> set DATA_COMPRESS for video mode encoders will be posted along with DSC
> v1.2
Quoting Douglas Anderson (2023-06-13 06:58:13)
> Memory for the "struct device" for any given device isn't supposed to
> be released until the device's release() is called. This is important
> because someone might be holding a kobject reference to the "struct
> device" and might try to access one
On 13/06/2023 16:47, Sarah Walker wrote:
> This patch series adds the initial DRM driver for Imagination Technologies
> PowerVR
> GPUs, starting with those based on our Rogue architecture. It's worth pointing
> out that this is a new driver, written from the ground up, rather than a
> refactored
On 13/06/2023 16:47, Sarah Walker wrote:
> Add the device tree binding documentation for the Series AXE GPU used in
> TI AM62 SoCs.
>
I don't see improvements. That's a NAK :(
This is a friendly reminder during the review process.
It seems my previous comments were not fully addressed. Maybe
On Tue, Jun 13, 2023 at 08:17:13PM +0200, Krzysztof Kozlowski wrote:
> On 13/06/2023 09:04, Manikandan Muralidharan wrote:
> > Add new compatible string for the XLCD controller on SAM9X7 SoC.
> >
> > Signed-off-by: Manikandan Muralidharan
> > ---
> >
On 08/06/2023 18:37, Aradhya Bhatia wrote:
> The DSS controller on TI's AM625 SoC is an update from that on TI's
> AM65X SoC. The former has an additional OLDI TX on its first video port
> that helps output cloned video or WUXGA (1920x1200@60fps) resolution
> video output over a dual-link mode to
On Tue, Jun 13, 2023 at 12:34:18PM +0530, Manikandan Muralidharan wrote:
> Add new compatible string for the XLCD controller on SAM9X7 SoC.
You should probably indicate here why this is not compatible with the
existing SoCs that are supported. To hazard a guess, it is the HLCDC IP
(I forget the
On 13/06/2023 09:04, Manikandan Muralidharan wrote:
> Add new compatible string for the XLCD controller on SAM9X7 SoC.
>
> Signed-off-by: Manikandan Muralidharan
> ---
> Documentation/devicetree/bindings/mfd/atmel-hlcdc.txt | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git
On Tue, Jun 13, 2023 at 12:34:23PM +0530, Manikandan Muralidharan wrote:
> - XLCDC in SAM9X7 has different sets of registers and additional
> configuration bits when compared to previous HLCDC IP. Read/write
> operation on the controller registers is now separated using the
> XLCDC status flag.
>
On Tue, Jun 13, 2023 at 12:34:22PM +0530, Manikandan Muralidharan wrote:
> From: Durai Manickam KR
>
> Add compatible string check to differentiate XLCDC and HLCDC code
> within the atmel-hlcdc driver files.
>
> Signed-off-by: Durai Manickam KR
> Signed-off-by: Manikandan Muralidharan
> ---
>
On 6/13/23 9:47 AM, Sarah Walker wrote:
Acquire clock, regulator and register resources, and enable/map as
appropriate.
Signed-off-by: Sarah Walker
---
drivers/gpu/drm/imagination/Makefile | 1 +
drivers/gpu/drm/imagination/pvr_device.c | 271 +++
Hi,
On Thu, Jun 8, 2023 at 8:15 AM Doug Anderson wrote:
>
> Hi,
>
> On Wed, Jun 7, 2023 at 6:25 PM Su Hui wrote:
> >
> > Smatch error:buffer overflow 'ti_sn_bridge_refclk_lut' 5 <= 5.
> >
> > Fixes: cea86c5bb442 ("drm/bridge: ti-sn65dsi86: Implement the pwm_chip")
> > Signed-off-by: Su Hui
> >
Hi Wolfram,
Thanks for the feedback.
> Subject: RE: [PATCH v5 01/11] i2c: Enhance i2c_new_ancillary_device API
>
> Hi Wolfram,
>
> Thanks for the feedback.
>
> > Subject: Re: [PATCH v5 01/11] i2c: Enhance i2c_new_ancillary_device
> > API
> >
> > Hi everyone,
> >
> > > Perhaps we should first
On 13.06.23 10:26, Kasireddy, Vivek wrote:
Hi David,
On 12.06.23 09:10, Kasireddy, Vivek wrote:
Hi Mike,
Hi Vivek,
Sorry for the late reply; I just got back from vacation.
If it is unsafe to directly use the subpages of a hugetlb page, then reverting
this patch seems like the only
On 6/13/23 9:47 AM, Sarah Walker wrote:
Add the device tree binding documentation for the Series AXE GPU used in
TI AM62 SoCs.
Signed-off-by: Sarah Walker
---
.../devicetree/bindings/gpu/img,powervr.yaml | 71 +++
MAINTAINERS | 7 ++
2
We don't want to create a fence for every command submission. It's
only necessary when userspace provides a waitable token for submission.
This could be:
1) bo_handles, to be used with VIRTGPU_WAIT
2) out_fence_fd, to be used with dma_fence apis
3) a ring_idx provided with
On 2023/6/14 00:20, Sui Jingfeng wrote:
We will remote this workaround at next version.
remote -> remove
Wow, so many drivers get nuked!
On 2023/6/13 22:51, Thomas Zimmermann wrote:
All drivers initialize this field with drm_gem_prime_mmap(). Call
the function directly and remove the field. Simplifies the code and
resolves a long-standing TODO item.
Signed-off-by: Thomas Zimmermann
Reviewed-by:
* Danilo Krummrich [230606 18:31]:
> Split up the MA_STATE() macro such that components using the maple tree
> can easily inherit from struct ma_state and build custom tree walk
> macros to hide their internals from users.
>
> Example:
>
> struct sample_iterator {
> struct ma_state mas;
>
On 6/13/23 17:26, Raphael Gallais-Pou wrote:
On 6/13/23 16:52, Michael Nazzareno Trimarchi wrote:
Hi
On Tue, Jun 13, 2023 at 4:41 PM Philippe CORNU
wrote:
On 6/9/23 08:20, Dario Binacchi wrote:
Boards that use the STM32F{4,7} series have limited amounts of RAM. The
added parameter
Hi, Lucas
I love your patch, perhaps something to improve:
The MLCG stand for "Module Level Clock Gating",
without reading the commit message, I guess there may have people don't
know its meaning.
There are still more thing in this patch can only be understand relay on
guessing... :-)
On 6/13/2023 4:23 AM, Pekka Paalanen wrote:
On Mon, 12 Jun 2023 12:56:57 -0400
Christopher Braga wrote:
On 6/12/2023 5:21 AM, Pekka Paalanen wrote:
On Fri, 9 Jun 2023 19:11:25 -0400
Christopher Braga wrote:
On 6/9/2023 12:30 PM, Simon Ser wrote:
Hi Christopher,
On Friday, June
Hi,
On 2023/5/21 20:21, WANG Xuerui wrote:
+
+static int __init loongson_module_init(void)
+{
+ struct pci_dev *pdev = NULL;
+
+ if (video_firmware_drivers_only())
+ return -ENODEV;
+
+ /* Multiple video card workaround */
+ while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA
Hi Geert,
Thanks for the feedback.
> Subject: Re: [PATCH v5 01/11] i2c: Enhance i2c_new_ancillary_device API
>
> Hi Biju,
>
> On Tue, Jun 13, 2023 at 12:45 PM Biju Das
> wrote:
> > > Subject: Re: [PATCH v5 01/11] i2c: Enhance i2c_new_ancillary_device
> > > API On Mon, Jun 12, 2023 at 10:43 PM
Hi,
On Tue, Jun 13, 2023 at 5:06 AM Maxime Ripard wrote:
>
> > > What I'm trying to say is: could we just make it work by passing a bunch
> > > of platform_data, 2-3 callbacks and a device registration from the panel
> > > driver directly?
> >
> > I think I'm still confused about what you're
On Tue, Jun 13, 2023 at 01:31:40AM +0300, Dmitry Baryshkov wrote:
> On 13/06/2023 01:10, Bjorn Andersson wrote:
> > From: Bjorn Andersson
> >
> > Some platforms provides a mechanism for configuring the mapping between
> > (one or two) DisplayPort intfs and their PHYs.
> >
> > In particular
On 6/12/23 23:59, Stephen Rothwell wrote:
> Hi all,
>
> Changes since 20230609:
>
In file included from :
./../drivers/gpu/drm/i915/display/intel_display_power.h:255:70: error: 'struct
seq_file' declared inside parameter list will not be visible outside of this
definition or declaration
On 6/1/2023 8:59 AM, Alan Previn wrote:
In the case of failed suspend flow or cases where the kernel does not go
into full suspend but goes from suspend_prepare back to resume_complete,
we get called for a pm_complete but without runtime_pm guaranteed.
Thus, ensure we take the runtime_pm when
On Tue, Jun 13, 2023 at 11:05 AM Thomas Zimmermann wrote:
>
> All drivers initialize this field with drm_gem_prime_mmap(). Call
> the function directly and remove the field. Simplifies the code and
> resolves a long-standing TODO item.
>
> Signed-off-by: Thomas Zimmermann
Series is:
On 6/13/23 16:52, Michael Nazzareno Trimarchi wrote:
> Hi
>
> On Tue, Jun 13, 2023 at 4:41 PM Philippe CORNU
> wrote:
>>
>>
>> On 6/9/23 08:20, Dario Binacchi wrote:
>>> Boards that use the STM32F{4,7} series have limited amounts of RAM. The
>>> added parameter allows users to size, within
Implement job submission ioctl. Job scheduling is implemented using
drm_sched.
Jobs are submitted in a stream format. This is intended to allow the UAPI
data format to be independent of the actual FWIF structures in use, which
vary depending on the GPU in use.
The stream formats are documented
Add the Series AXE GPU node to the AM62 device tree.
Signed-off-by: Sarah Walker
---
arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi
b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi
index
This adds the basic skeleton of the driver. The driver registers
itself with DRM on probe. Ioctl handlers are currently implemented
as stubs.
Signed-off-by: Sarah Walker
---
MAINTAINERS | 1 +
drivers/gpu/drm/Kconfig | 2 +
From: Matt Coster
Signed-off-by: Matt Coster
---
include/linux/sizes.h | 9 +
1 file changed, 9 insertions(+)
diff --git a/include/linux/sizes.h b/include/linux/sizes.h
index 84aa448d8bb3..c3a00b967d18 100644
--- a/include/linux/sizes.h
+++ b/include/linux/sizes.h
@@ -47,8 +47,17 @@
Implement ioctls to create and destroy free lists and HWRT datasets. Free
lists are used for GPU-side memory allocation during geometry processing.
HWRT datasets are the FW-side structures representing render targets.
Signed-off-by: Sarah Walker
---
drivers/gpu/drm/imagination/Makefile|
The infrastructure includes parsing of the firmware image, initialising
FW-side structures, handling the kernel and firmware command
ringbuffers and starting & stopping the firmware processor.
This patch also adds the necessary support code for the META firmware
processor.
This patch depends on:
Add the UAPI implementation for the PowerVR driver.
Signed-off-by: Sarah Walker
---
MAINTAINERS|1 +
include/uapi/drm/pvr_drm.h | 1333
2 files changed, 1334 insertions(+)
create mode 100644 include/uapi/drm/pvr_drm.h
diff --git
Read the GPU ID register at probe time and select the correct
features/quirks/enhancements. Use the GPU ID to form the firmware
file name and load the firmware.
The features/quirks/enhancements arrays are currently hardcoded in
the driver for the supported GPUs. We are looking at moving this
Implement ioctls for the creation and destruction of contexts. Contexts are
used for job submission and each is associated with a particular job type.
Signed-off-by: Sarah Walker
---
drivers/gpu/drm/imagination/Makefile | 4 +
drivers/gpu/drm/imagination/pvr_cccb.c| 230
Firmware trace is exposed at /sys/debug/dri//pvr_fw/trace_0.
Trace is enabled via the group mask at
/sys/debug/dri//pvr_params/fw_trace_mask.
Signed-off-by: Sarah Walker
---
drivers/gpu/drm/imagination/Makefile | 4 +
drivers/gpu/drm/imagination/pvr_debugfs.c | 53 +++
Add support for the MIPS firmware processor, used in the Series AXE GPU.
The MIPS firmware processor uses a separate MMU to the rest of the GPU, so
this patch adds support for that as well.
Signed-off-by: Sarah Walker
---
drivers/gpu/drm/imagination/Makefile | 4 +-
Add documentation for the UAPI and for the virtual memory design.
Signed-off-by: Sarah Walker
---
Documentation/gpu/drivers.rst | 2 +
Documentation/gpu/imagination/index.rst | 14 +
Documentation/gpu/imagination/uapi.rst| 174 +++
This patch series adds the initial DRM driver for Imagination Technologies
PowerVR
GPUs, starting with those based on our Rogue architecture. It's worth pointing
out that this is a new driver, written from the ground up, rather than a
refactored version of our existing downstream driver
Add the device tree binding documentation for the Series AXE GPU used in
TI AM62 SoCs.
Signed-off-by: Sarah Walker
---
.../devicetree/bindings/gpu/img,powervr.yaml | 71 +++
MAINTAINERS | 7 ++
2 files changed, 78 insertions(+)
create mode
Add power management to the driver, using runtime pm. The power off
sequence depends on firmware commands which are not implemented in this
patch.
Signed-off-by: Sarah Walker
---
drivers/gpu/drm/imagination/Makefile | 1 +
drivers/gpu/drm/imagination/pvr_device.c | 20 +-
Acquire clock, regulator and register resources, and enable/map as
appropriate.
Signed-off-by: Sarah Walker
---
drivers/gpu/drm/imagination/Makefile | 1 +
drivers/gpu/drm/imagination/pvr_device.c | 271 +++
drivers/gpu/drm/imagination/pvr_device.h | 214
All drivers initialize this field with drm_gem_prime_mmap(). Call
the function directly and remove the field. Simplifies the code and
resolves a long-standing TODO item.
Signed-off-by: Thomas Zimmermann
---
Documentation/gpu/todo.rst | 9 -
Only the msm driver provides its own implementation of gem_prime_mmap
from struct drm_driver. All other drivers use the drm_gem_prime_mmap()
helper.
Initialize the mmap offset when constructing the buffer object in msm
and reduce the gem_prime_mmap code to the generic helper. Prepares
msm for the
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