Am 19.09.23 um 07:01 schrieb Matthew Brost:
Add scheduler submit ready, stop, and start helpers to hide the
implementation details of the scheduler from the drivers.
Signed-off-by: Matthew Brost
Reviewed-by: Christian König for this one.
No idea when I have time to look into the rest :(
Am 18.09.23 um 16:57 schrieb Danilo Krummrich:
[SNIP]
What this component should do is to push jobs to the hardware and not
overview their execution, that's the job of the driver.
While, generally, I'd agree, I think we can't really get around having
something that
frees the job once it's
Am 19.09.23 um 03:26 schrieb Zack Rusin:
On Mon, 2023-09-18 at 16:21 -0400, Alex Deucher wrote:
!! External Email
On Mon, Sep 18, 2023 at 3:06 PM Thomas Hellström
wrote:
On 9/18/23 17:52, Zack Rusin wrote:
On Mon, 2023-09-18 at 17:13 +0200, Thomas Hellström wrote:
Hi,
On 9/18/23 16:56,
If the TDR is set to a value, it can fire before a job is submitted in
drm_sched_main. The job should be always be submitted before the TDR
fires, fix this ordering.
v2:
- Add to pending list before run_job, start TDR after (Luben, Boris)
Signed-off-by: Matthew Brost
---
Add helper to queue TDR immediately for current and future jobs. This
will be used in XE, new Intel GPU driver, to trigger the TDR to cleanup
a drm_scheduler that encounter errors.
v2:
- Drop timeout args, rename function, use mod delayed work (Luben)
Signed-off-by: Matthew Brost
---
Rather than a global modparam for scheduling policy, move the scheduling
policy to scheduler so user can control each scheduler policy.
v2:
- s/DRM_SCHED_POLICY_MAX/DRM_SCHED_POLICY_COUNT (Luben)
- Only include policy in scheduler (Luben)
v3:
- use a ternary operator as opposed to an
If the TDR is set to a very small value it can fire before the
submission is started in the function drm_sched_start. The submission is
expected to running when the TDR fires, fix this ordering so this
expectation is always met.
Signed-off-by: Matthew Brost
---
In XE, the new Intel GPU driver, a choice has made to have a 1 to 1
mapping between a drm_gpu_scheduler and drm_sched_entity. At first this
seems a bit odd but let us explain the reasoning below.
1. In XE the submission order from multiple drm_sched_entity is not
guaranteed to be the same
Add Matthew Brost to maintainers of GPU scheduler
Signed-off-by: Matthew Brost
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 60c2d97e427b..43c51d1abee5 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -7134,6 +7134,7 @@ F:
DRM_SCHED_POLICY_SINGLE_ENTITY creates a 1 to 1 relationship between
scheduler and entity. No priorities or run queue used in this mode.
Intended for devices with firmware schedulers.
v2:
- Drop sched / rq union (Luben)
v3:
- Don't pick entity if stopped in drm_sched_select_entity (Danilo)
Rather than call free_job and run_job in same work item have a dedicated
work item for each. This aligns with the design and intended use of work
queues.
v2:
- Test for DMA_FENCE_FLAG_TIMESTAMP_BIT before setting
timestamp in free_job() work item (Danilo)
v3:
- Drop forward dec of
Also add a lockdep assert to drm_sched_start_timeout.
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/scheduler/sched_main.c | 23 +--
1 file changed, 13 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/scheduler/sched_main.c
Add scheduler submit ready, stop, and start helpers to hide the
implementation details of the scheduler from the drivers.
Signed-off-by: Matthew Brost
---
.../drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 15 +++
As a prerequisite to merging the new Intel Xe DRM driver [1] [2], we
have been asked to merge our common DRM scheduler patches first.
This a continuation of a RFC [3] with all comments addressed, ready for
a full review, and hopefully in state which can merged in the near
future. More details of
`strncpy` is deprecated for use on NUL-terminated destination strings [1].
We should prefer more robust and less ambiguous string interfaces.
A suitable replacement is `strscpy` [2] due to the fact that it
guarantees NUL-termination on the destination buffer without
unnecessarily NUL-padding.
`strncpy` is deprecated for use on NUL-terminated destination strings [1].
We should prefer more robust and less ambiguous string interfaces.
Since `chan->base.name` is expected to be NUL-terminated, a suitable
replacement is `strscpy` [2] due to the fact that it guarantees
NUL-termination on
Add is_sec flag to identify current mtk_drm_plane is secure.
Add mtk_plane_is_sec_fb() to check current drm_framebuffer is secure.
Signed-off-by: Jason-JH.Lin
---
drivers/gpu/drm/mediatek/mtk_drm_plane.h | 2 ++
1 file changed, 2 insertions(+)
diff --git
Add secure layer config support for ovl_adaptor and sub driver mdp_rdma.
Signed-off-by: Jason-JH.Lin
---
drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 3 +++
drivers/gpu/drm/mediatek/mtk_mdp_rdma.c | 11 ---
drivers/gpu/drm/mediatek/mtk_mdp_rdma.h | 2 ++
3 files
Add mtk_ddp_sec_write to configure secure buffer information to
cmdq secure packet data.
Then secure cmdq driver will use these information to configure
curresponding secure DRAM address to HW overlay in secure world.
Signed-off-by: Jason-JH.Lin
---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c |
The patch series provides drm driver support for enabling secure video
path (SVP) playback on MediaiTek hardware in the Linux kernel.
Memory Definitions:
secure memory - Memory allocated in the TEE (Trusted Execution
Environment) which is inaccessible in the REE (Rich Execution
Environment, i.e.
To add secure flow support for mediatek-drm, each crtc have to
create a secure cmdq mailbox channel. Then cmdq packets with
display HW configuration will be sent to secure cmdq mailbox channel
and configured in the secure world.
Each crtc have to use secure cmdq interface to configure some secure
Add secure layer config support for ovl.
Signed-off-by: Jason-JH.Lin
---
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 3 ++
drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 31 +--
.../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 12 +++
Add secure buffer control flow to mtk_drm_gem.
When user space takes DRM_MTK_GEM_CREATE_ENCRYPTED flag and size
to create a mtk_drm_gem object, mtk_drm_gem will find a matched size
dma buffer from secure dma-heap and bind it to mtk_drm_gem object.
Signed-off-by: Jason-JH.Lin
---
Add a secure mailbox channel to support secure video path on
vdosys0 and vdosys1.
Signed-off-by: Jason-JH.Lin
---
arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
Add get_sec_port interface to ddp_comp to get the secure port settings
from ovl and ovl_adaptor.
Then mediatek-drm will use secure cmdq driver to configure DRAM access
permission in secure world by their secure port settings.
Signed-off-by: Jason-JH.Lin
---
From: CK Hu
Add an interface to allocate MediaTek GEM buffers, allow the IOCTLs
to be used by render nodes.
This patch also sets the RENDER driver feature.
Signed-off-by: CK Hu
Signed-off-by: Nicolas Boichat
Signed-off-by: Philipp Zabel
Signed-off-by: Jason-JH.Lin
Reviewed-by: Daniel Kurtz
Add DRM_MTK_GEM_CREATED_ENCRYPTTED flag to allocate a secure buffer
to support secure video path feature.
Signed-off-by: Jason-JH.Lin
---
include/uapi/drm/mediatek_drm.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/uapi/drm/mediatek_drm.h b/include/uapi/drm/mediatek_drm.h
index
On Sun, 17 Sept 2023 at 02:28, Danilo Krummrich wrote:
>
> Always stop and re-start the scheduler in order to let the scheduler
> free up the timedout job in case it got signaled. In case of exec jobs
> the job type specific callback will take care to signal all fences and
> tear down the
On Sat, 16 Sept 2023 at 11:15, Danilo Krummrich wrote:
>
> Fix the following warning.
>
> drivers/gpu/drm/nouveau/nouveau_fence.c:210:45: sparse: sparse:
> incorrect type in initializer (different address spaces)
> @@ expected struct nouveau_channel *chan
> @@ got struct
Hi Angelo,
Thank you for the patch.
On Monday, September 18, 2023 11:01 PM, AngeloGioacchino Del Regno
wrote:
> When external bridges are attached with
> DRM_BRIDGE_ATTACH_NO_CONNECTOR,
> the panel bridge may also get the same flag, but in the .attach()
> callback for the panel bridge a device
>
> As you may have gathered from the MAINTAINERS patch I just sent out, I
> have resigned from my position at Red Hat, and will be stepping back
> from nouveau development.
>
> This is a personal decision that I've been mulling over for a number
> of years now, and I feel that with GSP-RM greatly
On Mon, 2023-09-18 at 16:21 -0400, Alex Deucher wrote:
> !! External Email
>
> On Mon, Sep 18, 2023 at 3:06 PM Thomas Hellström
> wrote:
> >
> >
> > On 9/18/23 17:52, Zack Rusin wrote:
> > > On Mon, 2023-09-18 at 17:13 +0200, Thomas Hellström wrote:
> > > > Hi,
> > > >
> > > > On 9/18/23 16:56,
To fully cover drm_fb_blit(), add format conversion tests that are only
supported through drm_fb_blit().
Signed-off-by: Arthur Grillo
Reviewed-by: Maíra Canal
---
drivers/gpu/drm/tests/drm_format_helper_test.c | 142 +
1 file changed, 142 insertions(+)
diff --git
Add a call to drm_fb_blit() on existing format conversion tests that
has support.
Signed-off-by: Arthur Grillo
Reviewed-by: Maíra Canal
---
drivers/gpu/drm/tests/drm_format_helper_test.c | 143 +
1 file changed, 143 insertions(+)
diff --git
This patchset tests the drm_fb_blit() function.
As this function can be used with already tested formats, the first
patch adds calls to drm_fb_blit() on the tests of supported formats.
Some supported formats were not yet covered by the existing tests
because they are only supported by
Hi,
On 9/15/23 10:28, Jocelyn Falempe wrote:
> This introduces a new drm panic handler, which displays a message when a
> panic occurs.
> So when fbcon is disabled, you can still see a kernel panic.
>
> This is one of the missing feature, when disabling VT/fbcon in the kernel:
>
On 18/09/23 19:57, Arthur Grillo wrote:
> This patchset tests the drm_fb_blit() function.
>
> As this function can be used with already tested formats, the first
> patch adds calls to drm_fb_blit() on the tests of supported formats.
>
> Some supported formats were not yet covered by the
Add a call to drm_fb_blit() on existing format conversion tests that
has support.
Signed-off-by: Arthur Grillo
---
drivers/gpu/drm/tests/drm_format_helper_test.c | 143 +
1 file changed, 143 insertions(+)
diff --git a/drivers/gpu/drm/tests/drm_format_helper_test.c
This patchset tests the drm_fb_blit() function.
As this function can be used with already tested formats, the first
patch adds calls to drm_fb_blit() on the tests of supported formats.
Some supported formats were not yet covered by the existing tests
because they are only supported by
On 9/19/23 00:19, Lyude Paul wrote:
BTW - Would you like me to review work like this? I'm totally happy to do
that, although I'm not terribly familiar with these parts of nouveau/drm (but
I'm always willing to learn, and would like to know more about these areas
anyway :)
Of course, that's
On Mon, 18 Sep 2023 22:58:53 +1000, John Watts wrote:
> This is a small 3.5" 640x480 IPS LCD panel.
>
> Signed-off-by: John Watts
> ---
> .../display/panel/fascontek,fs035vg158.yaml | 56 +++
> 1 file changed, 56 insertions(+)
> create mode 100644
>
On Mon, 18 Sep 2023 22:58:51 +1000, John Watts wrote:
> Remove common properties listed in common yaml files.
> Add required properties needed to describe the panel.
>
> Signed-off-by: John Watts
> ---
> .../bindings/display/panel/leadtek,ltk035c5444t.yaml | 8 ++--
> 1 file changed,
Reviewed-by: Lyude Paul
I assume you need me to push this to drm-misc?
On Fri, 2023-09-15 at 15:59 +0300, Dan Carpenter wrote:
> The u_memcpya() function is supposed to return error pointers on
> error. Returning NULL will lead to an Oops.
>
> Fixes: 68132cc6d1bc ("nouveau/u_memcpya: use
BTW - Would you like me to review work like this? I'm totally happy to do
that, although I'm not terribly familiar with these parts of nouveau/drm (but
I'm always willing to learn, and would like to know more about these areas
anyway :)
…if the answer is yes, this patch looks fine to me so far -
On 14/09/2023 05:12, Daniel Vetter wrote:
On Thu, Sep 14, 2023 at 03:33:41PM +0900, Tetsuo Handa wrote:
On 2023/09/14 6:08, Thomas Gleixner wrote:
Maybe the VKMS people need to understand locking in the first place. The
first thing I saw in this code is:
static enum hrtimer_restart
Oops, my bad. I'm new to ARM development, so I forgot to update dt-bindings.
You should see a patch dropping soon (or already did), although I decided to
move to a new email address (which hopefully shouldn't cause any issues).
On 18/09/2023 12:07, Robert Foss wrote:
> On Sat, Sep 9, 2023 at
On 15/09/2023 12:08, Daniel Stone wrote:
Hey,
On Thu, 14 Sept 2023 at 10:54, Maxime Ripard wrote:
On Tue, Sep 12, 2023 at 02:16:41PM +0100, Daniel Stone wrote:
Hopefully less mangled formatting this time: turns out Thunderbird +
plain text is utterly unreadable, so that's one less MUA
Le mardi 19 septembre 2023 à 07:08 +1000, John Watts a écrit :
> On Mon, Sep 18, 2023 at 11:01:15PM +0200, Paul Cercueil wrote:
> > The datasheet does say a 5ms sleep time is necesary after a reset.
> > I
> > assume the 120ms delay you quote is when a *software* reset is
> > performed in Sleep-out
In cfb_copyarea(), when initializing *unsigned long const* bits_per_line
__u32 typed fb_fix_screeninfo::line_length gets multiplied by 8u -- which
might overflow __u32; multiplying by 8UL instead should fix that...
Also, that bits_per_line constant is used to advance *unsigned* src_idx
and dst_idx
In sys_copyarea(), when initializing *unsigned long const* bits_per_line
__u32 typed fb_fix_screeninfo::line_length gets multiplied by 8u -- which
might overflow __u32; multiplying by 8UL instead should fix that...
Also, that bits_per_line constant is used to advance *unsigned* src_idx
and dst_idx
Here are 2 patches against the 'master' branch of Linus' 'linux.git' repo...
In {cfb|sys}_copyarea(), when initializing *unsigned long const* bits_per_line
__u32 typed fb_fix_screeninfo::line_length gets multiplied by 8u which might
overflow __u32; this whole *struct* fb_fix_screeninfo seems to
Hi John,
Le mardi 19 septembre 2023 à 06:52 +1000, John Watts a écrit :
> On Mon, Sep 18, 2023 at 01:19:03PM -0700, Jessica Zhang wrote:
> > Hi John,
> >
> > Just wondering, is there some context to this change? I.e., was
> > this made to
> > fix a specific issue?
> >
> > This seems like a
On 9/18/2023 5:58 AM, John Watts wrote:
This display is extremely similar to the LTK035C5444T, but still has
some minor variations in panel initialization.
Signed-off-by: John Watts
Reviewed-by: Jessica Zhang
---
.../gpu/drm/panel/panel-newvision-nv3052c.c | 223 ++
On 9/18/2023 5:58 AM, John Watts wrote:
The panel needs us to wait 120ms between exiting and entering sleep.
Guarantee that by always waiting 150ms before entering sleep mode.
Hi John,
Same question as the last patch -- is this a fix for something?
Thanks,
Jessica Zhang
Signed-off-by:
On Mon, Sep 18, 2023 at 3:06 PM Thomas Hellström
wrote:
>
>
> On 9/18/23 17:52, Zack Rusin wrote:
> > On Mon, 2023-09-18 at 17:13 +0200, Thomas Hellström wrote:
> >> Hi,
> >>
> >> On 9/18/23 16:56, Thomas Hellström wrote:
> >>> Hi Zack, Christian
> >>>
> >>> On 9/18/23 13:36, Christian König
On 9/18/2023 5:58 AM, John Watts wrote:
The current code waits after resets for 5 to 20 milliseconds.
This is appropriate when resetting a sleeping panel, but an awake panel
requires at least 120ms of waiting.
Sleep for 150ms so the panel always completes it reset properly.
Signed-off-by:
On 9/15/2023 5:41 PM, Dmitry Baryshkov wrote:
On Sat, 16 Sept 2023 at 00:38, Kuogee Hsieh wrote:
Currently DP driver use drm_helper_hpd_irq_event(), bypassing drm bridge
framework, to report HPD status changes to user space frame work.
Replace it with drm_bridge_hpd_notify() since DP driver
On 9/15/2023 5:59 AM, Dan Carpenter wrote:
The irq_of_parse_and_map() function returns zero on error. It
never returns negative error codes. Fix the check.
Fixes: a689554ba6ed ("drm/msm: Initial add DSI connector support")
Signed-off-by: Dan Carpenter
---
Le 18/09/2023 à 05:10, Gustavo A. R. Silva a écrit :
On 9/18/23 12:46, Christophe JAILLET wrote:
If 'list_limit' is set to a very high value, 'lsize' computation could
overflow if 'head.count' is big enough.
In such a case, udmabuf_create() will access to memory beyond 'list'.
Use
Add CMDQ secure driver support for GCE0.
CMDQ secure driver will requset a GCE HW thread in GCE0 core to support
sending a CMDQ packet through secure mailbox.
Then ask GCE HW thread to excute commands in the secure world.
Signed-off-by: Jason-JH.Lin
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi
Add CMDQ driver support for mt8188 by adding its compatible and
driver data in CMDQ driver.
Signed-off-by: Jason-JH.Lin
---
drivers/mailbox/mtk-cmdq-mailbox.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c
b/drivers/mailbox/mtk-cmdq-mailbox.c
To support secure video path feature, GCE have to read/write registgers
in the secure world. GCE will enable the secure access permission to the
HW who wants to access the secure content buffer.
Add CMDQ secure mailbox driver to make CMDQ client user is able to
sending their HW settings to the
Add mboxes to define a GCE loopping thread as a secure irq handler.
Add mediatek,event to define a GCE software event siganl as a secure
irq.
These 2 properties are required for CMDQ secure driver.
Signed-off-by: Jason-JH.Lin
---
.../mailbox/mediatek,gce-mailbox.yaml | 30
Add cmdq_pkt_write_s_reg_value to CMDQ driver.
It appends write_s command to the command buffer in a CMDQ packet,
ask GCE to excute a write instruction to write a value to a register
with low 16 bits physical address offset.
Signed-off-by: Jason-JH.Lin
---
CMDQ client can use a loop flag for the CMDQ packet to make current
command buffer jumps to the beginning when GCE executes to the end
of commands buffer.
GCE irq occurs when GCE executes to the end of command instruction.
If the CMDQ packet is a loopping command, GCE irq handler can not
delete
Add mt8188 support for CMDQ secure driver.
Signed-off-by: Jason-JH.Lin
---
drivers/mailbox/mtk-cmdq-mailbox.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c
b/drivers/mailbox/mtk-cmdq-mailbox.c
index 3940b9f8e774..4e047dc916b9 100644
---
Add cmdq_insert_backup_cookie to append some commands before EOC:
1. Get GCE HW thread execute count from the GCE HW register.
2. Add 1 to the execute count and then store into a shared memory.
3. Set a software event siganl as secure irq to GCE HW.
Since the value of execute count + 1 is stored
Add cmdq_mbox_stop to disable GCE thread.
To support the error handling or the stop flow of the GCE loopping
thread, lopping thread user can call cmdq_mbox_stop to disable the
GCE HW thread.
Signed-off-by: Jason-JH.Lin
---
drivers/mailbox/mtk-cmdq-mailbox.c | 6 ++
For the Secure Video Path (SVP) feature, inculding the memory stored
secure video content, the registers of display HW pipeline and the
HW configure operations are required to execute in the secure world.
So using a CMDQ secure driver to make all display HW registers
configuration secure DRAM
Add mt8195 support for CMDQ secure driver.
Signed-off-by: Jason-JH.Lin
---
drivers/mailbox/mtk-cmdq-mailbox.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c
b/drivers/mailbox/mtk-cmdq-mailbox.c
index 4e047dc916b9..d27d033c587d 100644
---
CMDQ driver will probe a secure CMDQ driver when has_sec flag
in platform data is true and its device node in dts has defined a
event id of CMDQ_SYNC_TOKEN_SEC_EOF.
Signed-off-by: Jason-JH.Lin
---
drivers/mailbox/mtk-cmdq-mailbox.c | 40 ++--
Add cmdq_pkt_logic_command to support match operation.
cmdq_pkt_logic_command can append logic command to the CMDQ packet,
ask GCE to execute a arithematic calculate instruction,
such as add, subtract, multiply, AND, OR and NOT, etc.
Note that all instructions just accept unsigned calculate.
If
Add cmdq_pkt_finalize_loop to CMDQ driver.
cmdq_pkt_finalize_loop appends end of command(EOC) instruction and
jump to start of command buffer instruction to make the command
buffer loopable.
Signed-off-by: Jason-JH.Lin
---
drivers/soc/mediatek/mtk-cmdq-helper.c | 23 +++
CMDQ_SYNC_TOKEN_SECURE_THR_EOF is used as secure irq to notify CMDQ
driver in the normal world that GCE secure thread has completed a task
in thee secure world.
Signed-off-by: Jason-JH.Lin
---
include/dt-bindings/gce/mt8195-gce.h | 6 ++
1 file changed, 6 insertions(+)
diff --git
GCE has specific purpose registers, abbreviated as SPR.
Client can us SPR to store data or programs.
In CMDQ driver, it allows client to STORE or LOAD data into SPR.
The value stored in SPR will be cleared after reset GCE HW thread.
There are 4 SPR (register index 0 - 3) in every GCE HW thread.
On 9/18/23 12:46, Christophe JAILLET wrote:
If 'list_limit' is set to a very high value, 'lsize' computation could
overflow if 'head.count' is big enough.
In such a case, udmabuf_create() will access to memory beyond 'list'.
Use size_mul() to saturate the value, and have memdup_user() fail.
If 'list_limit' is set to a very high value, 'lsize' computation could
overflow if 'head.count' is big enough.
In such a case, udmabuf_create() will access to memory beyond 'list'.
Use size_mul() to saturate the value, and have memdup_user() fail.
Fixes: fbb0de795078 ("Add udmabuf misc device")
On Thu, Aug 31, 2023 at 8:21 AM Evan Quan wrote:
>
> Due to electrical and mechanical constraints in certain platform designs
> there may be likely interference of relatively high-powered harmonics of
> the (G-)DDR memory clocks with local radio module frequency bands used
> by Wifi 6/6e/7.
>
>
On 9/15/2023 6:21 PM, Dmitry Baryshkov wrote:
On Sat, 16 Sept 2023 at 00:38, Kuogee Hsieh wrote:
Add pm_runtime_force_suspend()/resume() to complete incorporating pm
runtime framework into DP driver. Both dp_pm_prepare() and dp_pm_complete()
are added to set hpd_state to correct state. After
On 9/18/23 17:52, Zack Rusin wrote:
On Mon, 2023-09-18 at 17:13 +0200, Thomas Hellström wrote:
Hi,
On 9/18/23 16:56, Thomas Hellström wrote:
Hi Zack, Christian
On 9/18/23 13:36, Christian König wrote:
Hi Zack,
adding Thomas and Daniel.
I briefly remember that I talked with Thomas and
On 9/15/2023 6:51 PM, Dmitry Baryshkov wrote:
On Sat, 16 Sept 2023 at 00:38, Kuogee Hsieh wrote:
The is_connected flag is set to true after DP mainlink successfully
finish link training. Replace the is_connected flag with link_ready
finishes.
Also this is not a replace, this patch renames
On 9/15/2023 5:29 PM, Dmitry Baryshkov wrote:
On Sat, 16 Sept 2023 at 00:38, Kuogee Hsieh wrote:
Currently the dp_display_irq_handler() is executed at msm_dp_modeset_init()
which ties irq registration to the DPU device's life cycle, while depending on
resources that are released as the DP
Hi,
On Mon, Jul 3, 2023 at 6:21 AM Linus Walleij wrote:
>
> This is two patches fixing things I would normally complain about
> in reviews, but alas I missed this one, so I go in and fix it up
> myself.
>
> Discovering that a completely unrelated driver has been merged
> into this panel driver I
On 18/08/2023 17:21, Aradhya Bhatia wrote:
Add support for the DSS controller on TI's AM62A7 SoC in the tidss
driver.
This contrller has 2 video pipelines that can render 2 video planes on
"controller".
over a screen, using the overlay managers. The output of the DSS comes
from video port 2
When external bridges are attached with DRM_BRIDGE_ATTACH_NO_CONNECTOR,
the panel bridge may also get the same flag, but in the .attach()
callback for the panel bridge a device link is added only when this
flag is not present; To make things worse, the .detach() callback
tries to delete the device
On 9/18/23 13:03, Christian König wrote:
Am 16.09.23 um 19:52 schrieb Danilo Krummrich:
On 9/12/23 16:47, Matthew Brost wrote:
On Tue, Sep 12, 2023 at 11:57:30AM +0200, Christian König wrote:
Am 12.09.23 um 04:16 schrieb Matthew Brost:
Wait for pending jobs to be complete before signaling
From: Tomer Tayar
Add debug prints to dump the content of the SG table which is prepared
when the dma-buf map op is called.
Signed-off-by: Tomer Tayar
Reviewed-by: Oded Gabbay
Signed-off-by: Oded Gabbay
---
drivers/accel/habanalabs/common/memory.c | 7 +++
1 file changed, 7
From: Tomer Tayar
In some cases the calculated number of required entries for the dma-buf
SG table is wrong. For example, if the page size is larger than both the
dma max segment size of the importer device and from the exported side,
or if the exported size is part of a phys_pg_pack that is
From: Ariel Suller
FW shutdown preparation status was added to spec.
Signed-off-by: Ariel Suller
Reviewed-by: Oded Gabbay
Signed-off-by: Oded Gabbay
---
drivers/accel/habanalabs/common/firmware_if.c | 4
1 file changed, 4 insertions(+)
diff --git
From: Dafna Hirschfeld
There are cases such when FW runs MBIST, that preboot is expected to take
longer than the usual. In such cases the firmware reports status
SECURITY_READY/IN_PREBOOT and we extend the timeout waiting for it.
This is currently implemented for Gaudi2 only.
Signed-off-by:
From: Tomer Tayar
The device_address member of 'struct hl_dmabuf_priv' is used only when
virtual device memory is not supported and dma-buf is exported from
address.
Set the value of this field only when it is relevant, and add "phys" to
its name so it would be clearer that it can't be a device
From: Dafna Hirschfeld
update hl_boot_if.h from specs to include
CPU_BOOT_STATUS_FW_SHUTDOWN_PREP
Signed-off-by: Dafna Hirschfeld
Reviewed-by: Oded Gabbay
Signed-off-by: Oded Gabbay
---
include/linux/habanalabs/hl_boot_if.h | 2 ++
1 file changed, 2 insertions(+)
diff --git
From: Tomer Tayar
On devices with virtual device memory (Gaudi2 onwards), user can provide
an offset within an allocated device memory from which he wants to
export a dma-buf object.
The offset value is verified by driver, but it is not taken into
consideration when the importer driver maps the
From: farah kassabri
Currently we use dynamic allocation inside the irq handler
in order to allocate free node to be used for the free jobs.
This operation is expensive, especially when we deal with large
burst of events records that get released at the same time.
The alternative is to have
From: farah kassabri
Currently driver maintain one list for both pending user interrupts
which seeks to wait till CQ reaches it's target value and also the ones
that seeks to get timestamp records when the CQ reaches it's target
value.
This causes delay in handling the waiters which gets higher
From: farah kassabri
There is a potential race between user thread seeking to re-use
a timestamp record with new interrupt id, while this record is still
in the middle of interrupt handling and it is about to be freed.
Imagine the driver set the record in_use to 0 and only then fill the
On Mon, Sep 18, 2023 at 3:17 AM Toralf Förster
wrote:
>
> I do suffer since 1 or 2 weeks from amd gpu problems (6.1.53 and before)
> like
>
> Sep 15 16:51:22 p14s kernel: [drm:amdgpu_job_timedout [amdgpu]] *ERROR*
> ring sdma0 timeout, signaled seq=122011, emitted seq=122013
> Sep 15 16:51:22
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