Hi, Xinlei:
On Wed, 2022-09-14 at 21:21 +0800, xinlei@mediatek.com wrote:
> From: Xinlei Lee
>
> Add the compatible because use edge_cfg_in_mmsys in mt8186.
>
> Signed-off-by: Xinlei Lee
> ---
> drivers/gpu/drm/mediatek/mtk_dpi.c | 21 +
>
Hi, Xinlei:
On Wed, 2022-09-14 at 21:21 +0800, xinlei@mediatek.com wrote:
> From: Xinlei Lee
>
> Dpi output needs to adjust the output format to dual edge for MT8186.
> The bridge ic on MT8186 uses the output format of RGB888_dual_edge.
I think different sink ic may support different
Hi, Xinlei:
On Mon, 2022-09-05 at 21:34 +0800, xinlei@mediatek.com wrote:
> From: Xinlei Lee
>
> Dpi output needs to adjust the output format to dual edge for MT8186.
Separate this patch into two patches. One is adding edge_cfg_in_mmsys,
and another one is adding mt8186 dpi support.
I
Hi, Bo-Chen:
On Thu, 2022-09-01 at 12:41 +0800, Bo-Chen Chen wrote:
> It's not necessary to have a next_bridge for DP device, so we add
> this
> patch to judge this.
Reviewed-by: CK Hu
>
> Signed-off-by: Bo-Chen Chen
> ---
> drivers/gpu/drm/mediatek/mtk_dp.c | 5 -
Hi, Nathan:
On Mon, 2022-08-22 at 11:32 +0800, nathan.lu wrote:
> From: Nathan Lu
>
> modify VDOSYS0 device tree Documentations for MT8188.
>
> Signed-off-by: Nathan Lu
> ---
> .../devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml | 1 +
>
Hi, Guillaume:
On Mon, 2021-11-08 at 01:08 +0100, Guillaume Ranquet wrote:
> Signed-off-by: Guillaume Ranquet
> Change-Id: I6399dec26cfe56a338c2ca96989cb7cbd14e292b
> ---
> drivers/gpu/drm/mediatek/Kconfig |9 +
> drivers/gpu/drm/mediatek/Makefile |2 +
>
Hi, Xinlei:
On Thu, 2022-01-27 at 19:42 +0800, xinlei@mediatek.com wrote:
> From: xinlei lee
>
> Add the compatible of mt8186-dsi because we use different cmdq
> addresses in mt8186.
Reviewed-by: CK Hu
>
> Signed-off-by: Xinlei Lee
> ---
> drivers/gpu/dr
Hi, Xinlei:
On Thu, 2022-01-27 at 19:42 +0800, xinlei@mediatek.com wrote:
> From: xinlei lee
>
> Add binding documentation for the MT8186 SoC.
DPI has a yaml format document, so I would like DSI also has a yaml
format document.
Please send a patch to transfer DSI document to yaml, and then
Hi, Xinlei:
On Thu, 2022-01-27 at 19:42 +0800, xinlei@mediatek.com wrote:
> From: xinlei lee
>
> The order of probe function for bridge drivers and dsi drivers is
> uncertain.
> To avoid the dsi probe cannot be executed, we place getting bridge
> node function in
> mtk_dsi_bind.
It seems
Hi, Guillaume:
On Mon, 2021-11-08 at 01:08 +0100, Guillaume Ranquet wrote:
> Signed-off-by: Guillaume Ranquet
> Change-Id: I6399dec26cfe56a338c2ca96989cb7cbd14e292b
> ---
> drivers/gpu/drm/mediatek/Kconfig |9 +
> drivers/gpu/drm/mediatek/Makefile |2 +
>
Hi, Nancy:
On Mon, 2022-01-10 at 16:46 +0800, Nancy.Lin wrote:
> Add driver data of mt8195 vdosys1 to mediatek-drm.
>
> Signed-off-by: Nancy.Lin
> ---
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 18 ++
> 1 file changed, 18 insertions(+)
>
> diff --git
Hi, Yongqiang:
On Thu, 2022-01-20 at 15:43 +0800, Yongqiang Niu wrote:
> From: mtk18742
>
> add cmdq_pkt_poll_addr function in cmdq helper functions
>
> Signed-off-by: Yongqiang Niu
> ---
> drivers/soc/mediatek/mtk-cmdq-helper.c | 39
>
>
Hi, Guillaume:
On Fri, 2021-12-17 at 16:08 +0100, Guillaume Ranquet wrote:
> From: Markus Schneider-Pargmann
>
> dpintf is the displayport interface hardware unit. This unit is
> similar
> to dpi and can reuse most of the code.
>
> This patch adds support for mt8195-dpintf to this dpi driver.
Hi, Guillaume:
On Mon, 2021-11-08 at 01:08 +0100, Guillaume Ranquet wrote:
> Signed-off-by: Guillaume Ranquet
> Change-Id: I6399dec26cfe56a338c2ca96989cb7cbd14e292b
> ---
> drivers/gpu/drm/mediatek/Kconfig |9 +
> drivers/gpu/drm/mediatek/Makefile |2 +
>
Hi, Nancy:
On Mon, 2022-01-10 at 16:46 +0800, Nancy.Lin wrote:
> Add drm ovl_adaptor sub driver. Bring up ovl_adaptor sub driver if
> the component exists in the path.
>
> Signed-off-by: Nancy.Lin
> ---
> drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 16
>
Hi, Angelo:
On Tue, 2022-01-04 at 10:59 +0100, AngeloGioacchino Del Regno wrote:
> DRM bridge drivers are now attaching their DSI device at probe time,
> which requires us to register our DSI host in order to let the bridge
> to probe: this recently started producing an endless -EPROBE_DEFER
>
Hi, Nancy:
On Wed, 2021-12-08 at 10:44 +0800, Nancy.Lin wrote:
> MT8195 have two mmsys. Modify drm for MT8195 multi-mmsys support.
> The two mmsys (vdosys0 and vdosys1) will bring up two drm drivers,
> only one drm driver register as the drm device.
> Each drm driver binds its own component. The
Hi, Nancy:
On Wed, 2021-12-08 at 10:44 +0800, Nancy.Lin wrote:
> Add merge async reset control in mtk_merge_stop. Async hw doesn't do
> self
> reset on each sof signal(start of frame), so need to reset the async
> to
> clear the hw status for the next merge start.
Rev
Hi, Guillaume:
This is a big patch, so I give you some comment first, and I would
continue to review this patch.
On Fri, 2021-12-17 at 16:08 +0100, Guillaume Ranquet wrote:
> From: Markus Schneider-Pargmann
>
> This patch adds a DisplayPort driver for the Mediatek mt8195 SoC.
>
> It supports
Hi, Nancy:
On Wed, 2021-08-18 at 17:18 +0800, Nancy.Lin wrote:
> Add MDP_RDMA driver for MT8195. MDP_RDMA is the DMA engine of
> the ovl_adaptor component.
>
> Signed-off-by: Nancy.Lin
> ---
[snip]
> +
> +#define MDP_RDMA_EN0x000
> +#define
Hi, Jason:
On Thu, 2021-08-19 at 10:23 +0800, jason-jh.lin wrote:
> Add MERGE engine file:
> MERGE module is used to merge two slice-per-line inputs
> into one side-by-side output.
>
> Signed-off-by: jason-jh.lin
> ---
[snip]
> +
> +int mtk_merge_clk_enable(struct device *dev)
> +{
> +
cOHigUMlikjhtJMFrEQqemcjQZa4NaXBE9tzMnAjuBCxsg$
>
>
> -title: mediatek DPI Controller Device Tree Bindings
> +title: mediatek DPI/DP_INTF Controller Device Tree Bindings
>
> maintainers:
>- CK Hu
> @@ -13,7 +13,8 @@ maintainers:
> description: |
>The Medi
Hi, Markus:
On Mon, 2021-08-16 at 21:25 +0200, Markus Schneider-Pargmann wrote:
> This patch adds a DisplayPort driver for the Mediatek mt8195 SoC.
>
> It supports both functional units on the mt8195, the embedded
> DisplayPort as well as the external DisplayPort units. It offers
>
Hi, Markus:
On Mon, 2021-08-16 at 21:25 +0200, Markus Schneider-Pargmann wrote:
> dpintf is the displayport interface hardware unit. This unit is similar
> to dpi and can reuse most of the code.
>
> This patch adds support for mt8195-dpintf to this dpi driver. Main
> differences are:
> - Some
Hi, Markus:
On Mon, 2021-08-16 at 21:25 +0200, Markus Schneider-Pargmann wrote:
> This patch adds a DisplayPort driver for the Mediatek mt8195 SoC.
>
> It supports both functional units on the mt8195, the embedded
> DisplayPort as well as the external DisplayPort units. It offers
>
Hi, Nancy:
On Thu, 2021-07-22 at 17:45 +0800, Nancy.Lin wrote:
> Add driver data of mt8195 vdosys1 to mediatek-drm and modify drm for
> multi-mmsys support. The two mmsys (vdosys0 and vdosys1) will bring
> up two drm drivers, only one drm driver register as the drm device.
> Each drm driver binds
Hi, Jitao:
On Mon, 2021-07-26 at 10:11 +0800, Jitao Shi wrote:
> Some bridge chip will shift screen when the dsi data does't ent at
> the same time in line.
>
> Signed-off-by: Jitao Shi
> ---
> .../devicetree/bindings/display/mediatek/mediatek,dsi.txt | 4
> 1 file changed, 4
Hi, Nancy:
On Thu, 2021-07-22 at 09:32 +0800, Nancy.Lin wrote:
> Hi Chun-Kuang,
>
> On Mon, 2021-07-19 at 07:56 +0800, Chun-Kuang Hu wrote:
> > Hi, Nancy:
> >
> > Nancy.Lin 於 2021年7月17日 週六 下午5:04寫道：
> > >
> > > Add ETHDR module files:
> > > ETHDR is designed for HDR video and graphics
Hi, Nancy:
On Sat, 2021-07-17 at 17:04 +0800, Nancy.Lin wrote:
> Add pseudo ovl module files:
> Pseudo ovl is an encapsulated module and designed for simplified
> DRM control flow. This module is composed of 8 RDMAs and 4 MERGEs.
> Two RDMAs merge into one layer, so this module support 4
>
k_dpi_dual_edge() will fail to write correct
> value to regs.
Reviewed-by: CK Hu
>
> Fixes: ec8747c52434 ("drm/mediatek: dpi: Add bus format negotiation")
> Signed-off-by: Hsin-Yi Wang
> ---
> drivers/gpu/drm/mediatek/mtk_dpi.c | 4
> 1 file changed, 4 insertions
Hi, Frank:
On Mon, 2021-07-12 at 10:07 +0200, Frank Wunderlich wrote:
> From: Frank Wunderlich
>
> bridge->driver_private is not set (NULL) so use bridge_to_dpi(bridge)
> like it's done in bridge_atomic_get_output_bus_fmts
Reviewed-by: CK Hu
>
> Fixes: ec8747c52434 (&q
Hi, Hsin-yi:
On Thu, 2021-04-22 at 19:10 +0800, Hsin-Yi Wang wrote:
> From: CK Hu
>
> In cmdq mode, packet may be flushed before it is executed, so
> the pending flag should be cleared after cmdq packet is done.
>
> Signed-off-by: CK Hu
> Signed-off-by: Hsin-Yi Wang
>
Hi, Yongqiang:
On Mon, 2021-04-12 at 16:45 +0800, Yongqiang Niu wrote:
> On Mon, 2021-04-12 at 16:28 +0800, CK Hu wrote:
> > Hi, Yongqiang:
> >
> > On Mon, 2021-04-12 at 14:35 +0800, Yongqiang Niu wrote:
> > > gamma lut set in vsync active will caused display f
Hi, Yongqiang:
On Mon, 2021-04-12 at 15:25 +0800, Yongqiang Niu wrote:
> the orginal formula will caused rdma fifo threshold config overflow
>
> Signed-off-by: Yongqiang Niu
> ---
> drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git
Hi, Yongqiang:
On Mon, 2021-04-12 at 14:35 +0800, Yongqiang Niu wrote:
> gamma lut set in vsync active will caused display flash issue
> set gamma lut with cmdq
In MT8173, it's ok to set gammma out of vblank period. Why do you
setting gamma in vblank in this patch?
Regards,
CK
>
>
Hi, Yongqiang:
On Mon, 2021-04-12 at 14:35 +0800, Yongqiang Niu wrote:
> mt8183 aal has no gamma function
Separate this patch to two patch: one is add has_gamma config in aal.
another one is add mt8183 aal support.
Regards,
CK
>
> Signed-off-by: Yongqiang Niu
> ---
>
Hi, Jitao:
On Tue, 2021-03-30 at 23:53 +0800, Jitao Shi wrote:
> Add the atomic_get_output_bus_fmts, atomic_get_input_bus_fmts to negociate
> the possible output and input formats for the current mode and monitor,
> and use the negotiated formats in a basic atomic_check callback.
>
>
Hi, Hsin-Yi:
On Tue, 2021-02-02 at 16:12 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> add support for mediatek SOC MT8192
Reviewed-by: CK Hu
>
> Signed-off-by: Yongqiang Niu
> Signed-off-by: Hsin-Yi Wang
> ---
> drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
Hi, Hsin-Yi:
On Tue, 2021-02-02 at 16:12 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> Add matrix_bits and coeffs_precision to ccorr private data:
> - matrix bits of mt8183 is 10
> - matrix bits of mt8192 is 11
>
Reviewed-by: CK Hu
> Signed-off-by: Yongqi
Hi, Hsin-Yi:
On Tue, 2021-02-02 at 16:12 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> This patch add component POSTMASK.
Reviewed-by: CK Hu
>
> Signed-off-by: Yongqiang Niu
> Signed-off-by: Hsin-Yi Wang
> ---
> drivers/gpu/drm/mediatek/
Hi, Hsin-Yi:
On Mon, 2021-02-01 at 18:37 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> Add matrix_bits and coeffs_precision to ccorr private data:
> - matrix bits of mt8183 is 10
> - matrix bits of mt8192 is 11
>
> Signed-off-by: Yongqiang Niu
> Signed-off-by: Hsin-Yi Wang
> ---
>
Hi, Hsin-Yi:
On Mon, 2021-02-01 at 18:37 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> Fix setting to follow hardware datasheet. The original error setting
> affects mt8192 display.
Reviewed-by: CK Hu
>
> Signed-off-by: Yongqiang Niu
> Signed-off-by: Hsin-Yi W
Hi, Hsin-Yi:
On Mon, 2021-02-01 at 18:37 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> ccorr ctm matrix bits will be different in mt8192
Reviewed-by: CK Hu
>
> Signed-off-by: Yongqiang Niu
> Signed-off-by: Hsin-Yi Wang
> ---
> drivers/gpu/drm/mediatek/
Hi, Hsin-Yi:
It looks like that postmask driver could be placed in mtk_drm_ddp_comp.c
and this patch would much smaller.
Regards,
CK
On Mon, 2021-02-01 at 18:37 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> This patch add component POSTMASK.
>
> Signed-off-by: Yongqiang Niu
>
Hi, Hsin-Yi:
On Fri, 2021-01-29 at 15:34 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> Add mtk mutex support for MT8192 SoC.
Reviewed-by: CK Hu
>
> Signed-off-by: Yongqiang Niu
> Signed-off-by: Hsin-Yi Wang
> ---
> drivers/soc/m
Hi, Hsin-Yi:
On Fri, 2021-01-29 at 15:34 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> matrix bits of mt8183 is 12
> matrix bits of mt8192 is 13
>
> Signed-off-by: Yongqiang Niu
> Signed-off-by: Hsin-Yi Wang
> ---
> drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 22
On Fri, 2021-01-29 at 16:32 +0800, Yongqiang Niu wrote:
> On Fri, 2021-01-29 at 16:18 +0800, CK Hu wrote:
> > Hi, Hsin-Yi:
> >
> > On Fri, 2021-01-29 at 15:34 +0800, Hsin-Yi Wang wrote:
> > > From: Yongqiang Niu
> > >
> > > This patch
Hi, Hsin-Yi:
On Fri, 2021-01-29 at 15:34 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> enable OVL_LAYER_SMI_ID_EN for multi-layer usecase, without this patch,
> ovl will hang up when more than 1 layer enabled.
Reviewed-by: CK Hu
>
> Signed-off-by: Yongqiang Niu
>
Hi, Hsin-Yi:
On Fri, 2021-01-29 at 15:34 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> This patch add component POSTMASK,
>
> Signed-off-by: Yongqiang Niu
> Signed-off-by: Hsin-Yi Wang
> ---
> drivers/gpu/drm/mediatek/Makefile| 1 +
>
Hi, Hsin-Yi:
On Thu, 2021-01-28 at 19:23 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> for 5 or 6 bpc panel, we need enable dither function
> to improve the display quality
>
> Signed-off-by: Yongqiang Niu
> Signed-off-by: Hsin-Yi Wang
> ---
>
Hi, Hsin-Yi:
On Thu, 2021-01-28 at 19:23 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> Add mtk mutex support for MT8183 SoC.
Reviewed-by: CK Hu
>
> Signed-off-by: Yongqiang Niu
> Signed-off-by: Hsin-Yi Wang
> ---
> drivers/soc/m
On Thu, 2021-01-28 at 16:18 +0800, Hsin-Yi Wang wrote:
> On Thu, Jan 28, 2021 at 4:10 PM Yongqiang Niu
> wrote:
> >
> > On Thu, 2021-01-28 at 16:07 +0800, CK Hu wrote:
> > > On Thu, 2021-01-28 at 15:59 +0800, Yongqiang Niu wrote:
> > > > On Thu,
On Thu, 2021-01-28 at 15:59 +0800, Yongqiang Niu wrote:
> On Thu, 2021-01-28 at 15:42 +0800, CK Hu wrote:
> > Hi, Hsin-Yi:
> >
> > On Thu, 2021-01-28 at 15:28 +0800, Hsin-Yi Wang wrote:
> > > From: Yongqiang Niu
> > >
> > > for 5 or 6 bpc panel,
Hi, Hsin-Yi:
On Thu, 2021-01-28 at 15:27 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> This patch add RDMA fifo size error handle
> rdma fifo size will not always bigger than the calculated threshold
> if that case happened, we need set fifo size as the threshold
>
> Signed-off-by:
Hi, Hsin-Yi:
On Thu, 2021-01-28 at 15:28 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> Add mtk mutex support for MT8183 SoC.
>
> Signed-off-by: Yongqiang Niu
> Signed-off-by: Hsin-Yi Wang
> ---
> drivers/soc/mediatek/mtk-mutex.c | 50
> 1 file
Hi, Hsin-Yi:
On Thu, 2021-01-28 at 15:28 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> for 5 or 6 bpc panel, we need enable dither function
> to improve the display quality
>
> Signed-off-by: Yongqiang Niu
> Signed-off-by: Hsin-Yi Wang
> ---
>
ponents (dither,
> gamma) can call this function.
Reviewed-by: CK Hu
>
> Signed-off-by: Hsin-Yi Wang
> ---
> drivers/gpu/drm/mediatek/mtk_disp_drv.h | 4
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 25 +
> 2 files changed, 20 insertions(+), 9 de
On Thu, 2021-01-28 at 14:15 +0800, Hsin-Yi Wang wrote:
> On Thu, Jan 28, 2021 at 2:13 PM CK Hu wrote:
> >
> > Hi, Hsin-Yi:
> >
> > Modify the title's prefix to 'soc: mediatek:'
> >
> > On Wed, 2021-01-27 at 12:54 +0800, Hsin-Yi Wang wrote:
> > >
On Thu, 2021-01-28 at 14:13 +0800, CK Hu wrote:
> Hi, Hsin-Yi:
>
> Modify the title's prefix to 'soc: mediatek:'
Modify more, the title should be 'soc: mediatek: add mtk mutex support
for MT8183'
>
> On Wed, 2021-01-27 at 12:54 +0800, Hsin-Yi Wang wrote:
> > From: Yongqi
Hi, Hsin-Yi:
On Wed, 2021-01-27 at 12:54 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> 1. add ovl private data
> 2. add rdma private data
> 3. add gamma privte data
> 4. add main and external path module for crtc create
Reviewed-by: CK Hu
>
> Signed-off-by:
Hi, Hsin-Yi:
Modify the title's prefix to 'soc: mediatek:'
On Wed, 2021-01-27 at 12:54 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> Add DDP support for MT8183 SoC.
>
> Signed-off-by: Yongqiang Niu
> Signed-off-by: Hsin-Yi Wang
> ---
> drivers/soc/mediatek/mtk-mutex.c | 50
Hi, Hsin-Yi:
On Wed, 2021-01-27 at 12:54 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> for 5 or 6 bpc panel, we need enable dither function
> to improve the display quality
>
> Signed-off-by: Yongqiang Niu
> Signed-off-by: Hsin-Yi Wang
> ---
>
Hi, Hsin-Yi:
On Wed, 2021-01-27 at 12:54 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> Not all SoC has dither function in gamma module.
> Add private data to control this function setting.
Reviewed-by: CK Hu
>
> Signed-off-by: Yongqiang Niu
> Signed
Hi, Hsin-Yi:
On Wed, 2021-01-27 at 12:54 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> mt8183 gamma module will different with mt8173
> separate gamma for add private data
Reviewed-by: CK Hu
>
> Signed-off-by: Yongqiang Niu
> Signed-off-by: Hsin-Yi Wang
>
On Thu, 2021-01-28 at 13:09 +0800, Hsin-Yi Wang wrote:
> On Thu, Jan 28, 2021 at 12:39 PM CK Hu wrote:
> >
> > Hi, Hsin-Yi:
> >
> > On Wed, 2021-01-27 at 12:54 +0800, Hsin-Yi Wang wrote:
> > > There may be data structure other than mtk_ddp_comp_dev that would
Hi, Hsin-Yi:
On Wed, 2021-01-27 at 12:54 +0800, Hsin-Yi Wang wrote:
> There may be data structure other than mtk_ddp_comp_dev that would call
> mtk_dither_set(), so use regs as parameter instead of device.
You does not change the interface of mtk_dither_set(). You move the
common part in
Hi, Hsin-Yi:
On Wed, 2021-01-27 at 12:54 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> This patch add RDMA fifo size error handle
> rdma fifo size will not always bigger than the calculated threshold
> if that case happened, we need set fifo size as the threshold
>
> Signed-off-by:
+ Chun-Kuang, Philipp:
This mail has been sent to dri devel and linux mediatek, but why it does
not exist in mail lists?
Regards,
CK
On Thu, 2020-12-24 at 17:54 +0800, Huijuan Xie wrote:
> The interrupt trigger is already set by OF. When do devm_request_irq()
> in driver, please use
@@ -0,0 +1,90 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +# Copyright (c) 2020 MediaTek
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/mediatek,hdmi-phy.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: MediaT
Hi, Matthias:
On Thu, 2020-03-26 at 16:45 +0100, Matthias Brugger wrote:
>
> On 26/03/2020 15:51, CK Hu wrote:
> > Hi, Matthias:
> >
> > On Thu, 2020-03-26 at 12:54 +0100, Matthias Brugger wrote:
> >> Hi CK,
> >>
> >> On 26/03/2020 00:05,
Hi, Yongqiang:
In [1], Matthias has applied below series to fix mmsys driver probe
problem. Please base on that series to resend your patches.
soc / drm: mediatek: Fix mediatek-drm device probingsoc / drm:
mediatek: Move routing control to mmsys device clk / soc: mediatek: Move
mt8173 MMSYS
Hi, Matthias:
On Thu, 2020-03-26 at 12:54 +0100, Matthias Brugger wrote:
> Hi CK,
>
> On 26/03/2020 00:05, CK Hu wrote:
> > Hi, Matthias:
> >
> > On Wed, 2020-03-25 at 17:16 +0100, Matthias Brugger wrote:
> >>
> >> On 11/03/2020 17:53
_path().
> > Those functions will allow DRM driver and others to control the data
> > path routing.
> >
> > Signed-off-by: Enric Balletbo i Serra
> > Reviewed-by: Matthias Brugger
> > Reviewed-by: CK Hu
> > Acked-by: CK Hu
>
> This patch does not ap
Hi, Enric:
On Wed, 2020-02-26 at 12:27 +0100, Enric Balletbo i Serra wrote:
> Equivalent information can be nowadays obtained using function tracer.
>
> Signed-off-by: Enric Balletbo i Serra
> ---
Acked-by: CK Hu
>
> drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 5 -
Hi, Enric:
On Wed, 2020-02-26 at 12:27 +0100, Enric Balletbo i Serra wrote:
> Equivalent information can be nowadays obtained using function tracer.
>
Acked-by: CK Hu
> Signed-off-by: Enric Balletbo i Serra
> ---
>
> drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 5 -
Hi, Dave & Daniel:
This include MT8183 DPI support.
And I change my email address to "Chun-Kuang Hu
", so I would use it afterward.
Regards,
CK
The following changes since commit
bb6d3fb354c5ee8d6bde2d576eb7220ea09862b9:
Linux 5.6-rc1 (2020-02-09 16:08:48 -0800)
are available in the Git
d
> > by that MMSYS driver.
> >
> > Signed-off-by: Enric Balletbo i Serra
> > Reviewed-by: CK Hu
>
> Same here.
Acked-by: CK Hu
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On Wed, 2020-03-11 at 14:25 +0100, Matthias Brugger wrote:
>
> On 11/03/2020 14:07, CK Hu wrote:
> > Hi, Enric:
> >
> > On Wed, 2020-03-11 at 12:56 +0100, Enric Balletbo i Serra wrote:
> >> Provide a mtk_mmsys_ddp_connect() and mtk_mmsys_disco
the data
> path routing.
>
Reviewed-by: CK Hu
> Signed-off-by: Enric Balletbo i Serra
> Reviewed-by: Matthias Brugger
> ---
>
> Changes in v11: None
> Changes in v10:
> - Select CONFIG_MTK_MMSYS (CK)
> - Pass device pointer of mmsys device instead of config regs
he mediatek-drm and the mediatek-mdp
> driver. So move the MMSYS clocks to a new platform driver and also
> create a new MMSYS platform driver in drivers/soc/mediatek that
> instantiates the clock driver.
>
Reviewed-by: CK Hu
> Signed-off-by: Matthias Brugger
> Signed-off-by: Enric Bal
Hi, Enric:
I'm confused this is v11 or v12.
For v12, you've lost some 'Acked-by' and 'Reviewed-by' tag.
Regards,
CK
On Wed, 2020-03-11 at 12:56 +0100, Enric Balletbo i Serra wrote:
> Dear all,
>
> These patches are intended to solve an old standing issue on some
> Mediatek devices (mt8173,
Hi, Thomas:
On Thu, 2020-03-05 at 16:59 +0100, Thomas Zimmermann wrote:
> The mediatak driver uses empty implementations for its encoders. Replace
> the code with the generic simple encoder.
>
Acked-by: CK Hu
> Signed-off-by: Thomas Zimmermann
> ---
> drivers/gpu/drm/media
Hi, Dennis:
On Sun, 2020-03-08 at 18:52 +0800, Dennis YC Hsieh wrote:
> Add clear parameter to let client decide if
> event should be clear to 0 after GCE receive it.
>
Reviewed-by: CK Hu
> Signed-off-by: Dennis YC Hsieh
> ---
> drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 2
Hi, Dennis:
On Sun, 2020-03-08 at 18:52 +0800, Dennis YC Hsieh wrote:
> Add jump function so that client can jump to any address which
> contains instruction.
>
Reviewed-by: CK Hu
> Signed-off-by: Dennis YC Hsieh
> ---
> drivers/soc/mediatek/mtk-cmdq-helper.c | 13 ++
freedesktop.org/drm/drm-misc
>
> DRM DRIVERS FOR MEDIATEK
> -M: CK Hu
> +M: Chun-Kuang Hu
> M: Philipp Zabel
> L: dri-devel@lists.freedesktop.org
> S: Supported
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Hi, Dave & Daniel:
This include OVL, cursor, and gce fixup.
Regards,
CK
The following changes since commit
bb6d3fb354c5ee8d6bde2d576eb7220ea09862b9:
Linux 5.6-rc1 (2020-02-09 16:08:48 -0800)
are available in the Git repository at:
https://github.com/ckhu-mediatek/linux.git-tags.git
Hi, Dennis:
On Tue, 2020-03-03 at 18:58 +0800, Dennis YC Hsieh wrote:
> Add clear parameter to let client decide if
> event should be clear to 0 after GCE receive it.
>
> Signed-off-by: Dennis YC Hsieh
> ---
> drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 2 +-
>
Hi, Dennis:
On Wed, 2020-03-04 at 10:32 +0800, CK Hu wrote:
> Hi, Dennis:
>
> On Tue, 2020-03-03 at 18:58 +0800, Dennis YC Hsieh wrote:
> > Some gce hardware shift pc and end address in register to support
> > large dram addressing.
> > Implement gce address shift wh
Hi, Dennis:
On Tue, 2020-03-03 at 18:58 +0800, Dennis YC Hsieh wrote:
> Add jump function so that client can jump to any address which
> contains instruction.
>
> Signed-off-by: Dennis YC Hsieh
> ---
> drivers/soc/mediatek/mtk-cmdq-helper.c | 12
>
Hi, Dennis:
On Tue, 2020-03-03 at 18:58 +0800, Dennis YC Hsieh wrote:
> Export finalize function to client which helps append eoc and jump
> command to pkt. Let client decide call finalize or not.
>
Reviewed-by: CK Hu
> Signed-off-by: Dennis YC Hsieh
> ---
> driver
Hi, Dennis:
On Tue, 2020-03-03 at 18:58 +0800, Dennis YC Hsieh wrote:
> Return error code to client if send message fail,
> so that client has chance to error handling.
>
Reviewed-by: CK Hu
> Signed-off-by: Dennis YC Hsieh
> Fixes: 576f1b4bc802 ("soc: mediatek: Add
Hi, Dennis:
On Tue, 2020-03-03 at 18:58 +0800, Dennis YC Hsieh wrote:
> Do success callback in channel when shutdown. For those task not finish,
> callback with error code thus client has chance to cleanup or reset.
>
Reviewed-by: CK Hu
> Signed-off-by: Dennis YC Hsieh
>
Hi, Dennis:
On Tue, 2020-03-03 at 18:58 +0800, Dennis YC Hsieh wrote:
> Some gce hardware shift pc and end address in register to support
> large dram addressing.
> Implement gce address shift when write or read pc and end register.
> And add shift bit in platform definition.
>
> Signed-off-by:
Hi, Matthias:
On Thu, 2020-02-27 at 19:22 +0100, Matthias Brugger wrote:
>
> On 27/02/2020 19:21, Matthias Brugger wrote:
> >
> >
> > On 27/02/2020 19:08, Enric Balletbo i Serra wrote:
> >> From: Matthias Brugger
> >>
> >> There is no strong reason for this to use CLK_OF_DECLARE instead of
>
the data
> path routing.
>
Reviewed-by: CK Hu
But what is the base of this series? When I apply this patch to 5.6-rc1,
some error happen, the apply --reject result is
In drivers/gpu/drm/mediatek/mtk_drm_crtc.c.rej
diff a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
b/drivers/gpu/drm/mediatek
y, we can consider that the mmsys driver is the top-level
> entry point for the multimedia subsystem, so is not a pure clock
> controller but a system controller, and the drm driver is instantiated
> by that MMSYS driver.
Reviewed-by: CK Hu
>
> Signed-off-by: Enric Balletbo i Serra
Hi, Enric:
On Thu, 2020-02-27 at 19:08 +0100, Enric Balletbo i Serra wrote:
> Provide a mtk_mmsys_ddp_connect() and mtk_mmsys_disconnect() functions to
> replace mtk_ddp_add_comp_to_path() and mtk_ddp_remove_comp_from_path().
> Those functions will allow DRM driver and others to control the data
he mediatek-drm and the mediatek-mdp
> driver. So move to drivers/soc/mediatek as a platform driver.
>
Reviewed-by: CK Hu
> Signed-off-by: Matthias Brugger
> Signed-off-by: Enric Balletbo i Serra
> ---
>
> Changes in v10:
> - Renamed to be generic mtk-mmsys
> - Add
registers.
>
Reviewed-by: CK Hu
> Signed-off-by: Enric Balletbo i Serra
> ---
>
> Changes in v10:
> - Update the binding documentation for the mmsys system controller.
>
> Changes in v9: None
> Changes in v8: None
> Changes in v7: None
>
> .../devicetree/bi
Hi, Enric:
On Thu, 2020-02-27 at 09:45 +0100, Enric Balletbo i Serra wrote:
> Hi CK,
>
> On 27/2/20 2:10, CK Hu wrote:
> > Hi, Enric:
> >
> > On Wed, 2020-02-26 at 11:54 +0100, Enric Balletbo i Serra wrote:
> >> From: Matthias Brugger
> >>
> >
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