t; ovl0_2l read layer4~5
> layer5 is at the top ot all these layers.
>
> the decision of how to setting ovl0/ovl0_2l read these layer data
> is controlled in mtk crtc, which will be another patch
>
Reviewed-by: CK Hu
> Signed-off-by: Yongqiang Niu
> ---
> drivers/gpu/
t select for these hardware.
> this is preparation patch for ovl/ovl_2l usecase
>
Reviewed-by: CK Hu
> Signed-off-by: Yongqiang Niu
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 14 ++
> 1 file changed, 14 insertions(+)
>
> diff --git a/drivers/gpu/drm/me
Hi, Yongqiang:
On Tue, 2019-07-09 at 06:33 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> This patch add mmsys private data for ddp path config
> all these register offset and value will be different in future SOC
> add these define into mmsys private data
> u32 ovl0_mo
Hi, Yongqiang:
On Tue, 2019-07-09 at 06:33 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> Here is two modifition in this patch:
> 1.bls->dpi0 and rdma1->dsi are differen usecase,
> Split DISP_REG_CONFIG_DSI_SEL setting into anther usecase
> 2.remove DISP_REG_CONFIG_DPI_SEL se
Hi, Yongqiang:
On Tue, 2019-07-09 at 06:33 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> mutex sof register offset will be private data of ddp
>
Reviewed-by: CK Hu
> Signed-off-by: Yongqiang Niu
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp.c |
Hi, Yongqiang:
On Tue, 2019-07-09 at 06:33 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> mutex sof will be ddp private data
>
Reviewed-by: CK Hu
> Signed-off-by: Yongqiang Niu
> ---
> drivers/gpu/drm/mediat
Hi, Yongqiang:
On Tue, 2019-07-09 at 06:33 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> mutex mod register offset will be private data of ddp.
>
Reviewed-by: CK Hu
> Signed-off-by: Yongqiang Niu
> ---
> drivers/gpu/drm/mediat
Hi, Yongqiang:
On Tue, 2019-07-09 at 06:33 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> except mutex mod, mutex mod reg,mutex sof reg,
> and mutex sof id will be ddp private data
Reviewed-by: CK Hu
>
> Signed-off-by: Yongqiang Niu
> ---
>
Hi, Yongqiang:
This version is identical to previous version, and Rob has gave a
'Reviwed-by' tag on previous version, so you should keep that tag on
this version, so we don't need to review this patch again.
Regards,
CK
On Tue, 2019-07-09 at 06:33 +0800, yongqiang@mediatek.com wrote:
> Fr
Hi, Yongqiang:
This version is identical to previous version, and Rob has gave a
'Reviwed-by' tag on previous version, so you should keep that tag on
this version, so we don't need to review this patch again.
Regards,
CK
On Tue, 2019-07-09 at 06:33 +0800, yongqiang@mediatek.com wrote:
> Fr
Hi, Yongqiang:
On Tue, 2019-07-09 at 06:33 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> Update device tree binding documention for the display subsystem for
> Mediatek MT8183 SOCs
>
> Signed-off-by: Yongqiang Niu
> ---
> .../bindings/display/mediatek/mediatek,display.txt
ude ""
>
> And sort the includes in the blocks
> Add the necessary includes to fix build after removal of drmP.h
Reviewed-by: CK Hu
Thanks.
>
> Signed-off-by: Sam Ravnborg
> Acked-by: Emil Velikov
> Cc: CK Hu
> Cc: Philipp Zabel
> Cc: David
Hi, Derek:
On Tue, 2019-07-09 at 19:16 -0700, Derek Basehore wrote:
> This inits the panel orientation property for the mediatek dsi driver
> if the panel orientation (connector.display_info.panel_orientation) is
> not DRM_MODE_PANEL_ORIENTATION_UNKNOWN.
>
Reviewed-by: CK Hu
>
Hi, Uli:
On Thu, 2019-07-04 at 17:33 +0200, Ulrich Hecht wrote:
> > On July 4, 2019 at 11:08 AM Matthias Brugger wrote:
> > You are right, it took far too long for me to respond with a new version of
> > the
> > series. The problem I face is, that I use my mt8173 based chromebook for
> > testing
Hi, Matthias:
On Fri, 2018-11-30 at 16:59 +0800, Matthias Brugger wrote:
>
> On 30/11/2018 07:43, Stephen Boyd wrote:
> > Quoting Matthias Brugger (2018-11-21 09:09:52)
> >>
> >>
> >> On 21/11/2018 17:46, Stephen Boyd wrote:
> >>> Quoting Rob Herring (2018-11-19 11:15:16)
> On Sun, Nov 18, 2
Hi, Derek:
On Fri, 2019-06-21 at 20:41 -0700, Derek Basehore wrote:
> This inits the panel orientation property for the mediatek dsi driver
> if the panel orientation (connector.display_info.panel_orientation) is
> not DRM_MODE_PANEL_ORIENTATION_UNKNOWN.
>
Reviewed-by: CK Hu
>
pixel
>
> Signed-off-by: Jitao Shi
> Tested-by: Ryan Case
> Reviewed-by: CK Hu
This version is different than previous version, so you should remove
Reviewed-by tag. For this version, I still give you a
Reviewed-by: CK Hu
> ---
> drivers/gpu/drm/mediatek/mtk_dsi.c | 117 +++
Hi, Jitao:
On Thu, 2019-06-27 at 16:01 +0800, Jitao Shi wrote:
> Our new DSI chip has frame size control.
> So add the driver data to control for different chips.
>
> Signed-off-by: Jitao Shi
> Reviewed-by: CK Hu
This version is different than previous version, so you sh
Hi, Jitao:
On Thu, 2019-06-27 at 10:58 +0800, Jitao Shi wrote:
> Update device tree binding documentation for the dsi for
> Mediatek MT8183 SoCs.
>
> Signed-off-by: Jitao Shi
> Acked-by: Rob Herring
This version is different than previous version, so I think you should
remove the Acked-by tag.
er to probe from bind.
>
> Signed-off-by: Jitao Shi
> Reviewed-by: CK Hu
This version is different than v4, so please remove reviewed-by tag when
this patch change. When I see a reviewed-by tag of mine, I would just
skip review it again because I assume this patch is the same as previous
version.
Hi, Jitao:
On Thu, 2019-06-27 at 16:01 +0800, Jitao Shi wrote:
> Config the different CMDQ reg address in driver data.
>
> Signed-off-by: Jitao Shi
> ---
> drivers/gpu/drm/mediatek/mtk_dsi.c | 29 -
> 1 file changed, 24 insertions(+), 5 deletions(-)
>
> diff --git a
Hi, Jitao:
On Thu, 2019-06-27 at 10:59 +0800, Jitao Shi wrote:
> Different IC has different mipi_tx setting of dsi.
> This patch separates the mipi_tx hardware relate part for mt8173.
>
> Signed-off-by: Jitao Shi
> Reviewed-by: CK Hu
> ---
> drivers/gpu/drm/mediatek/Makef
Hi, Jitao:
On Thu, 2019-06-27 at 10:59 +0800, Jitao Shi wrote:
> This patch add mt8183 mipi_tx driver.
> And also support other chips that use the same binding and driver.
>
> Signed-off-by: Jitao Shi
> ---
> drivers/gpu/drm/mediatek/Makefile | 1 +
> drivers/gpu/drm/mediatek/mtk_
Note that this relies on mtk setting drm_fb->obj, which is already
> done in mtk_drm_framebuffer_init().
Reviewed-by: CK Hu
>
> Aside: Probably can use the default commit_tail with this again, but I
> didn't check for that.
>
> Signed-off-by: Daniel Vetter
> Cc: CK Hu
Hi, Yongqiang:
On Wed, 2019-06-05 at 19:43 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> This patch add support for mediatek SOC MT8183
> 1.ovl_2l share driver with ovl
> 2.rdma1 share drive with rdma0, but fifo size is different
> 3.add mt8183 mutex private data, and mmsys
Hi, Yongqiang:
On Wed, 2019-06-05 at 19:43 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> This patch add clock property check before get it
In the binding document [1], clock is required property. In this patch,
you change it to optional property. I think you should change t
Hi, Yongqiang:
On Wed, 2019-06-05 at 19:42 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> This patch add function to background color input select for ovl/ovl_2l
> direct link
> for ovl/ovl_2l direct link usecase, we need set background color
> input select for these hardwar
Hi, Daniel:
On Fri, 2019-06-14 at 22:35 +0200, Daniel Vetter wrote:
> They're the default.
>
> Aside: Would be really nice to switch the others over to
> drm_gem_object_funcs.
Reviewed-by: CK Hu
>
> Signed-off-by: Daniel Vetter
> Cc: CK Hu
> Cc: Philipp Zabel
Hi, Yongqiang:
On Wed, 2019-06-05 at 19:42 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> This patch add background color input select function for ovl/ovl_2l
>
> ovl include 4 DRAM layer and 1 background color layer
> ovl_2l include 4 DRAM layer and 1 background color layer
reparation for ovl-2l and
> ovl share the same driver.
This patch is identical to v2, and I've give a 'Reviewed-by' for v2,
so you should keep this 'Reviewed-by' tag in this patch, so I still give
you a
Reviewed-by: CK Hu
>
> Signed-off-by: Yongqiang Niu
hd_l not
> used.
This patch is identical to v2, and I've give a 'Reviewed-by' for v2,
so you should keep this 'Reviewed-by' tag in this patch, so I still give
you a
Reviewed-by: CK Hu
>
> Signed-off-by: Yongqiang Niu
> ---
> drivers/gpu/drm/mediate
Hi, Yongqiang:
On Wed, 2019-06-05 at 19:42 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> This patch add component DITHER
Reviewed-by: CK Hu
>
> Signed-off-by: Yongqiang Niu
> ---
> drivers/gpu/drm/mediatek/mt
Hi, Yongqiang:
On Wed, 2019-06-05 at 19:42 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> This patch add component OVL_2L1
Reviewed-by: CK Hu
>
> Signed-off-by: Yongqiang Niu
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 1 +
>
Hi, Yongqiang:
On Wed, 2019-06-05 at 19:42 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> This patch add commponent OVL_2L0
Reviewed-by: CK Hu
>
> Signed-off-by: Yongqiang Niu
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 ++
>
in this patch, so I still give
you a
Reviewed-by: CK Hu
[1] https://patchwork.kernel.org/patch/10872697/
>
> Signed-off-by: Yongqiang Niu
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 32
> +
> drivers/gpu/drm/mediatek/mtk_drm_
Hi, Yongqiang:
On Wed, 2019-06-05 at 19:42 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> This patch add mmsys private data for ddp path config
> all these register offset and value will be different in future SOC
> add these define into mmsys private data
> u32 ovl0_mo
+Bibby:
Hi, Yongqiang:
On Wed, 2019-06-05 at 19:42 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> Here is two modifition in this patch:
> 1.bls->dpi0 and rdma1->dsi are differen usecase,
> Split DISP_REG_CONFIG_DSI_SEL setting into anther usecase
> 2.remove DISP_REG_CONFIG_D
On Thu, 2019-06-13 at 10:27 +0200, Daniel Vetter wrote:
> On Thu, Jun 13, 2019 at 02:31:18PM +0800, CK Hu wrote:
> > Hi, Daniel:
> >
> > On Wed, 2019-06-12 at 18:25 +0200, Daniel Vetter wrote:
> > > On Wed, Jun 12, 2019 at 03:51:08PM +0800, CK Hu
Hi, Yongqiang:
On Wed, 2019-06-05 at 19:42 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> mutex sof register offset will be private data of ddp
>
> Signed-off-by: Yongqiang Niu
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 13 ++---
> 1 file changed, 10 insertio
Hi, Daniel:
On Wed, 2019-06-12 at 18:25 +0200, Daniel Vetter wrote:
> On Wed, Jun 12, 2019 at 03:51:08PM +0800, CK Hu wrote:
> > Hi Dave, Daniel:
> >
> > This include unbind error fix, clock control flow refinement, and PRIME
> > mmap with page offset.
> >
Hi Dave, Daniel:
This include unbind error fix, clock control flow refinement, and PRIME
mmap with page offset.
Regards,
CK
The following changes since commit
a188339ca5a396acc588e5851ed7e19f66b0ebd9:
Linux 5.2-rc1 (2019-05-19 15:47:09 -0700)
are available in the Git repository at:
https:
Hi, Jitao:
On Sat, 2019-06-01 at 17:26 +0800, Jitao Shi wrote:
> Add mt8183 dsi driver data. Enable size control and
> reg commit control.
>
> Signed-off-by: Jitao Shi
> Reviewed-by: CK Hu
> ---
> drivers/gpu/drm/mediatek/mtk_dsi.c | 8
> 1 file changed, 8
Hi, Derek:
On Mon, 2019-06-10 at 17:22 -0700, Derek Basehore wrote:
> This inits the panel orientation property for the mediatek dsi driver
> if the panel orientation (connector.display_info.panel_orientation) is
> not DRM_MODE_PANEL_ORIENTATION_UNKNOWN.
>
Looks good to me,
Ack
Hi, Yongqiang:
On Wed, 2019-06-05 at 19:42 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> mutex sof will be ddp private data
>
> Signed-off-by: Yongqiang Niu
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 44
> +++---
> 1 file changed, 36 ins
Hi, Yongqiang:
On Wed, 2019-06-05 at 19:42 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> except mutex mod, mutex mod reg,mutex sof reg,
> and mutex sof id will be ddp private data
>
> Signed-off-by: Yongqiang Niu
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 53
>
Hi, Yongqiang:
On Wed, 2019-06-05 at 19:42 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> Update device tree binding documention for the display subsystem for
> Mediatek MT8183 SOCs
>
> Signed-off-by: Yongqiang Niu
> ---
> .../bindings/display/mediatek/mediatek,disp.txt
Hi, Hsin-Yi:
On Thu, 2019-05-30 at 17:18 +0800, Hsin-Yi Wang wrote:
> mtk_dsi_stop() should be called after mtk_drm_crtc_atomic_disable(), which
> needs
> ovl irq for drm_crtc_wait_one_vblank(), since after mtk_dsi_stop() is called,
> ovl irq will be disabled. If drm_crtc_wait_one_vblank() is cal
Hi, Hsin-Yi:
On Wed, 2019-05-29 at 18:25 +0800, Hsin-Yi Wang wrote:
> There are some errors when unbinding and rebinding mediatek drm, dsi,
> and disp-* drivers. This series is to fix those errors and warnings.
>
> Hsin-Yi Wang (4):
> drm: mediatek: fix unbind functions
> drm: mediatek: unbin
Hi, Jitao:
On Sat, 2019-06-01 at 17:52 +0800, Jitao Shi wrote:
> This patch add mt8183 mipi_tx driver.
> And also support other chips that use the same binding and driver.
>
> Signed-off-by: Jitao Shi
> ---
> drivers/gpu/drm/mediatek/Makefile | 1 +
> drivers/gpu/drm/mediatek/mtk_
gt;regs + DSI_PHY_TIMECON1);
> @@ -418,7 +451,8 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
> u32 horizontal_sync_active_byte;
> u32 horizontal_backporch_byte;
> u32 horizontal_frontporch_byte;
> - u32 dsi_tmp_buf_bpp;
> + u32 dsi_tmp_
lt on. But this driver doesn't use this
> function. So add the disable control.
Reviewed-by: CK Hu
>
> Signed-off-by: Jitao Shi
> ---
> drivers/gpu/drm/mediatek/mtk_dsi.c | 10 ++
> 1 file changed, 10 insertions(+)
>
> diff --git a/drivers/gpu/drm/medi
Hi, Jitao:
On Sat, 2019-06-01 at 17:26 +0800, Jitao Shi wrote:
> Config the different CMDQ reg address in driver data.
>
> Signed-off-by: Jitao Shi
> ---
> drivers/gpu/drm/mediatek/mtk_dsi.c | 29 -
> 1 file changed, 24 insertions(+), 5 deletions(-)
>
> diff --git a
;host);
> -err_ddp_comp_unregister:
> mtk_ddp_comp_unregister(drm, &dsi->ddp_comp);
> return ret;
> }
> @@ -1097,31 +1089,37 @@ static int mtk_dsi_probe(struct platform_device *pdev)
>
> dsi->host.ops = &mtk_dsi_ops;
> dsi->h
Hi, Jitao:
On Sun, 2019-05-19 at 17:25 +0800, Jitao Shi wrote:
> mtk_mipi_tx is the phy of mtk_dsi.
> mtk_dsi get the phy(mtk_mipi_tx) in probe().
>
> So, mtk_mipi_tx init should be ahead of mtk_dsi. Or mtk_dsi will
> defer to wait mtk_mipi_tx probe done.
Reviewed-by: CK Hu
Hi, Jitao:
On Sun, 2019-05-19 at 17:25 +0800, Jitao Shi wrote:
> New DSI IP has shadow register and working reg. The register
> values are writen to shadow register. And then trigger with
> commit reg, the register values will be moved working register.
>
> This fucntion is defualt on. But this d
Hi, Jitao:
On Sun, 2019-05-19 at 19:15 +0800, Jitao Shi wrote:
> Reset dsi HW to default when power on. Prevent the setting differet
> between bootloader and kernel.
>
> Signed-off-by: Jitao Shi
> ---
> drivers/gpu/drm/mediatek/mtk_dsi.c | 35 ++
> 1 file changed, 35
gt; ...
>--> mtk_dsi_ddp_stop()
> --> mtk_dsi_poweroff();
>
> mtk_dsi_poweroff() has reference count design, change to make mtk_dsi_stop()
> called in mtk_dsi_poweroff() when refcount is 0.
Reviewed-by: CK Hu
>
> Fixes: 0707632b5bac ("drm/mediatek: update
Hi, Hsin-Yi:
On Thu, 2019-05-30 at 10:55 +0800, Hsin-Yi Wang wrote:
> On Tue, May 28, 2019 at 4:53 PM CK Hu wrote:
>
> > I think we've already discussed in [1]. I need a reason to understand
> > this is hardware behavior or software bug. If this is a software bug, we
>
> 10 mutex id. Clear this number so it starts from 0 in every rebind.
Reviewed-by: CK Hu
>
> Fixes: 119f5173628a ("drm/mediatek: Add DRM Driver for Mediatek SoC MT8173.")
> Signed-off-by: Hsin-Yi Wang
> ---
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 1 +
> 1 file chan
Hi, Hsin-Yi:
On Wed, 2019-05-29 at 18:25 +0800, Hsin-Yi Wang wrote:
> shutdown all CRTC when unbinding drm driver.
>
Reviewed-by: CK Hu
> Fixes: 119f5173628a ("drm/mediatek: Add DRM Driver for Mediatek SoC MT8173.")
> Signed-off-by: Hsin-Yi Wang
> ---
&g
tk_drm_kms_init() is called, and the components are added back.
>
> .unbind() should call mtk_drm_kms_deinit() to unbind components.
>
> And since component_master_del() in .remove() will trigger .unbind(),
> which will also unregister device, it's fine to remove origin
Hi, Hsin-Yi:
On Wed, 2019-05-29 at 18:25 +0800, Hsin-Yi Wang wrote:
> detatch panel in mtk_dsi_destroy_conn_enc(), since .bind will try to
> attach it again.
>
Reviewed-by: CK Hu
> Fixes: 2e54c14e310f ("drm/mediatek: Add DSI sub driver")
> Signed-off-by: Hsin-Yi Wa
Hi, Hsin-Yi:
On Mon, 2019-05-27 at 12:50 +0800, Hsin-Yi Wang wrote:
> Unbinding components (i.e. mtk_dsi and mtk_disp_ovl/rdma/color) will
> trigger master(mtk_drm)'s .unbind(), and currently mtk_drm's unbind
> won't actually unbind components. During the next bind,
> mtk_drm_kms_init() is called,
Hi, Hsin-Yi:
On Wed, 2019-05-29 at 15:06 +0800, Hsin-Yi Wang wrote:
> On Wed, May 29, 2019 at 9:35 AM CK Hu wrote:
>
> >
> > I think mtk_dsi_destroy_conn_enc() has much thing to do and I would like
> > you to do more. You could refer to [2] for complete implementatio
Hi, Hsin-Yi:
On Wed, 2019-05-29 at 14:08 +0800, Hsin-Yi Wang wrote:
> On Wed, May 29, 2019 at 1:58 PM CK Hu wrote:
> >
> > Hi, Hsin-Yi:
> >
> > On Mon, 2019-05-27 at 12:50 +0800, Hsin-Yi Wang wrote:
> > > There is no clk_prepare() called in mtk_drm_crtc_rese
Hi, Hsin-Yi:
On Mon, 2019-05-27 at 12:50 +0800, Hsin-Yi Wang wrote:
> There is no clk_prepare() called in mtk_drm_crtc_reset(), when unbinding
> drm device, mtk_drm_crtc_destroy() will be triggered, and the clocks will
> be disabled and unprepared in mtk_crtc_ddp_clk_disable. If clk_unprepare()
>
Hi, Hsin-yi:
On Mon, 2019-05-27 at 12:50 +0800, Hsin-Yi Wang wrote:
> move mipi_dsi_host_unregister() to .remove since mipi_dsi_host_register()
> is called in .probe.
In the latest kernel [1], mipi_dsi_host_register() is called in
mtk_dsi_bind(), I think we don't need this part.
[1]
https://git.
Hi, Hsin-Yi:
On Tue, 2019-05-28 at 15:39 +0800, Hsin-Yi Wang wrote:
> mtk_dsi_stop() should be called after mtk_drm_crtc_atomic_disable(), which
> needs
> ovl irq for drm_crtc_wait_one_vblank(), since after mtk_dsi_stop() is called,
> ovl irq will be disabled. If drm_crtc_wait_one_vblank() is cal
Hi, Yongqiang:
On Tue, 2019-04-16 at 16:33 +0800, CK Hu wrote:
> Hi, Yongqiang:
>
> On Wed, 2019-03-27 at 14:19 +0800, yongqiang@mediatek.com wrote:
> > From: Yongqiang Niu
> >
> > Respect page offset for PRIME mmap calls
>
> Reviewed-by: CK Hu
This
Hi, Yongqiang:
On Tue, 2019-04-16 at 16:24 +0800, CK Hu wrote:
> Hi, Yongqiang:
>
> On Wed, 2019-03-27 at 14:19 +0800, yongqiang@mediatek.com wrote:
> > From: Yongqiang Niu
> >
> > display hardware clock will not unprepare when
> > crtc is disable, until
with the addition of HDMI_INFOFRAME_TYPE_DRM in the commit
> below, but the code really should have been future-proofed from the
> start.
Acked-by: CK Hu
>
> Fixes: 2cdbfd66a829 ("drm: Enable HDR infoframe support")
I think "drm: Enable HDR infoframe support" exist o
Hi, Jitao:
On Sun, 2019-05-19 at 17:33 +0800, Jitao Shi wrote:
> On Wed, 2019-05-08 at 10:39 +0800, CK Hu wrote:
> > On Tue, 2019-04-16 at 14:04 +0800, Jitao Shi wrote:
> > > Config the different CMDQ reg address in driver data.
> > >
> > For MT8173, you chang
Hi, Jitao:
On Sun, 2019-05-19 at 17:25 +0800, Jitao Shi wrote:
> DSI panel driver need attach function which is inculde in
> mipi_dsi_host_ops.
>
> If mipi_dsi_host_register is not in probe, dsi panel will
> probe fail or more delay.
In [1], you have agreed this patch just for delay not for prob
On Sun, 2019-05-19 at 17:36 +0800, Jitao Shi wrote:
> On Tue, 2019-05-07 at 17:52 +0800, CK Hu wrote:
> > Hi, Jitao:
> >
> > On Tue, 2019-04-16 at 14:04 +0800, Jitao Shi wrote:
> > > DSI panel driver need attach function which is inculde in
> >
Hi, Jitao:
On Sat, 2019-05-18 at 17:56 +0800, Jitao Shi wrote:
> Pull dpi pins low when dpi has nothing to display. Aovid leakage
> current from some dpi pins (Hsync Vsync DE ... ).
>
> Some chips have dpi pins, but there are some chip don't have pins.
> So this function is controlled by chips dr
Hi, Jitao:
On Sat, 2019-05-18 at 17:56 +0800, Jitao Shi wrote:
> DPI sample the data both rising and falling edge.
> It can reduce half data io pins.
All the registers which you control in this patch exist in MT8173. So I
think this is not a SoC-level feature. This feature depends on how much
io
On Sat, 2019-05-18 at 15:51 +0800, Jitao Shi wrote:
> On Mon, 2019-05-06 at 17:17 +0800, CK Hu wrote:
> > Hi, Jitao:
> >
> > On Tue, 2019-04-16 at 13:42 +0800, Jitao Shi wrote:
> > > This patch add mt8183 mipi_tx driver.
> > > And also support other chi
Reviewed-by: CK Hu
>
> Signed-off-by: Jitao Shi
> ---
> drivers/gpu/drm/mediatek/Makefile | 1 +
> drivers/gpu/drm/mediatek/mtk_mipi_tx.c| 342 ++
> drivers/gpu/drm/mediatek/mtk_mipi_tx.h| 49 +++
> drivers/gpu/drm/med
Hi, Jitao:
On Tue, 2019-04-16 at 14:05 +0800, Jitao Shi wrote:
> Add mt8183 dsi driver data. Enable size control and
> reg commit control.
>
Reviewed-by: CK Hu
> Signed-off-by: Jitao Shi
> ---
> drivers/gpu/drm/mediatek/mtk_dsi.c | 8
> 1 file changed, 8 in
Hi, Jitao:
On Tue, 2019-04-16 at 14:05 +0800, Jitao Shi wrote:
> Our new DSI chip has frame size control.
> So add the driver data to control for different chips.
>
Reviewed-by: CK Hu
> Signed-off-by: Jitao Shi
> ---
> drivers/gpu/drm/mediatek/mtk_dsi.c | 5 +
&g
Hi, Jitao:
On Tue, 2019-04-16 at 14:04 +0800, Jitao Shi wrote:
> New DSI IP has shadow register and working reg. The register
> values are writen to shadow register. And then trigger with
> commit reg, the register values will be moved working register.
This patch looks good, but the message is n
On Tue, 2019-04-16 at 14:04 +0800, Jitao Shi wrote:
> Config the different CMDQ reg address in driver data.
>
For MT8173, you change reg_cmd_off from 0x180 to 0x200, so this patch is
a bug fix. You should add a 'Fixes' tag.
> Signed-off-by: Jitao Shi
> ---
> drivers/gpu/drm/mediatek/mtk_dsi.c |
Hi, Jitao:
On Tue, 2019-04-16 at 14:04 +0800, Jitao Shi wrote:
> DSI panel driver need attach function which is inculde in
> mipi_dsi_host_ops.
>
> If mipi_dsi_host_register is not in probe, dsi panel will
> probe fail or more delay.
I think this patch just prevent delay, not to prevent dsi pane
Hi, Jitao:
On Tue, 2019-04-16 at 13:52 +0800, Jitao Shi wrote:
I need the commit message. Even though the code is easy to understand,
words for this patch is still necessary.
Regards,
CK
> Signed-off-by: Jitao Shi
> ---
> drivers/gpu/drm/mediatek/mtk_dpi.c | 19 +++
> 1 file c
Hi, Jitao:
On Tue, 2019-04-16 at 13:52 +0800, Jitao Shi wrote:
Where is the commit message? I think you could introduce what is dual
edge (Maybe it's trivial for you, but not for me)
Regards,
CK
> Signed-off-by: Jitao Shi
> ---
> drivers/gpu/drm/mediatek/mtk_dpi.c | 10 ++
> 1 file ch
Hi, Jitao:
On Tue, 2019-04-16 at 13:42 +0800, Jitao Shi wrote:
> This patch add mt8183 mipi_tx driver.
> And also support other chips that use the same binding and driver.
>
> Signed-off-by: Jitao Shi
> ---
> drivers/gpu/drm/mediatek/Makefile | 1 +
> drivers/gpu/drm/mediatek/mtk_
Hi, Jitao:
On Tue, 2019-04-16 at 16:54 +0800, Jitao Shi wrote:
> Add dsi and mipitx nodes to the mt8183
>
> Signed-off-by: Jitao Shi
> ---
> arch/arm64/boot/dts/mediatek/mt8183.dtsi | 25
> 1 file changed, 25 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/
Hi, Frank:
On Tue, 2019-04-16 at 16:58 +0200, Frank Wunderlich wrote:
> From: chunhui dai
>
> - 1080 plg in/out with ng/ok
> - support other resolutions like 1280x1024
The description is so simple and I could not understand why
pll_default_off could fix this problem. And why only MT2701 has thi
Hi, Frank:
On Wed, 2019-04-17 at 07:30 +0200, Frank Wunderlich wrote:
> Hi CK Hu,
>
> you mean the problematic patch is fix possible_crtcs (4/4) and the others are
> ok?
>
> can you push the first 3 while working on the last one?
I think 3 patches is related to possible
Hi, Frank:
On Tue, 2019-04-16 at 16:58 +0200, Frank Wunderlich wrote:
> This Patch-Series adds missing Patches/Bugfixes to get hdmi working on BPI-R2
>
> first 2 Patches were already posted, but not yet merged into mainline
> i found no hint why
> - config component output by device node port
>
Hi, Yongqiang:
On Wed, 2019-03-27 at 14:19 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> Respect page offset for PRIME mmap calls
Reviewed-by: CK Hu
>
> Signed-off-by: Yongqiang Niu
> ---
> drivers/gpu/drm/mediatek/mtk_drm_gem.c | 7 ++-
Hi, Yongqiang:
On Wed, 2019-03-27 at 14:19 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> This patch add add vmap support for mediatek drm
I think the upstreamed patch 'drm/mediatek: Implement gem prime
vmap/vunmap function' [1] has the same function of this patch. You could
Hi, Yongqiang:
On Wed, 2019-03-27 at 14:19 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> display hardware clock will not unprepare when
> crtc is disable, until crtc is destroyed.
> with this patch, hard clock will disable and unprepare
> at the same time
Hi, Yongqiang:
On Wed, 2019-03-27 at 14:19 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> This patch add ovl0/ovl0_2l usecase
> in ovl->ovl0_2l direct link usecase:
> 1. the crtc support layer number will 4+2
> 2. ovl0_2l background color input select ovl0 when crtc init
> an
Hi, Yongqiang:
On Wed, 2019-03-27 at 14:19 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> This patch add RDMA fifo size error handle
> rdma fifo size will not always bigger than the calculated threshold
> if that case happened, we need set fifo size as the threshold
>
> Sign
Hi, Yongqiang:
On Wed, 2019-03-27 at 14:19 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> This patch add background color input select function for ovl/ovl_2l
>
> ovl include 4 DRAM layer and 1 background color layer
> ovl_2l include 4 DRAM layer and 1 background color layer
Hi, Yongqiang:
On Wed, 2019-03-27 at 14:19 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> This patch add ddp write register common api
> this is preparation patch for ovl/ovl_2l direct link
> usecase.
> in that case, we need this funtion to set one bit of ovl_2l
> register
T
Hi, Yongqiang:
On Wed, 2019-03-27 at 14:19 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> This patch add function to background color input select for ovl/ovl_2l
> direct link
> for ovl/ovl_2l direct link usecase, we need set background color
> input select for these hardwar
reparation for ovl-2l and
> ovl share the same driver.
Reviewed-by: CK Hu
>
> Signed-off-by: Yongqiang Niu
> ---
> drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 7 ++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mt
Hi, Yongqiang:
On Wed, 2019-03-27 at 14:19 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> This patch add mmsys private data for ddp path config
> all these register offset and value will be different in future SOC
> add these define into mmsys private data
> u32 ovl0_mo
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