Re: [linux-sunxi] [PATCH 00/12] Add support for Orange Pi 3
Hi, On Sun, 7 Apr 2019 at 16:32, Ondřej Jirman wrote: > > On Sun, Apr 07, 2019 at 03:36:21PM +0200, Clément Péron wrote: > > Hi, > > > > On Sat, 6 Apr 2019 at 01:45, megous via linux-sunxi > > wrote: > > > > > > From: Ondrej Jirman > > > > > > This series implements support for Xunlong Orange Pi 3 board. > > > > OrangePi 3 Lite2 and One Plus boards support has already been merged. > > The support is not complete but you should rebase your patches on top > > of sunxi/for-next > > Hi, > > OrangePi 3 is somewhat different from these two boards (mostly it has a > differnt > power tree). It doesn't use the AXP regulators that are defined in the > sun50i-h6-orangepi.dtsi in the same way. > > For example: > > - bldo3 (is turned always on in sun50i-h6-orangepi.dtsi but unused for opi3) > - cldo2 and cldo3 are unused on opi3 and have nothing to do with WiFi > - aldo3 is not for dram > - bldo1 on the other hand is for dram on opi3 > - some other regulators are used for different/more functions and thus > named differntly > - USB id-det pin is differnt > - ... > > OrangePi 3 is not a superset of what is defined in sun50i-h6-orangepi.dtsi. > > So to base Orange Pi 3 dts on top of existing sun50i-h6-orangepi.dtsi I'd have > to first move some things out of the base dtsi to the OrangePi Lite2 and One > Plus board dts files, in order to have sun50i-h6-orangepi.dtsi only describe > HW > that is *really* shared by these 2 boards and Orange Pi 3. > > If I do that, I'd undefine all the axp805 regulator nodes and move the > configurations to each of the 3 board files. That will probably end up being > the least confusing and most maintainable. See axp81x.dtsi lines 86-144 for > what I mean. > > What do you think? Is this acceptable to everyone? Indeed it seems to be a totally different board, not as much in common as I thought with Lite2 and One Plus. You should also add your board in Documentation devicetree/bindings/arm/sunxi.yaml Regards, Clement > > regards, > o. > > > https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux.git/tree/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi?h=sunxi/for-next > > > > Regards, > > Clement > > > > > > > > Unfortunately, this board needs some small driver patches, so I have > > > split the boards DT patch into chunks that require patches for drivers > > > in various subsystems: > > > > > > - Basic DT for the board (patch 1) > > > - HDMI support(patches 2, 3, 4) > > > - Ethernet support(patches 5, 6, 7) > > > - WiFi support(patches 8, 9, 10, 11, 12) > > > > > > This patch is also needed to not get segfault on boot: > > > https://lkml.org/lkml/2019/4/5/856 > > > > > > Please take a look. > > > > > > regards, > > > Ondrej Jirman > > > > > > Icenowy Zheng (2): > > > net: stmmac: sun8i: add support for Allwinner H6 EMAC > > > net: stmmac: sun8i: force select external PHY when no internal one > > > > > > Ondrej Jirman (10): > > > arm64: dts: allwinner: h6: Add Orange Pi 3 DTS > > > drm: sun4i: Add support for enabling DDC I2C bus to dw_hdmi glue > > > dt-bindings: display: sun4i-drm: Add DDC power supply > > > arm64: dts: allwinner: orange-pi-3: Enable HDMI output > > > arm64: dts: allwinner: orange-pi-3: Enable ethernet > > > arm64: dts: allwinner: h6: Add MMC1 pins > > > pinctrl: sunxi: Prepare for alternative bias voltage setting methods > > > pinctrl: sunxi: Support I/O bias voltage setting on H6 > > > brcmfmac: Loading the correct firmware for brcm43456 > > > arm64: dts: allwinner: orange-pi-3: Enable WiFi > > > > > > .../bindings/display/sunxi/sun4i-drm.txt | 1 + > > > arch/arm64/boot/dts/allwinner/Makefile| 1 + > > > .../dts/allwinner/sun50i-h6-orangepi-3.dts| 339 ++ > > > arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 9 + > > > drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c | 17 +- > > > drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h | 1 + > > > .../net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 22 ++ > > > .../broadcom/brcm80211/brcmfmac/sdio.c| 4 +- > > > drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c | 1 + > > > drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c | 2 +- > > > drivers/pinctrl/sunxi/pinctrl-sunxi.c | 50 ++- > > > drivers/pinctrl/sunxi/pinctrl-sunxi.h | 7 +- > > > 12 files changed, 433 insertions(+), 21 deletions(-) > > > create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts > > > > > > -- > > > 2.21.0 > > > > > > -- > > > You received this message because you are subscribed to the Google Groups > > > "linux-sunxi" group. > > > To unsubscribe from this group and stop receiving emails from it, send an > > > email to linux-sunxi+unsubscr...@googlegroups.com. > > > For more options, visit https://groups.google.com/d/optout. ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [linux-sunxi] [PATCH 12/12] arm64: dts: allwinner: orange-pi-3: Enable WiFi
Hi,
On Sat, 6 Apr 2019 at 01:45, megous via linux-sunxi
wrote:
>
> From: Ondrej Jirman
>
> Orange Pi 3 has AP6256 WiFi/BT module. WiFi part of the module is
> called bcm43356 and can be used with the brcmfmac driver. The module
> is powered by the two always on regulators (not AXP805).
>
> WiFi uses a PG port with 1.8V voltage level signals. SoC needs to be
> configured so that it sets up an 1.8V input bias on this port. This is
> done by the pio driver by reading the vcc-pg-supply voltage.
>
> You'll need a fw_bcm43456c5_ag.bin firmware file and nvram.txt
> configuration that can be found in the Xulongs's repository for H6:
>
> https://github.com/orangepi-xunlong/OrangePiH6_external/tree/master/ap6256
>
> Mainline brcmfmac driver expects the firmware and nvram at the
> following paths relative to the firmware directory:
>
> brcm/brcmfmac43456-sdio.bin
> brcm/brcmfmac43456-sdio.txt
>
> Signed-off-by: Ondrej Jirman
> ---
> .../dts/allwinner/sun50i-h6-orangepi-3.dts| 48 +++
> 1 file changed, 48 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
> b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
> index 5270142527f5..6a201829bb62 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
> @@ -66,6 +66,26 @@
> regulator-always-on;
> };
>
> + reg_vcc33_wifi: vcc33-wifi {
> + /* Always on 3.3V regulator for WiFi and BT */
> + compatible = "regulator-fixed";
> + regulator-name = "vcc33-wifi";
> + regulator-min-microvolt = <330>;
> + regulator-max-microvolt = <330>;
> + regulator-always-on;
> +vin-supply = <_vcc5v>;
> + };
> +
> + reg_vcc_wifi_io: vcc-wifi-io {
> + /* Always on 1.8V/300mA regulator for WiFi and BT IO */
> + compatible = "regulator-fixed";
> + regulator-name = "vcc-wifi-io";
> + regulator-min-microvolt = <180>;
> + regulator-max-microvolt = <180>;
> + regulator-always-on;
> +vin-supply = <_vcc33_wifi>;
> + };
> +
> /*
> * The board uses 2.5V RGMII signalling. Power sequence
> * to enable the phy is to enable GMAC-2V5 and GMAC-3V3 (aldo2)
> @@ -86,6 +106,14 @@
> */
> vin-supply = <_aldo2>; /* GMAC-3V3 */
> };
> +
> + wifi_pwrseq: wifi_pwrseq {
> + compatible = "mmc-pwrseq-simple";
> + clocks = < 1>;
Maybe I missed something, but the RTC in H6 is not yet available :
https://lkml.org/lkml/2018/10/31/822
Regards,
Clement
> + clock-names = "ext_clock";
> + reset-gpios = <_pio 1 3 GPIO_ACTIVE_LOW>; /* PM3 */
> + post-power-on-delay-ms = <200>;
> + };
> };
>
> {
> @@ -146,6 +174,25 @@
> status = "okay";
> };
>
> + {
> + pinctrl-names = "default";
> + pinctrl-0 = <_pins>;
> + vmmc-supply = <_vcc33_wifi>;
> + vqmmc-supply = <_vcc_wifi_io>;
> + mmc-pwrseq = <_pwrseq>;
> + bus-width = <4>;
> + non-removable;
> + status = "okay";
> +
> + brcm: sdio-wifi@1 {
> + reg = <1>;
> + compatible = "brcm,bcm4329-fmac";
> + interrupt-parent = <_pio>;
> + interrupts = <1 0 IRQ_TYPE_LEVEL_LOW>; /* PM0 */
> + interrupt-names = "host-wake";
> + };
> +};
> +
> {
> status = "okay";
> };
> @@ -157,6 +204,7 @@
> {
> vcc-pc-supply = <_bldo2>;
> vcc-pd-supply = <_cldo1>;
> + vcc-pg-supply = <_vcc_wifi_io>;
> };
>
> _i2c {
> --
> 2.21.0
>
> --
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Re: [linux-sunxi] [PATCH 00/12] Add support for Orange Pi 3
Hi, On Sat, 6 Apr 2019 at 01:45, megous via linux-sunxi wrote: > > From: Ondrej Jirman > > This series implements support for Xunlong Orange Pi 3 board. OrangePi 3 Lite2 and One Plus boards support has already been merged. The support is not complete but you should rebase your patches on top of sunxi/for-next https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux.git/tree/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi?h=sunxi/for-next Regards, Clement > > Unfortunately, this board needs some small driver patches, so I have > split the boards DT patch into chunks that require patches for drivers > in various subsystems: > > - Basic DT for the board (patch 1) > - HDMI support(patches 2, 3, 4) > - Ethernet support(patches 5, 6, 7) > - WiFi support(patches 8, 9, 10, 11, 12) > > This patch is also needed to not get segfault on boot: > https://lkml.org/lkml/2019/4/5/856 > > Please take a look. > > regards, > Ondrej Jirman > > Icenowy Zheng (2): > net: stmmac: sun8i: add support for Allwinner H6 EMAC > net: stmmac: sun8i: force select external PHY when no internal one > > Ondrej Jirman (10): > arm64: dts: allwinner: h6: Add Orange Pi 3 DTS > drm: sun4i: Add support for enabling DDC I2C bus to dw_hdmi glue > dt-bindings: display: sun4i-drm: Add DDC power supply > arm64: dts: allwinner: orange-pi-3: Enable HDMI output > arm64: dts: allwinner: orange-pi-3: Enable ethernet > arm64: dts: allwinner: h6: Add MMC1 pins > pinctrl: sunxi: Prepare for alternative bias voltage setting methods > pinctrl: sunxi: Support I/O bias voltage setting on H6 > brcmfmac: Loading the correct firmware for brcm43456 > arm64: dts: allwinner: orange-pi-3: Enable WiFi > > .../bindings/display/sunxi/sun4i-drm.txt | 1 + > arch/arm64/boot/dts/allwinner/Makefile| 1 + > .../dts/allwinner/sun50i-h6-orangepi-3.dts| 339 ++ > arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 9 + > drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c | 17 +- > drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h | 1 + > .../net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 22 ++ > .../broadcom/brcm80211/brcmfmac/sdio.c| 4 +- > drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c | 1 + > drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c | 2 +- > drivers/pinctrl/sunxi/pinctrl-sunxi.c | 50 ++- > drivers/pinctrl/sunxi/pinctrl-sunxi.h | 7 +- > 12 files changed, 433 insertions(+), 21 deletions(-) > create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts > > -- > 2.21.0 > > -- > You received this message because you are subscribed to the Google Groups > "linux-sunxi" group. > To unsubscribe from this group and stop receiving emails from it, send an > email to linux-sunxi+unsubscr...@googlegroups.com. > For more options, visit https://groups.google.com/d/optout. ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 1/8] dt-bindings: gpu: mali-midgard: Add resets property
From: Neil Armstrong The Amlogic ARM Mali Midgard requires reset controls to power on and software reset the GPU, adds these as optional in the bindings. Signed-off-by: Neil Armstrong Reviewed-by: Rob Herring Signed-off-by: Kevin Hilman --- .../devicetree/bindings/gpu/arm,mali-midgard.txt | 14 ++ 1 file changed, 14 insertions(+) diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt index 18a2cde2e5f3..1b1a74129141 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt +++ b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt @@ -37,6 +37,20 @@ Optional properties: - operating-points-v2 : Refer to Documentation/devicetree/bindings/opp/opp.txt for details. +- resets : Phandle of the GPU reset line. + +Vendor-specific bindings + + +The Mali GPU is integrated very differently from one SoC to +another. In order to accomodate those differences, you have the option +to specify one more vendor-specific compatible, among: + +- "amlogic,meson-gxm-mali" + Required properties: + - resets : Should contain phandles of : ++ GPU reset line ++ GPU APB glue reset line Example for a Mali-T760: -- 2.17.1 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 0/8] Add Allwinner H6 Mali Midgard gpu node
Hi, The Allwinner H6 has a Mali-T720 MP2. The drivers are out-of-tree so this serie only introduce the dt-bindings. The first patch is from Neil Amstrong and has been already merged in linux-amlogic. It is required for this serie. The second patch is from Icenowy Zheng where I changed the order has required by Rob Herring. See: https://patchwork.kernel.org/patch/10699829/ The GPU opp table is taken from Jernej Škrabec's patch on LibreELEC.tv. Thanks, Clement Clément Péron (7): dt-bindings: gpu: add bus clock for Mali Midgard GPUs dt-bindings: gpu: mali-midgard: Add h6 mali gpu compatible arm64: dts: allwinner: Add ARM Mali GPU node for H6 arm64: dts: allwinner: Add mali GPU supply for Pine H64 arm64: dts: allwinner: Add mali GPU supply for Beelink GS1 arm64: dts: allwinner: Add mali GPU supply for OrangePi Boards arm64: dts: allwinner: Add mali GPU supply for OrangePi 3 Neil Armstrong (1): dt-bindings: gpu: mali-midgard: Add resets property .../bindings/gpu/arm,mali-midgard.txt | 26 ++ .../dts/allwinner/sun50i-h6-beelink-gs1.dts | 5 ++ .../dts/allwinner/sun50i-h6-orangepi-3.dts| 5 ++ .../dts/allwinner/sun50i-h6-orangepi.dtsi | 5 ++ .../boot/dts/allwinner/sun50i-h6-pine-h64.dts | 5 ++ arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 80 +++ 6 files changed, 126 insertions(+) -- 2.17.1 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 5/8] arm64: dts: allwinner: Add mali GPU supply for Pine H64
Enable and add supply to the Mali GPU node on the
Pine H64 board.
Signed-off-by: Clément Péron
---
arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
index 4802902e128f..e16a8c6738f9 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
@@ -85,6 +85,11 @@
status = "okay";
};
+ {
+ mali-supply = <_dcdcc>;
+ status = "okay";
+};
+
{
status = "okay";
};
--
2.17.1
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[PATCH 8/8] arm64: dts: allwinner: Add mali GPU supply for OrangePi 3
Enable and add supply to the Mali GPU node on the
Orange Pi 3 board.
Signed-off-by: Clément Péron
---
arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
index 17d496990108..d4c989cc92a7 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
@@ -58,6 +58,11 @@
status = "okay";
};
+ {
+ mali-supply = <_dcdcc>;
+ status = "okay";
+};
+
{
vmmc-supply = <_cldo1>;
cd-gpios = < 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
--
2.17.1
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Re: [PATCH 4/8] arm64: dts: allwinner: Add ARM Mali GPU node for H6
Hi,
On Thu, 11 Apr 2019 at 09:28, Maxime Ripard wrote:
>
> On Thu, Apr 11, 2019 at 01:25:39AM +0200, Clément Péron wrote:
> > Add the mali gpu node to the H6 device-tree.
> >
> > Signed-off-by: Clément Péron
> > ---
> > arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 80
> > 1 file changed, 80 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> > b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> > index e0dc4a05c1ba..152b2128aadf 100644
> > --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> > +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> > @@ -17,6 +17,71 @@
> > #address-cells = <1>;
> > #size-cells = <1>;
> >
> > + gpu_opp_table: opp_table1 {
> > + compatible = "operating-points-v2";
> > +
> > + opp@75600 {
> > + opp-hz = /bits/ 64 <75600>;
> > + opp-microvolt = <104>;
> > + };
> > + opp@62400 {
> > + opp-hz = /bits/ 64 <62400>;
> > + opp-microvolt = <95>;
> > + };
> > + opp@57600 {
> > + opp-hz = /bits/ 64 <57600>;
> > + opp-microvolt = <93>;
> > + };
> > + opp@54000 {
> > + opp-hz = /bits/ 64 <54000>;
> > + opp-microvolt = <91>;
> > + };
> > + opp@50400 {
> > + opp-hz = /bits/ 64 <50400>;
> > + opp-microvolt = <89>;
> > + };
> > + opp@45600 {
> > + opp-hz = /bits/ 64 <45600>;
> > + opp-microvolt = <87>;
> > + };
> > + opp@43200 {
> > + opp-hz = /bits/ 64 <43200>;
> > + opp-microvolt = <86>;
> > + };
> > + opp@42000 {
> > + opp-hz = /bits/ 64 <42000>;
> > + opp-microvolt = <85>;
> > + };
> > + opp@40800 {
> > + opp-hz = /bits/ 64 <40800>;
> > + opp-microvolt = <84>;
> > + };
> > + opp@38400 {
> > + opp-hz = /bits/ 64 <38400>;
> > + opp-microvolt = <83>;
> > + };
> > + opp@36000 {
> > + opp-hz = /bits/ 64 <36000>;
> > + opp-microvolt = <82>;
> > + };
> > + opp@33600 {
> > + opp-hz = /bits/ 64 <33600>;
> > + opp-microvolt = <81>;
> > + };
> > + opp@31200 {
> > + opp-hz = /bits/ 64 <31200>;
> > + opp-microvolt = <81>;
> > + };
> > + opp@26400 {
> > + opp-hz = /bits/ 64 <26400>;
> > + opp-microvolt = <81>;
> > + };
> > + opp@21600 {
> > + opp-hz = /bits/ 64 <21600>;
> > + opp-microvolt = <81>;
> > + };
> > + };
> > +
>
> How were those OPPs tested?
They are taken from the vendor device tree.
https://github.com/Allwinner-Homlet/H6-BSP4.9-linux/blob/master/arch/arm64/boot/dts/sunxi/sun50iw6p1.dtsi#L2121
Clement
>
> Maxime
>
> --
> Maxime Ripard, Bootlin
> Embedded Linux and Kernel engineering
> https://bootlin.com
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[PATCH 2/8] dt-bindings: gpu: add bus clock for Mali Midgard GPUs
Some SoCs adds a bus clock gate to the Mali Midgard GPU. Add the binding for the bus clock. Signed-off-by: Icenowy Zheng Signed-off-by: Clément Péron --- Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt | 6 ++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt index 1b1a74129141..2e8bbce35695 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt +++ b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt @@ -31,6 +31,12 @@ Optional properties: - clocks : Phandle to clock for the Mali Midgard device. +- clock-names : Specify the names of the clocks specified in clocks + when multiple clocks are present. +* core: clock driving the GPU itself (When only one clock is present, + assume it's this clock.) +* bus: bus clock for the GPU + - mali-supply : Phandle to regulator for the Mali device. Refer to Documentation/devicetree/bindings/regulator/regulator.txt for details. -- 2.17.1 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 7/8] arm64: dts: allwinner: Add mali GPU supply for OrangePi Boards
Enable and add supply to the Mali GPU node on the
Orange Pi One Plus and Lite2 boards.
Signed-off-by: Clément Péron
---
arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
index 62e27948a3fa..bd13297555ab 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
@@ -55,6 +55,11 @@
status = "okay";
};
+ {
+ mali-supply = <_dcdcc>;
+ status = "okay";
+};
+
{
vmmc-supply = <_cldo1>;
cd-gpios = < 5 6 GPIO_ACTIVE_LOW>;
--
2.17.1
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[PATCH 6/8] arm64: dts: allwinner: Add mali GPU supply for Beelink GS1
Enable and add supply to the Mali GPU node on the
Beelink GS1 board.
Signed-off-by: Clément Péron
---
arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
index 0dc33c90dd60..21440d572f0a 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
@@ -70,6 +70,11 @@
status = "okay";
};
+ {
+ mali-supply = <_dcdcc>;
+ status = "okay";
+};
+
{
status = "okay";
};
--
2.17.1
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[PATCH 3/8] dt-bindings: gpu: mali-midgard: Add h6 mali gpu compatible
This add the H6 mali compatible in the dt-bindings to later support specific implementation. Signed-off-by: Clément Péron --- .../devicetree/bindings/gpu/arm,mali-midgard.txt | 8 +++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt index 2e8bbce35695..9e71146b5c8a 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt +++ b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt @@ -15,6 +15,7 @@ Required properties: + "arm,mali-t860" + "arm,mali-t880" * which must be preceded by one of the following vendor specifics: ++ "allwinner,sun50i-h6-mali" + "amlogic,meson-gxm-mali" + "rockchip,rk3288-mali" + "rockchip,rk3399-mali" @@ -49,9 +50,14 @@ Vendor-specific bindings The Mali GPU is integrated very differently from one SoC to -another. In order to accomodate those differences, you have the option +another. In order to accommodate those differences, you have the option to specify one more vendor-specific compatible, among: +- "allwinner,sun50i-h6-mali" + Required properties: + - resets: Should contain phandle of : ++ GPU reset line + - "amlogic,meson-gxm-mali" Required properties: - resets : Should contain phandles of : -- 2.17.1 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 4/8] arm64: dts: allwinner: Add ARM Mali GPU node for H6
Add the mali gpu node to the H6 device-tree.
Signed-off-by: Clément Péron
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 80
1 file changed, 80 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index e0dc4a05c1ba..152b2128aadf 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -17,6 +17,71 @@
#address-cells = <1>;
#size-cells = <1>;
+ gpu_opp_table: opp_table1 {
+ compatible = "operating-points-v2";
+
+ opp@75600 {
+ opp-hz = /bits/ 64 <75600>;
+ opp-microvolt = <104>;
+ };
+ opp@62400 {
+ opp-hz = /bits/ 64 <62400>;
+ opp-microvolt = <95>;
+ };
+ opp@57600 {
+ opp-hz = /bits/ 64 <57600>;
+ opp-microvolt = <93>;
+ };
+ opp@54000 {
+ opp-hz = /bits/ 64 <54000>;
+ opp-microvolt = <91>;
+ };
+ opp@50400 {
+ opp-hz = /bits/ 64 <50400>;
+ opp-microvolt = <89>;
+ };
+ opp@45600 {
+ opp-hz = /bits/ 64 <45600>;
+ opp-microvolt = <87>;
+ };
+ opp@43200 {
+ opp-hz = /bits/ 64 <43200>;
+ opp-microvolt = <86>;
+ };
+ opp@42000 {
+ opp-hz = /bits/ 64 <42000>;
+ opp-microvolt = <85>;
+ };
+ opp@40800 {
+ opp-hz = /bits/ 64 <40800>;
+ opp-microvolt = <84>;
+ };
+ opp@38400 {
+ opp-hz = /bits/ 64 <38400>;
+ opp-microvolt = <83>;
+ };
+ opp@36000 {
+ opp-hz = /bits/ 64 <36000>;
+ opp-microvolt = <82>;
+ };
+ opp@33600 {
+ opp-hz = /bits/ 64 <33600>;
+ opp-microvolt = <81>;
+ };
+ opp@31200 {
+ opp-hz = /bits/ 64 <31200>;
+ opp-microvolt = <81>;
+ };
+ opp@26400 {
+ opp-hz = /bits/ 64 <26400>;
+ opp-microvolt = <81>;
+ };
+ opp@21600 {
+ opp-hz = /bits/ 64 <21600>;
+ opp-microvolt = <81>;
+ };
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -157,6 +222,21 @@
allwinner,sram = <_sram 1>;
};
+ gpu: gpu@180 {
+ compatible = "allwinner,sun50i-h6-mali",
+"arm,mali-t720";
+ reg = <0x0180 0x4000>;
+ interrupts = ,
+,
+;
+ interrupt-names = "job", "mmu", "gpu";
+ clocks = < CLK_GPU>, < CLK_BUS_GPU>;
+ clock-names = "core", "bus";
+ resets = < RST_BUS_GPU>;
+ operating-points-v2 = <_opp_table>;
+ status = "disabled";
+ };
+
syscon: syscon@300 {
compatible = "allwinner,sun50i-h6-system-control",
"allwinner,sun50i-a64-system-control";
--
2.17.1
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[PATCH v2 6/8] arm64: dts: allwinner: Add mali GPU supply for Beelink GS1
Enable and add supply to the Mali GPU node on the
Beelink GS1 board.
Signed-off-by: Clément Péron
---
arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
index 0dc33c90dd60..21440d572f0a 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
@@ -70,6 +70,11 @@
status = "okay";
};
+ {
+ mali-supply = <_dcdcc>;
+ status = "okay";
+};
+
{
status = "okay";
};
--
2.17.1
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Re: [PATCH v2 4/8] arm64: dts: allwinner: Add ARM Mali GPU node for H6
Hi,
On Thu, 11 Apr 2019 at 17:05, Jernej Škrabec wrote:
>
> Dne četrtek, 11. april 2019 ob 12:57:16 CEST je Clément Péron napisal(a):
> > Add the mali gpu node to the H6 device-tree.
> >
> > Signed-off-by: Clément Péron
> > ---
> > arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 14 ++
> > 1 file changed, 14 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> > b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi index
> > e0dc4a05c1ba..196753110434 100644
> > --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> > +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> > @@ -157,6 +157,20 @@
> > allwinner,sram = <_sram 1>;
> > };
> >
> > + gpu: gpu@180 {
> > + compatible = "allwinner,sun50i-h6-mali",
> > + "arm,mali-t720";
> > + reg = <0x0180 0x4000>;
> > + interrupts = IRQ_TYPE_LEVEL_HIGH>,
> > + IRQ_TYPE_LEVEL_HIGH>,
> > + IRQ_TYPE_LEVEL_HIGH>;
> > + interrupt-names = "job", "mmu", "gpu";
> > + clocks = < CLK_GPU>, < CLK_BUS_GPU>;
> > + clock-names = "core", "bus";
> > + resets = < RST_BUS_GPU>;
> > + status = "disabled";
>
> Usually self sufficient peripherals are enabled by default in DTSI.
I follow the other Mali Midgard (rk3399, rk3288) syntax.
But I think you're right here, will go for an update I think.
Clement
>
> > + };
> > +
> > syscon: syscon@300 {
> > compatible = "allwinner,sun50i-h6-system-
> control",
> >"allwinner,sun50i-a64-
> system-control";
>
>
>
>
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Re: [PATCH v2 2/8] dt-bindings: gpu: add bus clock for Mali Midgard GPUs
Hi, On Thu, 11 Apr 2019 at 14:30, Maxime Ripard wrote: > > On Thu, Apr 11, 2019 at 12:57:14PM +0200, Clément Péron wrote: > > Some SoCs adds a bus clock gate to the Mali Midgard GPU. > > > > Add the binding for the bus clock. > > > > Signed-off-by: Icenowy Zheng > > Signed-off-by: Clément Péron > > I'm not quite sure what you did there. If Icenowy is the author and > you're sending that commit on her behalf, then she should have the > authorship of that commit. Indeed bad cherry pick, I will change the author sorry for that. Clément > > If you're the author of that commit, then we Icenowy's SoB is there? > > Maxime > > -- > Maxime Ripard, Bootlin > Embedded Linux and Kernel engineering > https://bootlin.com ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH 3/8] dt-bindings: gpu: mali-midgard: Add h6 mali gpu compatible
Hi, On Thu, 11 Apr 2019 at 09:27, Maxime Ripard wrote: > > On Thu, Apr 11, 2019 at 01:25:38AM +0200, Clément Péron wrote: > > This add the H6 mali compatible in the dt-bindings to later support > > specific implementation. > > > > Signed-off-by: Clément Péron > > --- > > .../devicetree/bindings/gpu/arm,mali-midgard.txt | 8 +++- > > 1 file changed, 7 insertions(+), 1 deletion(-) > > > > diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt > > b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt > > index 2e8bbce35695..9e71146b5c8a 100644 > > --- a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt > > +++ b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt > > @@ -15,6 +15,7 @@ Required properties: > > + "arm,mali-t860" > > + "arm,mali-t880" > >* which must be preceded by one of the following vendor specifics: > > ++ "allwinner,sun50i-h6-mali" > > + "amlogic,meson-gxm-mali" > > + "rockchip,rk3288-mali" > > + "rockchip,rk3399-mali" > > @@ -49,9 +50,14 @@ Vendor-specific bindings > > > > > > The Mali GPU is integrated very differently from one SoC to > > -another. In order to accomodate those differences, you have the option > > +another. In order to accommodate those differences, you have the option > > to specify one more vendor-specific compatible, among: > > > > +- "allwinner,sun50i-h6-mali" > > + Required properties: > > + - resets: Should contain phandle of : > > ++ GPU reset line > > + > > And clocks, I assume? Yes you're right clocks are also required for the H6. Clement > > Maxime > > -- > Maxime Ripard, Bootlin > Embedded Linux and Kernel engineering > https://bootlin.com ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v2 8/8] arm64: dts: allwinner: Add mali GPU supply for OrangePi 3
Enable and add supply to the Mali GPU node on the
Orange Pi 3 board.
Signed-off-by: Clément Péron
---
arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
index 17d496990108..d4c989cc92a7 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
@@ -58,6 +58,11 @@
status = "okay";
};
+ {
+ mali-supply = <_dcdcc>;
+ status = "okay";
+};
+
{
vmmc-supply = <_cldo1>;
cd-gpios = < 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
--
2.17.1
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[PATCH v2 4/8] arm64: dts: allwinner: Add ARM Mali GPU node for H6
Add the mali gpu node to the H6 device-tree.
Signed-off-by: Clément Péron
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index e0dc4a05c1ba..196753110434 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -157,6 +157,20 @@
allwinner,sram = <_sram 1>;
};
+ gpu: gpu@180 {
+ compatible = "allwinner,sun50i-h6-mali",
+"arm,mali-t720";
+ reg = <0x0180 0x4000>;
+ interrupts = ,
+,
+;
+ interrupt-names = "job", "mmu", "gpu";
+ clocks = < CLK_GPU>, < CLK_BUS_GPU>;
+ clock-names = "core", "bus";
+ resets = < RST_BUS_GPU>;
+ status = "disabled";
+ };
+
syscon: syscon@300 {
compatible = "allwinner,sun50i-h6-system-control",
"allwinner,sun50i-a64-system-control";
--
2.17.1
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[PATCH v2 0/8] Add Allwinner H6 Mali Midgard GPU
Hi, The Allwinner H6 has a Mali-T720 MP2. The drivers are out-of-tree so this series only introduce the dt-bindings. The first patch is from Neil Amstrong and has been already merged in linux-amlogic. It is required for this series. The second patch is from Icenowy Zheng where I changed the order has required by Rob Herring. See: https://patchwork.kernel.org/patch/10699829/ The GPU opp table was taken from Jernej Škrabec's patch on LibreELEC.tv. Thanks, Clement Changes in v2 (Thanks to Maxime Ripard): - Drop GPU OPP Table - Add clocks and clock-names in required Clément Péron (7): dt-bindings: gpu: add bus clock for Mali Midgard GPUs dt-bindings: gpu: mali-midgard: Add h6 mali gpu compatible arm64: dts: allwinner: Add ARM Mali GPU node for H6 arm64: dts: allwinner: Add mali GPU supply for Pine H64 arm64: dts: allwinner: Add mali GPU supply for Beelink GS1 arm64: dts: allwinner: Add mali GPU supply for OrangePi Boards arm64: dts: allwinner: Add mali GPU supply for OrangePi 3 Neil Armstrong (1): dt-bindings: gpu: mali-midgard: Add resets property .../bindings/gpu/arm,mali-midgard.txt | 27 +++ .../dts/allwinner/sun50i-h6-beelink-gs1.dts | 5 .../dts/allwinner/sun50i-h6-orangepi-3.dts| 5 .../dts/allwinner/sun50i-h6-orangepi.dtsi | 5 .../boot/dts/allwinner/sun50i-h6-pine-h64.dts | 5 arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 14 ++ 6 files changed, 61 insertions(+) -- 2.17.1 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v2 7/8] arm64: dts: allwinner: Add mali GPU supply for OrangePi Boards
Enable and add supply to the Mali GPU node on the
Orange Pi One Plus and Lite2 boards.
Signed-off-by: Clément Péron
---
arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
index 62e27948a3fa..bd13297555ab 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
@@ -55,6 +55,11 @@
status = "okay";
};
+ {
+ mali-supply = <_dcdcc>;
+ status = "okay";
+};
+
{
vmmc-supply = <_cldo1>;
cd-gpios = < 5 6 GPIO_ACTIVE_LOW>;
--
2.17.1
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[PATCH v2 1/8] dt-bindings: gpu: mali-midgard: Add resets property
From: Neil Armstrong The Amlogic ARM Mali Midgard requires reset controls to power on and software reset the GPU, adds these as optional in the bindings. Signed-off-by: Neil Armstrong Reviewed-by: Rob Herring Signed-off-by: Kevin Hilman --- .../devicetree/bindings/gpu/arm,mali-midgard.txt | 14 ++ 1 file changed, 14 insertions(+) diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt index 18a2cde2e5f3..1b1a74129141 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt +++ b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt @@ -37,6 +37,20 @@ Optional properties: - operating-points-v2 : Refer to Documentation/devicetree/bindings/opp/opp.txt for details. +- resets : Phandle of the GPU reset line. + +Vendor-specific bindings + + +The Mali GPU is integrated very differently from one SoC to +another. In order to accomodate those differences, you have the option +to specify one more vendor-specific compatible, among: + +- "amlogic,meson-gxm-mali" + Required properties: + - resets : Should contain phandles of : ++ GPU reset line ++ GPU APB glue reset line Example for a Mali-T760: -- 2.17.1 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v2 0/8] Add Allwinner H6 Mali Midgard GPU
Hi, On Thu, 11 Apr 2019 at 17:01, Jernej Škrabec wrote: > > Hi! > > Dne četrtek, 11. april 2019 ob 14:32:23 CEST je Maxime Ripard napisal(a): > > On Thu, Apr 11, 2019 at 12:57:12PM +0200, Clément Péron wrote: > > > Hi, > > > > > > The Allwinner H6 has a Mali-T720 MP2. The drivers are > > > out-of-tree so this series only introduce the dt-bindings. > > > > > > The first patch is from Neil Amstrong and has been already > > > merged in linux-amlogic. It is required for this series. > > > > > > The second patch is from Icenowy Zheng where I changed the > > > order has required by Rob Herring. > > > See: https://patchwork.kernel.org/patch/10699829/ > > > > > > The GPU opp table was taken from Jernej Škrabec's patch > > > on LibreELEC.tv. > > > > One valuable information here would be which stack did you use, > > panfrost and mesa or the ARM stack? If so, with which driver and which > > blob? All of this work has be done by Jernej so he could answer better than me. He uses the ARM stack r22p0-01rel0 + patches https://github.com/LibreELEC/LibreELEC.tv/commit/5273f889964c42e88fe02289290c3c6cb6086770 Blob are also from Jernej too (taken from ???) : https://github.com/jernejsk/H6-mali-userspace Regards, Clement > > I'm using similar binding (different clock and interrupt names, but otherwise > same) for quiet some time now on LibreELEC with ARM proprietary userspace and > kernel space driver (32-bit GBM version) and it works well. > > It's true that I'm using OPP table, but most (if not all) of the time GPU is > set to lowest setting as there is not much to do when rendering GUI. > > Best regards, > Jernej > > ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v2 3/8] dt-bindings: gpu: mali-midgard: Add h6 mali gpu compatible
This add the H6 mali compatible in the dt-bindings to later support specific implementation. Signed-off-by: Clément Péron --- .../devicetree/bindings/gpu/arm,mali-midgard.txt | 9 - 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt index 2e8bbce35695..ec4a9f44 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt +++ b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt @@ -15,6 +15,7 @@ Required properties: + "arm,mali-t860" + "arm,mali-t880" * which must be preceded by one of the following vendor specifics: ++ "allwinner,sun50i-h6-mali" + "amlogic,meson-gxm-mali" + "rockchip,rk3288-mali" + "rockchip,rk3399-mali" @@ -49,9 +50,15 @@ Vendor-specific bindings The Mali GPU is integrated very differently from one SoC to -another. In order to accomodate those differences, you have the option +another. In order to accommodate those differences, you have the option to specify one more vendor-specific compatible, among: +- "allwinner,sun50i-h6-mali" + Required properties: + - clocks : phandles to core and bus clocks + - clock-names : must contain "core" and "bus" + - resets: phandle to GPU reset line + - "amlogic,meson-gxm-mali" Required properties: - resets : Should contain phandles of : -- 2.17.1 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v2 2/8] dt-bindings: gpu: add bus clock for Mali Midgard GPUs
Some SoCs adds a bus clock gate to the Mali Midgard GPU. Add the binding for the bus clock. Signed-off-by: Icenowy Zheng Signed-off-by: Clément Péron --- Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt | 6 ++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt index 1b1a74129141..2e8bbce35695 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt +++ b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt @@ -31,6 +31,12 @@ Optional properties: - clocks : Phandle to clock for the Mali Midgard device. +- clock-names : Specify the names of the clocks specified in clocks + when multiple clocks are present. +* core: clock driving the GPU itself (When only one clock is present, + assume it's this clock.) +* bus: bus clock for the GPU + - mali-supply : Phandle to regulator for the Mali device. Refer to Documentation/devicetree/bindings/regulator/regulator.txt for details. -- 2.17.1 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v2 5/8] arm64: dts: allwinner: Add mali GPU supply for Pine H64
Enable and add supply to the Mali GPU node on the
Pine H64 board.
Signed-off-by: Clément Péron
---
arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
index 4802902e128f..e16a8c6738f9 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
@@ -85,6 +85,11 @@
status = "okay";
};
+ {
+ mali-supply = <_dcdcc>;
+ status = "okay";
+};
+
{
status = "okay";
};
--
2.17.1
___
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[PATCH v5 4/6] dt-bindings: gpu: mali-midgard: Add H6 mali gpu compatible
This add the H6 mali compatible in the dt-bindings to later support specific implementation. Signed-off-by: Clément Péron Reviewed-by: Rob Herring --- .../devicetree/bindings/gpu/arm,mali-midgard.txt | 9 - 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt index 2e8bbce35695..4bf17e1cf555 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt +++ b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt @@ -15,6 +15,7 @@ Required properties: + "arm,mali-t860" + "arm,mali-t880" * which must be preceded by one of the following vendor specifics: ++ "allwinner,sun50i-h6-mali" + "amlogic,meson-gxm-mali" + "rockchip,rk3288-mali" + "rockchip,rk3399-mali" @@ -49,9 +50,15 @@ Vendor-specific bindings The Mali GPU is integrated very differently from one SoC to -another. In order to accomodate those differences, you have the option +another. In order to accommodate those differences, you have the option to specify one more vendor-specific compatible, among: +- "allwinner,sun50i-h6-mali" + Required properties: + - clocks : phandles to core and bus clocks + - clock-names : must contain "core" and "bus" + - resets: phandle to GPU reset line + - "amlogic,meson-gxm-mali" Required properties: - resets : Should contain phandles of : -- 2.17.1
[PATCH v5 1/6] drm: panfrost: add optional bus_clock
Allwinner H6 has an ARM Mali-T720 MP2 which required a bus_clock.
Add an optional bus_clock at the init of the panfrost driver.
Signed-off-by: Clément Péron
---
drivers/gpu/drm/panfrost/panfrost_device.c | 25 +-
drivers/gpu/drm/panfrost/panfrost_device.h | 1 +
2 files changed, 25 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/panfrost/panfrost_device.c
b/drivers/gpu/drm/panfrost/panfrost_device.c
index 3b2bced1b015..8da6e612d384 100644
--- a/drivers/gpu/drm/panfrost/panfrost_device.c
+++ b/drivers/gpu/drm/panfrost/panfrost_device.c
@@ -44,7 +44,8 @@ static int panfrost_clk_init(struct panfrost_device *pfdev)
pfdev->clock = devm_clk_get(pfdev->dev, NULL);
if (IS_ERR(pfdev->clock)) {
- dev_err(pfdev->dev, "get clock failed %ld\n",
PTR_ERR(pfdev->clock));
+ dev_err(pfdev->dev, "get clock failed %ld\n",
+ PTR_ERR(pfdev->clock));
return PTR_ERR(pfdev->clock);
}
@@ -55,11 +56,33 @@ static int panfrost_clk_init(struct panfrost_device *pfdev)
if (err)
return err;
+ pfdev->bus_clock = devm_clk_get_optional(pfdev->dev, "bus");
+ if (IS_ERR(pfdev->bus_clock)) {
+ dev_err(pfdev->dev, "get bus_clock failed %ld\n",
+ PTR_ERR(pfdev->bus_clock));
+ return PTR_ERR(pfdev->bus_clock);
+ }
+
+ if (pfdev->bus_clock) {
+ rate = clk_get_rate(pfdev->bus_clock);
+ dev_info(pfdev->dev, "bus_clock rate = %lu\n", rate);
+
+ err = clk_prepare_enable(pfdev->bus_clock);
+ if (err)
+ goto disable_clock;
+ }
+
return 0;
+
+disable_clock:
+ clk_disable_unprepare(pfdev->clock);
+
+ return err;
}
static void panfrost_clk_fini(struct panfrost_device *pfdev)
{
+ clk_disable_unprepare(pfdev->bus_clock);
clk_disable_unprepare(pfdev->clock);
}
diff --git a/drivers/gpu/drm/panfrost/panfrost_device.h
b/drivers/gpu/drm/panfrost/panfrost_device.h
index 56f452dfb490..8074f221034b 100644
--- a/drivers/gpu/drm/panfrost/panfrost_device.h
+++ b/drivers/gpu/drm/panfrost/panfrost_device.h
@@ -66,6 +66,7 @@ struct panfrost_device {
void __iomem *iomem;
struct clk *clock;
+ struct clk *bus_clock;
struct regulator *regulator;
struct reset_control *rstc;
--
2.17.1
[PATCH v5 3/6] dt-bindings: gpu: add bus clock for Mali Midgard GPUs
From: Icenowy Zheng Some SoCs adds a bus clock gate to the Mali Midgard GPU. Add the binding for the bus clock. Signed-off-by: Icenowy Zheng Signed-off-by: Clément Péron Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt | 6 ++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt index 1b1a74129141..2e8bbce35695 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt +++ b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt @@ -31,6 +31,12 @@ Optional properties: - clocks : Phandle to clock for the Mali Midgard device. +- clock-names : Specify the names of the clocks specified in clocks + when multiple clocks are present. +* core: clock driving the GPU itself (When only one clock is present, + assume it's this clock.) +* bus: bus clock for the GPU + - mali-supply : Phandle to regulator for the Mali device. Refer to Documentation/devicetree/bindings/regulator/regulator.txt for details. -- 2.17.1
[PATCH v5 6/6] arm64: dts: allwinner: Add mali GPU supply for H6 boards
Enable and add supply to the Mali GPU node on all the
H6 boards.
Regarding the datasheet the maximum time for supply to reach
its voltage is 32ms.
Signed-off-by: Clément Péron
---
arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts | 6 ++
arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts | 6 ++
arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi | 6 ++
arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts| 6 ++
4 files changed, 24 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
index 0dc33c90dd60..fe36c6588d8e 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
@@ -70,6 +70,11 @@
status = "okay";
};
+ {
+ mali-supply = <_dcdcc>;
+ status = "okay";
+};
+
{
status = "okay";
};
@@ -206,6 +211,7 @@
};
reg_dcdcc: dcdcc {
+ regulator-enable-ramp-delay = <32000>;
regulator-min-microvolt = <81>;
regulator-max-microvolt = <108>;
regulator-name = "vdd-gpu";
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
index 17d496990108..ea4866b0fa7a 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
@@ -58,6 +58,11 @@
status = "okay";
};
+ {
+ mali-supply = <_dcdcc>;
+ status = "okay";
+};
+
{
vmmc-supply = <_cldo1>;
cd-gpios = < 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
@@ -165,6 +170,7 @@
};
reg_dcdcc: dcdcc {
+ regulator-enable-ramp-delay = <32000>;
regulator-min-microvolt = <81>;
regulator-max-microvolt = <108>;
regulator-name = "vdd-gpu";
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
index 62e27948a3fa..ec770f07aa82 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
@@ -55,6 +55,11 @@
status = "okay";
};
+ {
+ mali-supply = <_dcdcc>;
+ status = "okay";
+};
+
{
vmmc-supply = <_cldo1>;
cd-gpios = < 5 6 GPIO_ACTIVE_LOW>;
@@ -163,6 +168,7 @@
};
reg_dcdcc: dcdcc {
+ regulator-enable-ramp-delay = <32000>;
regulator-min-microvolt = <81>;
regulator-max-microvolt = <108>;
regulator-name = "vdd-gpu";
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
index 4802902e128f..625a29a25c52 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
@@ -85,6 +85,11 @@
status = "okay";
};
+ {
+ mali-supply = <_dcdcc>;
+ status = "okay";
+};
+
{
status = "okay";
};
@@ -215,6 +220,7 @@
};
reg_dcdcc: dcdcc {
+ regulator-enable-ramp-delay = <32000>;
regulator-min-microvolt = <81>;
regulator-max-microvolt = <108>;
regulator-name = "vdd-gpu";
--
2.17.1
[PATCH v5 0/6] Allwinner H6 Mali GPU support
Hi, The Allwinner H6 has a Mali-T720 MP2 which should be supported by the new panfrost driver. This series fix two issues and introduce the dt-bindings but a simple benchmark show that it's still NOT WORKING. I'm pushing it in case someone want to continue the work. This has been tested with Mesa3D 19.1.0-RC2 and a GPU bitness patch[1]. One patch is from Icenowy Zheng where I changed the order has required by Rob Herring[2]. Thanks, Clement [1] https://gitlab.freedesktop.org/kszaq/mesa/tree/panfrost_64_32 [2] https://patchwork.kernel.org/patch/10699829/ [ 345.204813] panfrost 180.gpu: mmu irq status=1 [ 345.209617] panfrost 180.gpu: Unhandled Page fault in AS0 at VA 0x02400400 [ 345.209617] Reason: TODO [ 345.209617] raw fault status: 0x82C1 [ 345.209617] decoded fault status: SLAVE FAULT [ 345.209617] exception type 0xC1: TRANSLATION_FAULT_LEVEL1 [ 345.209617] access type 0x2: READ [ 345.209617] source id 0x8000 [ 345.729957] panfrost 180.gpu: gpu sched timeout, js=0, status=0x8, head=0x2400400, tail=0x2400400, sched_job=9e204de9 [ 346.055876] panfrost 180.gpu: mmu irq status=1 [ 346.060680] panfrost 180.gpu: Unhandled Page fault in AS0 at VA 0x02C00A00 [ 346.060680] Reason: TODO [ 346.060680] raw fault status: 0x810002C1 [ 346.060680] decoded fault status: SLAVE FAULT [ 346.060680] exception type 0xC1: TRANSLATION_FAULT_LEVEL1 [ 346.060680] access type 0x2: READ [ 346.060680] source id 0x8100 [ 346.561955] panfrost 180.gpu: gpu sched timeout, js=1, status=0x8, head=0x2c00a00, tail=0x2c00a00, sched_job=b55a9a85 [ 346.573913] panfrost 180.gpu: mmu irq status=1 [ 346.578707] panfrost 180.gpu: Unhandled Page fault in AS0 at VA 0x02C00B80 Changes in v4: - Add bus_clock probe - Fix sanity check in io-pgtable - Add vramp-delay - Merge all boards into one patch - Remove upstreamed Neil A. patch Changes in v3 (Thanks to Maxime Ripard): - Reauthor Icenowy for her path Changes in v2 (Thanks to Maxime Ripard): - Drop GPU OPP Table - Add clocks and clock-names in required Clément Péron (5): drm: panfrost: add optional bus_clock iommu: io-pgtable: fix sanity check for non 48-bit mali iommu dt-bindings: gpu: mali-midgard: Add H6 mali gpu compatible arm64: dts: allwinner: Add ARM Mali GPU node for H6 arm64: dts: allwinner: Add mali GPU supply for H6 boards Icenowy Zheng (1): dt-bindings: gpu: add bus clock for Mali Midgard GPUs .../bindings/gpu/arm,mali-midgard.txt | 15 ++- .../dts/allwinner/sun50i-h6-beelink-gs1.dts | 6 + .../dts/allwinner/sun50i-h6-orangepi-3.dts| 6 + .../dts/allwinner/sun50i-h6-orangepi.dtsi | 6 + .../boot/dts/allwinner/sun50i-h6-pine-h64.dts | 6 + arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 14 +++ drivers/gpu/drm/panfrost/panfrost_device.c| 25 ++- drivers/gpu/drm/panfrost/panfrost_device.h| 1 + drivers/iommu/io-pgtable-arm.c| 2 +- 9 files changed, 78 insertions(+), 3 deletions(-) -- 2.17.1
[PATCH v5 5/6] arm64: dts: allwinner: Add ARM Mali GPU node for H6
Add the mali gpu node to the H6 device-tree.
Signed-off-by: Clément Péron
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index 16c5c3d0fd81..6aad06095c40 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -157,6 +157,20 @@
allwinner,sram = <_sram 1>;
};
+ gpu: gpu@180 {
+ compatible = "allwinner,sun50i-h6-mali",
+"arm,mali-t720";
+ reg = <0x0180 0x4000>;
+ interrupts = ,
+,
+;
+ interrupt-names = "job", "mmu", "gpu";
+ clocks = < CLK_GPU>, < CLK_BUS_GPU>;
+ clock-names = "core", "bus";
+ resets = < RST_BUS_GPU>;
+ status = "disabled";
+ };
+
syscon: syscon@300 {
compatible = "allwinner,sun50i-h6-system-control",
"allwinner,sun50i-a64-system-control";
--
2.17.1
[PATCH v5 2/6] iommu: io-pgtable: fix sanity check for non 48-bit mali iommu
Allwinner H6 SoC has a Mali T720MP2 with a 33-bit iommu which
trig the sanity check during the alloc of the pgtable.
Change the sanity check to allow non 48-bit configuration.
Suggested-by: Robin Murphy
Signed-off-by: Clément Péron
---
drivers/iommu/io-pgtable-arm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/io-pgtable-arm.c
index 4e21efbc4459..74f2ce802e6f 100644
--- a/drivers/iommu/io-pgtable-arm.c
+++ b/drivers/iommu/io-pgtable-arm.c
@@ -1016,7 +1016,7 @@ arm_mali_lpae_alloc_pgtable(struct io_pgtable_cfg *cfg,
void *cookie)
{
struct io_pgtable *iop;
- if (cfg->ias != 48 || cfg->oas > 40)
+ if (cfg->ias > 48 || cfg->oas > 40)
return NULL;
cfg->pgsize_bitmap &= (SZ_4K | SZ_2M | SZ_1G);
--
2.17.1
Re: [PATCH v5 1/6] drm: panfrost: add optional bus_clock
Hi Rob,
On Fri, 17 May 2019 at 22:07, Rob Herring wrote:
>
> On Fri, May 17, 2019 at 1:47 PM Clément Péron wrote:
> >
> > Allwinner H6 has an ARM Mali-T720 MP2 which required a bus_clock.
> >
> > Add an optional bus_clock at the init of the panfrost driver.
> >
> > Signed-off-by: Clément Péron
> > ---
> > drivers/gpu/drm/panfrost/panfrost_device.c | 25 +-
> > drivers/gpu/drm/panfrost/panfrost_device.h | 1 +
> > 2 files changed, 25 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/panfrost/panfrost_device.c
> > b/drivers/gpu/drm/panfrost/panfrost_device.c
> > index 3b2bced1b015..8da6e612d384 100644
> > --- a/drivers/gpu/drm/panfrost/panfrost_device.c
> > +++ b/drivers/gpu/drm/panfrost/panfrost_device.c
> > @@ -44,7 +44,8 @@ static int panfrost_clk_init(struct panfrost_device
> > *pfdev)
> >
> > pfdev->clock = devm_clk_get(pfdev->dev, NULL);
> > if (IS_ERR(pfdev->clock)) {
> > - dev_err(pfdev->dev, "get clock failed %ld\n",
> > PTR_ERR(pfdev->clock));
> > + dev_err(pfdev->dev, "get clock failed %ld\n",
> > + PTR_ERR(pfdev->clock));
>
> Please drop this whitespace change.
Sorry, I thought it was only a mistake here, I will drop it.
Why are they so many lines over 80 characters?
Is there a specific coding style to follow ?
Thanks,
Clement
>
> > return PTR_ERR(pfdev->clock);
> > }
> >
Re: [PATCH v6 0/6] Allwinner H6 Mali GPU support
Hi Rob, On Wed, 22 May 2019 at 21:27, Rob Herring wrote: > > On Tue, May 21, 2019 at 11:11 AM Clément Péron wrote: > > > > Hi, > > > > The Allwinner H6 has a Mali-T720 MP2 which should be supported by > > the new panfrost driver. This series fix two issues and introduce the > > dt-bindings but a simple benchmark show that it's still NOT WORKING. > > > > I'm pushing it in case someone want to continue the work. > > > > This has been tested with Mesa3D 19.1.0-RC2 and a GPU bitness patch[1]. > > > > One patch is from Icenowy Zheng where I changed the order as required > > by Rob Herring[2]. > > > > Thanks, > > Clement > > > > [1] https://gitlab.freedesktop.org/kszaq/mesa/tree/panfrost_64_32 > > [2] https://patchwork.kernel.org/patch/10699829/ > > > > > > [ 345.204813] panfrost 180.gpu: mmu irq status=1 > > [ 345.209617] panfrost 180.gpu: Unhandled Page fault in AS0 at VA > > 0x02400400 > > [ 345.209617] Reason: TODO > > [ 345.209617] raw fault status: 0x82C1 > > [ 345.209617] decoded fault status: SLAVE FAULT > > [ 345.209617] exception type 0xC1: TRANSLATION_FAULT_LEVEL1 > > [ 345.209617] access type 0x2: READ > > [ 345.209617] source id 0x8000 > > [ 345.729957] panfrost 180.gpu: gpu sched timeout, js=0, > > status=0x8, head=0x2400400, tail=0x2400400, sched_job=9e204de9 > > [ 346.055876] panfrost 180.gpu: mmu irq status=1 > > [ 346.060680] panfrost 180.gpu: Unhandled Page fault in AS0 at VA > > 0x02C00A00 > > [ 346.060680] Reason: TODO > > [ 346.060680] raw fault status: 0x810002C1 > > [ 346.060680] decoded fault status: SLAVE FAULT > > [ 346.060680] exception type 0xC1: TRANSLATION_FAULT_LEVEL1 > > [ 346.060680] access type 0x2: READ > > [ 346.060680] source id 0x8100 > > [ 346.561955] panfrost 180.gpu: gpu sched timeout, js=1, > > status=0x8, head=0x2c00a00, tail=0x2c00a00, sched_job=b55a9a85 > > [ 346.573913] panfrost 180.gpu: mmu irq status=1 > > [ 346.578707] panfrost 180.gpu: Unhandled Page fault in AS0 at VA > > 0x02C00B80 > > > > Change in v5: > > - Remove fix indent > > > > Changes in v4: > > - Add bus_clock probe > > - Fix sanity check in io-pgtable > > - Add vramp-delay > > - Merge all boards into one patch > > - Remove upstreamed Neil A. patch > > > > Change in v3 (Thanks to Maxime Ripard): > > - Reauthor Icenowy for her path > > > > Changes in v2 (Thanks to Maxime Ripard): > > - Drop GPU OPP Table > > - Add clocks and clock-names in required > > > > Clément Péron (5): > > drm: panfrost: add optional bus_clock > > iommu: io-pgtable: fix sanity check for non 48-bit mali iommu > > dt-bindings: gpu: mali-midgard: Add H6 mali gpu compatible > > arm64: dts: allwinner: Add ARM Mali GPU node for H6 > > arm64: dts: allwinner: Add mali GPU supply for H6 boards > > > > Icenowy Zheng (1): > > dt-bindings: gpu: add bus clock for Mali Midgard GPUs > > I've applied patches 1 and 3 to drm-misc. I was going to do patch 4 > too, but it doesn't apply. Thanks, I have tried to applied on drm-misc/for-linux-next but it doesn't apply too. It looks like commit d5ff1adb3809e2f74a3b57cea2e57c8e37d693c4 is missing on drm-misc ? https://github.com/torvalds/linux/commit/d5ff1adb3809e2f74a3b57cea2e57c8e37d693c4#diff-c3172f5d421d492ff91d7bb44dd44917 Clément > > Patch 2 can go in via the iommu tree and the rest via the allwinner tree. > > Rob ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: Panfrost impossible to probe without opp table
Hi Tomeu, On Tue, 4 Jun 2019 at 09:09, Tomeu Vizoso wrote: > > On Mon, 3 Jun 2019 at 19:24, Clément Péron wrote: > > > > Hi, > > > > > > On Fri, 31 May 2019 at 14:13, Neil Armstrong > > wrote: > > > > > > On 31/05/2019 14:09, Tomeu Vizoso wrote: > > > > On Fri, 31 May 2019 at 14:03, Neil Armstrong > > > > wrote: > > > >> > > > >> Hi Tomeu, > > > >> > > > >> On 31/05/2019 13:59, Tomeu Vizoso wrote: > > > >>> On Wed, 29 May 2019 at 23:29, Clément Péron > > > >>> wrote: > > > >>>> > > > >>>> Hi, > > > >>>> > > > >>>> I have rebase my kernel on latest 5.2-rc2, and my panfrost driver is > > > >>>> no more probing. > > > >>>> > > > >>>> The issue is coming from f3617b449d0bcf3b5d80a97f51498dcf7463cf7e > > > >>>> drm/panfrost: Select devfreq > > > >>>> > > > >>>> Currently, there is some logic for the driver to work without > > > >>>> devfreq. > > > >>>> However, the driver actually fails to probe if > > > >>>> !CONFIG_PM_DEVFREQ. > > > >>>> > > > >>>> Fix this by selecting devfreq, and drop the additional checks > > > >>>> for devfreq. > > > >>>> > > > >>>> It seems that with this commit the OPP table is now mandatory. > > > >>>> is it intentional? > > > >>> > > > >>> Hi Clément, > > > >>> > > > >>> devfreq support is intentionally required. I got a H64 board which I'm > > > >>> using to add T720 support to Panfrost. > > > >> > > > >> operating-points-v2 and clocks are optional, devfreq should be > > > >> optional, > > > >> this was the default behaviour of the first applied version. > > > > > > > > I'm concerned by the safety of running these GPUs all the time at > > > > their maximum frequencies. Maybe not on Chromebooks and other consumer > > > > devices, but the SBCs I have here have all very crappy heat > > > > dissipation. > > > > > > Sure, it's logical to have devfreq running on these devices. > > > > > > > > > > >> Amlogic dt does not have operating-points-v2, and devfreq won't be > > > >> supported > > > >> soon. > > > > > > > > What's the problem with coming up with the operating points? > > > > > > Because the bindings are optional : > > > Optional properties: > > > > > > - clocks : Phandle to clock for the Mali Midgard device. > > > > > > - mali-supply : Phandle to regulator for the Mali device. Refer to > > > Documentation/devicetree/bindings/regulator/regulator.txt for details. > > > > > > - operating-points-v2 : Refer to > > > Documentation/devicetree/bindings/opp/opp.txt > > > for details. > > > > > > Unless you change the bindings, it's mandated to be optional by the > > > bindings. > > > > I can propose a patch to fix this but what is the best solution? > > > > Leave DEVFREQ config mandatory but allow to probe without opp_table? > > Revert the commit? > > Fix the documentation to have opp table mandatory? > > Hi Clément, > > Neil has a patch on its way to keep DEVFREQ compulsory at build time, > but have it disabled at runtime if we don't have a OPP table. Thanks, Clément > > Cheers, > > Tomeu > > > Thanks, > > Clément > > > > > > > > Neil > > > > > > > > > > > > > > Thanks, > > > > > > > > Tomeu > > > > > > > >> Neil > > > >> > > > >>> > > > >>> Once I'm able to test the GPU properly along with frequency scaling, I > > > >>> will ping you so you can retest and resubmit. > > > >>> > > > >>> Thanks, > > > >>> > > > >>> Tomeu > > > >>> > > > >>>> Actually > > > >>>> [3.046237] panfrost 180.gpu: clock rate = 43200 > > > >>>> [3.051593]
Panfrost impossible to probe without opp table
Hi, I have rebase my kernel on latest 5.2-rc2, and my panfrost driver is no more probing. The issue is coming from f3617b449d0bcf3b5d80a97f51498dcf7463cf7e drm/panfrost: Select devfreq Currently, there is some logic for the driver to work without devfreq. However, the driver actually fails to probe if !CONFIG_PM_DEVFREQ. Fix this by selecting devfreq, and drop the additional checks for devfreq. It seems that with this commit the OPP table is now mandatory. is it intentional? Actually [3.046237] panfrost 180.gpu: clock rate = 43200 [3.051593] panfrost 180.gpu: bus_clock rate = 1 [3.096012] panfrost 180.gpu: mali-t720 id 0x720 major 0x1 minor 0x1 status 0x0 [3.103682] panfrost 180.gpu: features: ,10309e40, issues: ,21054400 [3.111789] panfrost 180.gpu: Features: L2:0x07110206 Shader:0x Tiler:0x0809 Mem:0x1 MMU:0x2821 AS:0xf JS:0x7 [3.123435] panfrost 180.gpu: shader_present=0x3 l2_present=0x1 [3.130405] panfrost 180.gpu: Fatal error during devfreq init With commit reverted [3.038236] panfrost 180.gpu: clock rate = 43200 [3.043593] panfrost 180.gpu: bus_clock rate = 1 [3.087994] panfrost 180.gpu: mali-t720 id 0x720 major 0x1 minor 0x1 status 0x0 [3.095658] panfrost 180.gpu: features: ,10309e40, issues: ,21054400 [3.103763] panfrost 180.gpu: Features: L2:0x07110206 Shader:0x Tiler:0x0809 Mem:0x1 MMU:0x2821 AS:0xf JS:0x7 [3.115410] panfrost 180.gpu: shader_present=0x3 l2_present=0x1 [3.122798] [drm] Initialized panfrost 1.0.0 20180908 for 180.gpu on minor 0 Thanks, Clément ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v6 0/6] Allwinner H6 Mali GPU support
Hi Maxime, Joerg, On Wed, 22 May 2019 at 21:27, Rob Herring wrote: > > On Tue, May 21, 2019 at 11:11 AM Clément Péron wrote: > > > > Hi, > > > > The Allwinner H6 has a Mali-T720 MP2 which should be supported by > > the new panfrost driver. This series fix two issues and introduce the > > dt-bindings but a simple benchmark show that it's still NOT WORKING. > > > > I'm pushing it in case someone want to continue the work. > > > > This has been tested with Mesa3D 19.1.0-RC2 and a GPU bitness patch[1]. > > > > One patch is from Icenowy Zheng where I changed the order as required > > by Rob Herring[2]. > > > > Thanks, > > Clement > > > > [1] https://gitlab.freedesktop.org/kszaq/mesa/tree/panfrost_64_32 > > [2] https://patchwork.kernel.org/patch/10699829/ > > > > > > [ 345.204813] panfrost 180.gpu: mmu irq status=1 > > [ 345.209617] panfrost 180.gpu: Unhandled Page fault in AS0 at VA > > 0x02400400 > > [ 345.209617] Reason: TODO > > [ 345.209617] raw fault status: 0x82C1 > > [ 345.209617] decoded fault status: SLAVE FAULT > > [ 345.209617] exception type 0xC1: TRANSLATION_FAULT_LEVEL1 > > [ 345.209617] access type 0x2: READ > > [ 345.209617] source id 0x8000 > > [ 345.729957] panfrost 180.gpu: gpu sched timeout, js=0, > > status=0x8, head=0x2400400, tail=0x2400400, sched_job=9e204de9 > > [ 346.055876] panfrost 180.gpu: mmu irq status=1 > > [ 346.060680] panfrost 180.gpu: Unhandled Page fault in AS0 at VA > > 0x02C00A00 > > [ 346.060680] Reason: TODO > > [ 346.060680] raw fault status: 0x810002C1 > > [ 346.060680] decoded fault status: SLAVE FAULT > > [ 346.060680] exception type 0xC1: TRANSLATION_FAULT_LEVEL1 > > [ 346.060680] access type 0x2: READ > > [ 346.060680] source id 0x8100 > > [ 346.561955] panfrost 180.gpu: gpu sched timeout, js=1, > > status=0x8, head=0x2c00a00, tail=0x2c00a00, sched_job=b55a9a85 > > [ 346.573913] panfrost 180.gpu: mmu irq status=1 > > [ 346.578707] panfrost 180.gpu: Unhandled Page fault in AS0 at VA > > 0x02C00B80 > > > > Change in v5: > > - Remove fix indent > > > > Changes in v4: > > - Add bus_clock probe > > - Fix sanity check in io-pgtable > > - Add vramp-delay > > - Merge all boards into one patch > > - Remove upstreamed Neil A. patch > > > > Change in v3 (Thanks to Maxime Ripard): > > - Reauthor Icenowy for her path > > > > Changes in v2 (Thanks to Maxime Ripard): > > - Drop GPU OPP Table > > - Add clocks and clock-names in required > > > > Clément Péron (5): > > drm: panfrost: add optional bus_clock > > iommu: io-pgtable: fix sanity check for non 48-bit mali iommu > > dt-bindings: gpu: mali-midgard: Add H6 mali gpu compatible > > arm64: dts: allwinner: Add ARM Mali GPU node for H6 > > arm64: dts: allwinner: Add mali GPU supply for H6 boards > > > > Icenowy Zheng (1): > > dt-bindings: gpu: add bus clock for Mali Midgard GPUs > > I've applied patches 1 and 3 to drm-misc. I was going to do patch 4 > too, but it doesn't apply. > > Patch 2 can go in via the iommu tree and the rest via the allwinner tree. Is this OK for you to pick up this series? Thanks, Clément > > Rob
Re: Panfrost impossible to probe without opp table
Hi, On Fri, 31 May 2019 at 14:13, Neil Armstrong wrote: > > On 31/05/2019 14:09, Tomeu Vizoso wrote: > > On Fri, 31 May 2019 at 14:03, Neil Armstrong > > wrote: > >> > >> Hi Tomeu, > >> > >> On 31/05/2019 13:59, Tomeu Vizoso wrote: > >>> On Wed, 29 May 2019 at 23:29, Clément Péron wrote: > >>>> > >>>> Hi, > >>>> > >>>> I have rebase my kernel on latest 5.2-rc2, and my panfrost driver is > >>>> no more probing. > >>>> > >>>> The issue is coming from f3617b449d0bcf3b5d80a97f51498dcf7463cf7e > >>>> drm/panfrost: Select devfreq > >>>> > >>>> Currently, there is some logic for the driver to work without > >>>> devfreq. > >>>> However, the driver actually fails to probe if !CONFIG_PM_DEVFREQ. > >>>> > >>>> Fix this by selecting devfreq, and drop the additional checks > >>>> for devfreq. > >>>> > >>>> It seems that with this commit the OPP table is now mandatory. > >>>> is it intentional? > >>> > >>> Hi Clément, > >>> > >>> devfreq support is intentionally required. I got a H64 board which I'm > >>> using to add T720 support to Panfrost. > >> > >> operating-points-v2 and clocks are optional, devfreq should be optional, > >> this was the default behaviour of the first applied version. > > > > I'm concerned by the safety of running these GPUs all the time at > > their maximum frequencies. Maybe not on Chromebooks and other consumer > > devices, but the SBCs I have here have all very crappy heat > > dissipation. > > Sure, it's logical to have devfreq running on these devices. > > > > >> Amlogic dt does not have operating-points-v2, and devfreq won't be > >> supported > >> soon. > > > > What's the problem with coming up with the operating points? > > Because the bindings are optional : > Optional properties: > > - clocks : Phandle to clock for the Mali Midgard device. > > - mali-supply : Phandle to regulator for the Mali device. Refer to > Documentation/devicetree/bindings/regulator/regulator.txt for details. > > - operating-points-v2 : Refer to Documentation/devicetree/bindings/opp/opp.txt > for details. > > Unless you change the bindings, it's mandated to be optional by the bindings. I can propose a patch to fix this but what is the best solution? Leave DEVFREQ config mandatory but allow to probe without opp_table? Revert the commit? Fix the documentation to have opp table mandatory? Thanks, Clément > > Neil > > > > > > Thanks, > > > > Tomeu > > > >> Neil > >> > >>> > >>> Once I'm able to test the GPU properly along with frequency scaling, I > >>> will ping you so you can retest and resubmit. > >>> > >>> Thanks, > >>> > >>> Tomeu > >>> > >>>> Actually > >>>> [3.046237] panfrost 180.gpu: clock rate = 43200 > >>>> [3.051593] panfrost 180.gpu: bus_clock rate = 1 > >>>> [3.096012] panfrost 180.gpu: mali-t720 id 0x720 major 0x1 > >>>> minor 0x1 status 0x0 > >>>> [3.103682] panfrost 180.gpu: features: ,10309e40, > >>>> issues: ,21054400 > >>>> [3.111789] panfrost 180.gpu: Features: L2:0x07110206 > >>>> Shader:0x Tiler:0x0809 Mem:0x1 MMU:0x2821 AS:0xf > >>>> JS:0x7 > >>>> [3.123435] panfrost 180.gpu: shader_present=0x3 l2_present=0x1 > >>>> [3.130405] panfrost 180.gpu: Fatal error during devfreq init > >>>> > >>>> With commit reverted > >>>> [3.038236] panfrost 180.gpu: clock rate = 43200 > >>>> [3.043593] panfrost 180.gpu: bus_clock rate = 1 > >>>> [3.087994] panfrost 180.gpu: mali-t720 id 0x720 major 0x1 > >>>> minor 0x1 status 0x0 > >>>> [3.095658] panfrost 180.gpu: features: ,10309e40, > >>>> issues: ,21054400 > >>>> [3.103763] panfrost 180.gpu: Features: L2:0x07110206 > >>>> Shader:0x Tiler:0x0809 Mem:0x1 MMU:0x2821 AS:0xf > >>>> JS:0x7 > >>>> [3.115410] panfrost 180.gpu: shader_present=0x3 l2_present=0x1 > >>>> [3.122798] [drm] Initialized panfrost 1.0.0 20180908 for > >>>> 180.gpu on minor 0 > >>>> > >>>> > >>>> Thanks, > >>>> Clément > >>>> > >>>> ___ > >>>> linux-arm-kernel mailing list > >>>> linux-arm-ker...@lists.infradead.org > >>>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel > >>> ___ > >>> dri-devel mailing list > >>> dri-devel@lists.freedesktop.org > >>> https://lists.freedesktop.org/mailman/listinfo/dri-devel > >>> > >> > >> ___ > >> dri-devel mailing list > >> dri-devel@lists.freedesktop.org > >> https://lists.freedesktop.org/mailman/listinfo/dri-devel > ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v4 0/8] Allwinner H6 Mali GPU support
Hi, On Tue, 14 May 2019 at 17:17, Clément Péron wrote: > > Hi, > > On Tue, 14 May 2019 at 12:29, Neil Armstrong wrote: > > > > Hi, > > > > On 13/05/2019 17:14, Daniel Vetter wrote: > > > On Sun, May 12, 2019 at 07:46:00PM +0200, peron.c...@gmail.com wrote: > > >> From: Clément Péron > > >> > > >> Hi, > > >> > > >> The Allwinner H6 has a Mali-T720 MP2. The drivers are > > >> out-of-tree so this series only introduce the dt-bindings. > > > > > > We do have an in-tree midgard driver now (since 5.2). Does this stuff work > > > together with your dt changes here? > > > > No, but it should be easy to add. > I will give it a try and let you know. Added the bus_clock and a ramp delay to the gpu_vdd but the driver fail at probe. [3.052919] panfrost 180.gpu: clock rate = 43200 [3.058278] panfrost 180.gpu: bus_clock rate = 1 [3.179772] panfrost 180.gpu: mali-t720 id 0x720 major 0x1 minor 0x1 status 0x0 [3.187432] panfrost 180.gpu: features: ,10309e40, issues: ,21054400 [3.195531] panfrost 180.gpu: Features: L2:0x07110206 Shader:0x Tiler:0x0809 Mem:0x1 MMU:0x2821 AS:0xf JS:0x7 [3.207178] panfrost 180.gpu: shader_present=0x3 l2_present=0x1 [3.238257] panfrost 180.gpu: Fatal error during GPU init [3.244165] panfrost: probe of 180.gpu failed with error -12 The ENOMEM is coming from "panfrost_mmu_init" alloc_io_pgtable_ops(ARM_MALI_LPAE, >mmu->pgtbl_cfg, pfdev); Which is due to a check in the pgtable alloc "cfg->ias != 48" arm-lpae io-pgtable: arm_mali_lpae_alloc_pgtable cfg->ias 33 cfg->oas 40 DRI stack is totally new for me, could you give me a little clue about this issue ? Thanks, Clément > > > > > Clément, no need to resend the first patch, it's now on > > linus master. > Ok > > Thanks, > Clement > > > > > Could you also add support for the bus clock in panfrost > > in the same patchset since it's also on master now ? > > > > Neil > > > > > -Daniel > > > > > >> The first patch is from Neil Amstrong and has been already > > >> merged in linux-amlogic. It is required for this series. > > >> > > >> The second patch is from Icenowy Zheng where I changed the > > >> order has required by Rob Herring. > > >> See: https://patchwork.kernel.org/patch/10699829/ > > >> > > >> Thanks, > > >> Clément > > >> > > >> Changes in v4: > > >> - Add Rob Herring reviewed-by tag > > >> - Resent with correct Maintainers > > >> > > >> Changes in v3 (Thanks to Maxime Ripard): > > >> - Reauthor Icenowy for her patch > > >> > > >> Changes in v2 (Thanks to Maxime Ripard): > > >> - Drop GPU OPP Table > > >> - Add clocks and clock-names in required > > >> > > >> Clément Péron (6): > > >> dt-bindings: gpu: mali-midgard: Add H6 mali gpu compatible > > >> arm64: dts: allwinner: Add ARM Mali GPU node for H6 > > >> arm64: dts: allwinner: Add mali GPU supply for Pine H64 > > >> arm64: dts: allwinner: Add mali GPU supply for Beelink GS1 > > >> arm64: dts: allwinner: Add mali GPU supply for OrangePi Boards > > >> arm64: dts: allwinner: Add mali GPU supply for OrangePi 3 > > >> > > >> Icenowy Zheng (1): > > >> dt-bindings: gpu: add bus clock for Mali Midgard GPUs > > >> > > >> Neil Armstrong (1): > > >> dt-bindings: gpu: mali-midgard: Add resets property > > >> > > >> .../bindings/gpu/arm,mali-midgard.txt | 27 +++ > > >> .../dts/allwinner/sun50i-h6-beelink-gs1.dts | 5 > > >> .../dts/allwinner/sun50i-h6-orangepi-3.dts| 5 > > >> .../dts/allwinner/sun50i-h6-orangepi.dtsi | 5 > > >> .../boot/dts/allwinner/sun50i-h6-pine-h64.dts | 5 > > >> arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 14 ++ > > >> 6 files changed, 61 insertions(+) > > >> > > >> -- > > >> 2.17.1 > > >> > > > > >
Re: [PATCH v4 0/8] Allwinner H6 Mali GPU support
Hi, On Tue, 14 May 2019 at 12:29, Neil Armstrong wrote: > > Hi, > > On 13/05/2019 17:14, Daniel Vetter wrote: > > On Sun, May 12, 2019 at 07:46:00PM +0200, peron.c...@gmail.com wrote: > >> From: Clément Péron > >> > >> Hi, > >> > >> The Allwinner H6 has a Mali-T720 MP2. The drivers are > >> out-of-tree so this series only introduce the dt-bindings. > > > > We do have an in-tree midgard driver now (since 5.2). Does this stuff work > > together with your dt changes here? > > No, but it should be easy to add. I will give it a try and let you know. > > Clément, no need to resend the first patch, it's now on > linus master. Ok Thanks, Clement > > Could you also add support for the bus clock in panfrost > in the same patchset since it's also on master now ? > > Neil > > > -Daniel > > > >> The first patch is from Neil Amstrong and has been already > >> merged in linux-amlogic. It is required for this series. > >> > >> The second patch is from Icenowy Zheng where I changed the > >> order has required by Rob Herring. > >> See: https://patchwork.kernel.org/patch/10699829/ > >> > >> Thanks, > >> Clément > >> > >> Changes in v4: > >> - Add Rob Herring reviewed-by tag > >> - Resent with correct Maintainers > >> > >> Changes in v3 (Thanks to Maxime Ripard): > >> - Reauthor Icenowy for her patch > >> > >> Changes in v2 (Thanks to Maxime Ripard): > >> - Drop GPU OPP Table > >> - Add clocks and clock-names in required > >> > >> Clément Péron (6): > >> dt-bindings: gpu: mali-midgard: Add H6 mali gpu compatible > >> arm64: dts: allwinner: Add ARM Mali GPU node for H6 > >> arm64: dts: allwinner: Add mali GPU supply for Pine H64 > >> arm64: dts: allwinner: Add mali GPU supply for Beelink GS1 > >> arm64: dts: allwinner: Add mali GPU supply for OrangePi Boards > >> arm64: dts: allwinner: Add mali GPU supply for OrangePi 3 > >> > >> Icenowy Zheng (1): > >> dt-bindings: gpu: add bus clock for Mali Midgard GPUs > >> > >> Neil Armstrong (1): > >> dt-bindings: gpu: mali-midgard: Add resets property > >> > >> .../bindings/gpu/arm,mali-midgard.txt | 27 +++ > >> .../dts/allwinner/sun50i-h6-beelink-gs1.dts | 5 > >> .../dts/allwinner/sun50i-h6-orangepi-3.dts| 5 > >> .../dts/allwinner/sun50i-h6-orangepi.dtsi | 5 > >> .../boot/dts/allwinner/sun50i-h6-pine-h64.dts | 5 > >> arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 14 ++ > >> 6 files changed, 61 insertions(+) > >> > >> -- > >> 2.17.1 > >> > > > ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v5 1/6] drm: panfrost: add optional bus_clock
Hi,
On Sat, 18 May 2019 at 00:17, Rob Herring wrote:
>
> On Fri, May 17, 2019 at 5:08 PM Clément Péron wrote:
> >
> > Hi Rob,
> >
> > On Fri, 17 May 2019 at 22:07, Rob Herring wrote:
> > >
> > > On Fri, May 17, 2019 at 1:47 PM Clément Péron
> > > wrote:
> > > >
> > > > Allwinner H6 has an ARM Mali-T720 MP2 which required a bus_clock.
> > > >
> > > > Add an optional bus_clock at the init of the panfrost driver.
> > > >
> > > > Signed-off-by: Clément Péron
> > > > ---
> > > > drivers/gpu/drm/panfrost/panfrost_device.c | 25 +-
> > > > drivers/gpu/drm/panfrost/panfrost_device.h | 1 +
> > > > 2 files changed, 25 insertions(+), 1 deletion(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/panfrost/panfrost_device.c
> > > > b/drivers/gpu/drm/panfrost/panfrost_device.c
> > > > index 3b2bced1b015..8da6e612d384 100644
> > > > --- a/drivers/gpu/drm/panfrost/panfrost_device.c
> > > > +++ b/drivers/gpu/drm/panfrost/panfrost_device.c
> > > > @@ -44,7 +44,8 @@ static int panfrost_clk_init(struct panfrost_device
> > > > *pfdev)
> > > >
> > > > pfdev->clock = devm_clk_get(pfdev->dev, NULL);
> > > > if (IS_ERR(pfdev->clock)) {
> > > > - dev_err(pfdev->dev, "get clock failed %ld\n",
> > > > PTR_ERR(pfdev->clock));
> > > > + dev_err(pfdev->dev, "get clock failed %ld\n",
> > > > + PTR_ERR(pfdev->clock));
> > >
> > > Please drop this whitespace change.
> >
> > Sorry, I thought it was only a mistake here, I will drop it.
> > Why are they so many lines over 80 characters?
>
> I'd guess most are prints and/or just slightly over.
>
> > Is there a specific coding style to follow ?
>
> Yes, but generally the 80 character thing is more a guidance. Not
> having unrelated changes in a single commit is more of a hard rule.
Ok, thanks for the clarification.
Clément
>
> Rob
[PATCH v6 1/6] drm: panfrost: add optional bus_clock
Allwinner H6 has an ARM Mali-T720 MP2 which required a bus_clock.
Add an optional bus_clock at the init of the panfrost driver.
Signed-off-by: Clément Péron
---
drivers/gpu/drm/panfrost/panfrost_device.c | 22 ++
drivers/gpu/drm/panfrost/panfrost_device.h | 1 +
2 files changed, 23 insertions(+)
diff --git a/drivers/gpu/drm/panfrost/panfrost_device.c
b/drivers/gpu/drm/panfrost/panfrost_device.c
index 3b2bced1b015..ccb8eb2a518c 100644
--- a/drivers/gpu/drm/panfrost/panfrost_device.c
+++ b/drivers/gpu/drm/panfrost/panfrost_device.c
@@ -55,11 +55,33 @@ static int panfrost_clk_init(struct panfrost_device *pfdev)
if (err)
return err;
+ pfdev->bus_clock = devm_clk_get_optional(pfdev->dev, "bus");
+ if (IS_ERR(pfdev->bus_clock)) {
+ dev_err(pfdev->dev, "get bus_clock failed %ld\n",
+ PTR_ERR(pfdev->bus_clock));
+ return PTR_ERR(pfdev->bus_clock);
+ }
+
+ if (pfdev->bus_clock) {
+ rate = clk_get_rate(pfdev->bus_clock);
+ dev_info(pfdev->dev, "bus_clock rate = %lu\n", rate);
+
+ err = clk_prepare_enable(pfdev->bus_clock);
+ if (err)
+ goto disable_clock;
+ }
+
return 0;
+
+disable_clock:
+ clk_disable_unprepare(pfdev->clock);
+
+ return err;
}
static void panfrost_clk_fini(struct panfrost_device *pfdev)
{
+ clk_disable_unprepare(pfdev->bus_clock);
clk_disable_unprepare(pfdev->clock);
}
diff --git a/drivers/gpu/drm/panfrost/panfrost_device.h
b/drivers/gpu/drm/panfrost/panfrost_device.h
index 56f452dfb490..8074f221034b 100644
--- a/drivers/gpu/drm/panfrost/panfrost_device.h
+++ b/drivers/gpu/drm/panfrost/panfrost_device.h
@@ -66,6 +66,7 @@ struct panfrost_device {
void __iomem *iomem;
struct clk *clock;
+ struct clk *bus_clock;
struct regulator *regulator;
struct reset_control *rstc;
--
2.17.1
___
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v6 3/6] dt-bindings: gpu: add bus clock for Mali Midgard GPUs
From: Icenowy Zheng Some SoCs adds a bus clock gate to the Mali Midgard GPU. Add the binding for the bus clock. Signed-off-by: Icenowy Zheng Signed-off-by: Clément Péron Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt | 6 ++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt index 1b1a74129141..2e8bbce35695 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt +++ b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt @@ -31,6 +31,12 @@ Optional properties: - clocks : Phandle to clock for the Mali Midgard device. +- clock-names : Specify the names of the clocks specified in clocks + when multiple clocks are present. +* core: clock driving the GPU itself (When only one clock is present, + assume it's this clock.) +* bus: bus clock for the GPU + - mali-supply : Phandle to regulator for the Mali device. Refer to Documentation/devicetree/bindings/regulator/regulator.txt for details. -- 2.17.1 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v6 0/6] Allwinner H6 Mali GPU support
Hi, The Allwinner H6 has a Mali-T720 MP2 which should be supported by the new panfrost driver. This series fix two issues and introduce the dt-bindings but a simple benchmark show that it's still NOT WORKING. I'm pushing it in case someone want to continue the work. This has been tested with Mesa3D 19.1.0-RC2 and a GPU bitness patch[1]. One patch is from Icenowy Zheng where I changed the order as required by Rob Herring[2]. Thanks, Clement [1] https://gitlab.freedesktop.org/kszaq/mesa/tree/panfrost_64_32 [2] https://patchwork.kernel.org/patch/10699829/ [ 345.204813] panfrost 180.gpu: mmu irq status=1 [ 345.209617] panfrost 180.gpu: Unhandled Page fault in AS0 at VA 0x02400400 [ 345.209617] Reason: TODO [ 345.209617] raw fault status: 0x82C1 [ 345.209617] decoded fault status: SLAVE FAULT [ 345.209617] exception type 0xC1: TRANSLATION_FAULT_LEVEL1 [ 345.209617] access type 0x2: READ [ 345.209617] source id 0x8000 [ 345.729957] panfrost 180.gpu: gpu sched timeout, js=0, status=0x8, head=0x2400400, tail=0x2400400, sched_job=9e204de9 [ 346.055876] panfrost 180.gpu: mmu irq status=1 [ 346.060680] panfrost 180.gpu: Unhandled Page fault in AS0 at VA 0x02C00A00 [ 346.060680] Reason: TODO [ 346.060680] raw fault status: 0x810002C1 [ 346.060680] decoded fault status: SLAVE FAULT [ 346.060680] exception type 0xC1: TRANSLATION_FAULT_LEVEL1 [ 346.060680] access type 0x2: READ [ 346.060680] source id 0x8100 [ 346.561955] panfrost 180.gpu: gpu sched timeout, js=1, status=0x8, head=0x2c00a00, tail=0x2c00a00, sched_job=b55a9a85 [ 346.573913] panfrost 180.gpu: mmu irq status=1 [ 346.578707] panfrost 180.gpu: Unhandled Page fault in AS0 at VA 0x02C00B80 Change in v5: - Remove fix indent Changes in v4: - Add bus_clock probe - Fix sanity check in io-pgtable - Add vramp-delay - Merge all boards into one patch - Remove upstreamed Neil A. patch Change in v3 (Thanks to Maxime Ripard): - Reauthor Icenowy for her path Changes in v2 (Thanks to Maxime Ripard): - Drop GPU OPP Table - Add clocks and clock-names in required Clément Péron (5): drm: panfrost: add optional bus_clock iommu: io-pgtable: fix sanity check for non 48-bit mali iommu dt-bindings: gpu: mali-midgard: Add H6 mali gpu compatible arm64: dts: allwinner: Add ARM Mali GPU node for H6 arm64: dts: allwinner: Add mali GPU supply for H6 boards Icenowy Zheng (1): dt-bindings: gpu: add bus clock for Mali Midgard GPUs .../bindings/gpu/arm,mali-midgard.txt | 15 - .../dts/allwinner/sun50i-h6-beelink-gs1.dts | 6 + .../dts/allwinner/sun50i-h6-orangepi-3.dts| 6 + .../dts/allwinner/sun50i-h6-orangepi.dtsi | 6 + .../boot/dts/allwinner/sun50i-h6-pine-h64.dts | 6 + arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 14 drivers/gpu/drm/panfrost/panfrost_device.c| 22 +++ drivers/gpu/drm/panfrost/panfrost_device.h| 1 + drivers/iommu/io-pgtable-arm.c| 2 +- 9 files changed, 76 insertions(+), 2 deletions(-) -- 2.17.1 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v6 4/6] dt-bindings: gpu: mali-midgard: Add H6 mali gpu compatible
This add the H6 mali compatible in the dt-bindings to later support specific implementation. Signed-off-by: Clément Péron Reviewed-by: Rob Herring --- .../devicetree/bindings/gpu/arm,mali-midgard.txt | 9 - 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt index 2e8bbce35695..4bf17e1cf555 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt +++ b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt @@ -15,6 +15,7 @@ Required properties: + "arm,mali-t860" + "arm,mali-t880" * which must be preceded by one of the following vendor specifics: ++ "allwinner,sun50i-h6-mali" + "amlogic,meson-gxm-mali" + "rockchip,rk3288-mali" + "rockchip,rk3399-mali" @@ -49,9 +50,15 @@ Vendor-specific bindings The Mali GPU is integrated very differently from one SoC to -another. In order to accomodate those differences, you have the option +another. In order to accommodate those differences, you have the option to specify one more vendor-specific compatible, among: +- "allwinner,sun50i-h6-mali" + Required properties: + - clocks : phandles to core and bus clocks + - clock-names : must contain "core" and "bus" + - resets: phandle to GPU reset line + - "amlogic,meson-gxm-mali" Required properties: - resets : Should contain phandles of : -- 2.17.1 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v6 5/6] arm64: dts: allwinner: Add ARM Mali GPU node for H6
Add the mali gpu node to the H6 device-tree.
Signed-off-by: Clément Péron
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index 16c5c3d0fd81..6aad06095c40 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -157,6 +157,20 @@
allwinner,sram = <_sram 1>;
};
+ gpu: gpu@180 {
+ compatible = "allwinner,sun50i-h6-mali",
+"arm,mali-t720";
+ reg = <0x0180 0x4000>;
+ interrupts = ,
+,
+;
+ interrupt-names = "job", "mmu", "gpu";
+ clocks = < CLK_GPU>, < CLK_BUS_GPU>;
+ clock-names = "core", "bus";
+ resets = < RST_BUS_GPU>;
+ status = "disabled";
+ };
+
syscon: syscon@300 {
compatible = "allwinner,sun50i-h6-system-control",
"allwinner,sun50i-a64-system-control";
--
2.17.1
[PATCH v6 6/6] arm64: dts: allwinner: Add mali GPU supply for H6 boards
Enable and add supply to the Mali GPU node on all the
H6 boards.
Regarding the datasheet the maximum time for supply to reach
its voltage is 32ms.
Signed-off-by: Clément Péron
---
arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts | 6 ++
arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts | 6 ++
arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi | 6 ++
arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts| 6 ++
4 files changed, 24 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
index 0dc33c90dd60..fe36c6588d8e 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
@@ -70,6 +70,11 @@
status = "okay";
};
+ {
+ mali-supply = <_dcdcc>;
+ status = "okay";
+};
+
{
status = "okay";
};
@@ -206,6 +211,7 @@
};
reg_dcdcc: dcdcc {
+ regulator-enable-ramp-delay = <32000>;
regulator-min-microvolt = <81>;
regulator-max-microvolt = <108>;
regulator-name = "vdd-gpu";
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
index 17d496990108..ea4866b0fa7a 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
@@ -58,6 +58,11 @@
status = "okay";
};
+ {
+ mali-supply = <_dcdcc>;
+ status = "okay";
+};
+
{
vmmc-supply = <_cldo1>;
cd-gpios = < 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
@@ -165,6 +170,7 @@
};
reg_dcdcc: dcdcc {
+ regulator-enable-ramp-delay = <32000>;
regulator-min-microvolt = <81>;
regulator-max-microvolt = <108>;
regulator-name = "vdd-gpu";
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
index 62e27948a3fa..ec770f07aa82 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
@@ -55,6 +55,11 @@
status = "okay";
};
+ {
+ mali-supply = <_dcdcc>;
+ status = "okay";
+};
+
{
vmmc-supply = <_cldo1>;
cd-gpios = < 5 6 GPIO_ACTIVE_LOW>;
@@ -163,6 +168,7 @@
};
reg_dcdcc: dcdcc {
+ regulator-enable-ramp-delay = <32000>;
regulator-min-microvolt = <81>;
regulator-max-microvolt = <108>;
regulator-name = "vdd-gpu";
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
index 4802902e128f..625a29a25c52 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
@@ -85,6 +85,11 @@
status = "okay";
};
+ {
+ mali-supply = <_dcdcc>;
+ status = "okay";
+};
+
{
status = "okay";
};
@@ -215,6 +220,7 @@
};
reg_dcdcc: dcdcc {
+ regulator-enable-ramp-delay = <32000>;
regulator-min-microvolt = <81>;
regulator-max-microvolt = <108>;
regulator-name = "vdd-gpu";
--
2.17.1
[PATCH v6 2/6] iommu: io-pgtable: fix sanity check for non 48-bit mali iommu
Allwinner H6 SoC has a Mali T720MP2 with a 33-bit iommu which
trig the sanity check during the alloc of the pgtable.
Change the sanity check to allow non 48-bit configuration.
Suggested-by: Robin Murphy
Signed-off-by: Clément Péron
---
drivers/iommu/io-pgtable-arm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/io-pgtable-arm.c
index 4e21efbc4459..74f2ce802e6f 100644
--- a/drivers/iommu/io-pgtable-arm.c
+++ b/drivers/iommu/io-pgtable-arm.c
@@ -1016,7 +1016,7 @@ arm_mali_lpae_alloc_pgtable(struct io_pgtable_cfg *cfg,
void *cookie)
{
struct io_pgtable *iop;
- if (cfg->ias != 48 || cfg->oas > 40)
+ if (cfg->ias > 48 || cfg->oas > 40)
return NULL;
cfg->pgsize_bitmap &= (SZ_4K | SZ_2M | SZ_1G);
--
2.17.1
Re: [PATCH v4 0/8] Allwinner H6 Mali GPU support
Hi Robin, On Tue, 14 May 2019 at 23:57, Robin Murphy wrote: > > On 2019-05-14 10:22 pm, Clément Péron wrote: > > Hi, > > > > On Tue, 14 May 2019 at 17:17, Clément Péron wrote: > >> > >> Hi, > >> > >> On Tue, 14 May 2019 at 12:29, Neil Armstrong > >> wrote: > >>> > >>> Hi, > >>> > >>> On 13/05/2019 17:14, Daniel Vetter wrote: > >>>> On Sun, May 12, 2019 at 07:46:00PM +0200, peron.c...@gmail.com wrote: > >>>>> From: Clément Péron > >>>>> > >>>>> Hi, > >>>>> > >>>>> The Allwinner H6 has a Mali-T720 MP2. The drivers are > >>>>> out-of-tree so this series only introduce the dt-bindings. > >>>> > >>>> We do have an in-tree midgard driver now (since 5.2). Does this stuff > >>>> work > >>>> together with your dt changes here? > >>> > >>> No, but it should be easy to add. > >> I will give it a try and let you know. > > Added the bus_clock and a ramp delay to the gpu_vdd but the driver > > fail at probe. > > > > [3.052919] panfrost 180.gpu: clock rate = 43200 > > [3.058278] panfrost 180.gpu: bus_clock rate = 1 > > [3.179772] panfrost 180.gpu: mali-t720 id 0x720 major 0x1 > > minor 0x1 status 0x0 > > [3.187432] panfrost 180.gpu: features: ,10309e40, > > issues: ,21054400 > > [3.195531] panfrost 180.gpu: Features: L2:0x07110206 > > Shader:0x Tiler:0x0809 Mem:0x1 MMU:0x2821 AS:0xf > > JS:0x7 > > [3.207178] panfrost 180.gpu: shader_present=0x3 l2_present=0x1 > > [3.238257] panfrost 180.gpu: Fatal error during GPU init > > [3.244165] panfrost: probe of 180.gpu failed with error -12 > > > > The ENOMEM is coming from "panfrost_mmu_init" > > alloc_io_pgtable_ops(ARM_MALI_LPAE, >mmu->pgtbl_cfg, > > pfdev); > > > > Which is due to a check in the pgtable alloc "cfg->ias != 48" > > arm-lpae io-pgtable: arm_mali_lpae_alloc_pgtable cfg->ias 33 cfg->oas 40 > > > > DRI stack is totally new for me, could you give me a little clue about > > this issue ? > > Heh, this is probably the one bit which doesn't really count as "DRI stack". > > That's merely a somewhat-conservative sanity check - I'm pretty sure it > *should* be fine to change the test to "cfg->ias > 48" (io-pgtable > itself ought to cope). You'll just get to be the first to actually test > a non-48-bit configuration here :) Thanks a lot, the probe seems fine now :) I try to run glmark2 : # glmark2-es2-drm === glmark2 2017.07 === OpenGL Information GL_VENDOR: panfrost GL_RENDERER: panfrost GL_VERSION:OpenGL ES 2.0 Mesa 19.1.0-rc2 === [build] use-vbo=false: But it seems that H6 is not so easy to add :(. [ 345.204813] panfrost 180.gpu: mmu irq status=1 [ 345.209617] panfrost 180.gpu: Unhandled Page fault in AS0 at VA 0x02400400 [ 345.209617] Reason: TODO [ 345.209617] raw fault status: 0x82C1 [ 345.209617] decoded fault status: SLAVE FAULT [ 345.209617] exception type 0xC1: TRANSLATION_FAULT_LEVEL1 [ 345.209617] access type 0x2: READ [ 345.209617] source id 0x8000 [ 345.729957] panfrost 180.gpu: gpu sched timeout, js=0, status=0x8, head=0x2400400, tail=0x2400400, sched_job=9e204de9 [ 346.055876] panfrost 180.gpu: mmu irq status=1 [ 346.060680] panfrost 180.gpu: Unhandled Page fault in AS0 at VA 0x02C00A00 [ 346.060680] Reason: TODO [ 346.060680] raw fault status: 0x810002C1 [ 346.060680] decoded fault status: SLAVE FAULT [ 346.060680] exception type 0xC1: TRANSLATION_FAULT_LEVEL1 [ 346.060680] access type 0x2: READ [ 346.060680] source id 0x8100 [ 346.561955] panfrost 180.gpu: gpu sched timeout, js=1, status=0x8, head=0x2c00a00, tail=0x2c00a00, sched_job=b55a9a85 [ 346.573913] panfrost 180.gpu: mmu irq status=1 [ 346.578707] panfrost 180.gpu: Unhandled Page fault in AS0 at VA 0x02C00B80 [ 346.578707] Reason: TODO [ 346.578707] raw fault status: 0x82C1 [ 346.578707] decoded fault status: SLAVE FAULT [ 346.578707] exception type 0xC1: TRANSLATION_FAULT_LEVEL1 [ 346.578707] access type 0x2: READ [ 346.578707] source id 0x8000 [ 347.073947] panfrost 180.gpu: gpu sched timeout, js=0, status=0x8, head=0x2c00b80, tail=0x2c00b80, sched_job=cf6af8e8 [ 347.104125] panfro
Re: [linux-sunxi] [PATCH v4 5/8] arm64: dts: allwinner: Add mali GPU supply for Pine H64
Hi Jagan, Chen-Yu,
On Tue, 14 May 2019 at 12:18, Chen-Yu Tsai wrote:
>
> On Mon, May 13, 2019 at 2:28 AM Jagan Teki wrote:
> >
> > On Sun, May 12, 2019 at 11:16 PM wrote:
> > >
> > > From: Clément Péron
> > >
> > > Enable and add supply to the Mali GPU node on the
> > > Pine H64 board.
> > >
> > > Signed-off-by: Clément Péron
> > > ---
> > > arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts | 5 +
> > > 1 file changed, 5 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
> > > b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
> > > index 4802902e128f..e16a8c6738f9 100644
> > > --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
> > > +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
> > > @@ -85,6 +85,11 @@
> > > status = "okay";
> > > };
> > >
> > > + {
> > > + mali-supply = <_dcdcc>;
> > > + status = "okay";
> > > +};
> >
> > I think we can squash all these board dts changes into single patch.
>
> Yes. Please do so for all patches with the same changes applied to different
> boards, and authored by the same person.
I thought it was required to have "smallest" patch as possible.
And it's also better for tracking "Tested-by" tag.
I will squash them in the next version.
Thanks,
Clement
>
> ChenYu
[PATCH] drm/panfrost: no need to display probe deferred error
Panfrost driver is shouting an error if the regulator init
return an -EPROBE_DEFFER. This is a not a real error and
it doesn't require to be display.
Check if the error is not an EPROBE_DEFFER before displaying it.
Signed-off-by: Clément Péron
---
drivers/gpu/drm/panfrost/panfrost_device.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/panfrost/panfrost_device.c
b/drivers/gpu/drm/panfrost/panfrost_device.c
index 238fb6d54df4..00cef062c35d 100644
--- a/drivers/gpu/drm/panfrost/panfrost_device.c
+++ b/drivers/gpu/drm/panfrost/panfrost_device.c
@@ -92,7 +92,8 @@ static int panfrost_regulator_init(struct panfrost_device
*pfdev)
pfdev->regulator = devm_regulator_get(pfdev->dev, "mali");
if (IS_ERR(pfdev->regulator)) {
ret = PTR_ERR(pfdev->regulator);
- dev_err(pfdev->dev, "failed to get regulator: %d\n", ret);
+ if (ret != -EPROBE_DEFER)
+ dev_err(pfdev->dev, "failed to get regulator: %d\n",
ret);
return ret;
}
@@ -130,7 +131,8 @@ int panfrost_device_init(struct panfrost_device *pfdev)
err = panfrost_regulator_init(pfdev);
if (err) {
- dev_err(pfdev->dev, "regulator init failed %d\n", err);
+ if (err != -EPROBE_DEFER)
+ dev_err(pfdev->dev, "regulator init failed %d\n", err);
goto err_out0;
}
--
2.20.1
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Re: [PATCH 2/2] drm/panfrost: add devfreq regulator support
Hi Mark, On Tue, 14 Apr 2020 at 20:55, Mark Brown wrote: > > On Tue, Apr 14, 2020 at 08:20:23PM +0200, Clément Péron wrote: > > Hi Liam and Mark, > > You might want to flag stuff like this in the subject line, I very > nearly deleted this without opening it since most of the email I get > about panfrost appears to be coming from me having sent patches rather > than being relevant. Ok will do next time, > > > We are having an issue with Panfrost driver registering two times the > > same regulator and giving an error when trying to create the debugfs > > folder. > > > Could you clarify if it is allowed for a device to register two times > > the same regulator? > > > I check Documentation/power/regulator/regulator.rst but this point is > > not specified. > > We don't actively prevent it and I can't think what other than debugfs > might run into problems (and that's just a warning) but it does seem > like a weird thing to want to do and like it's pointing to some > confusion in your code with two different parts of the device > controlling the same supply independently. What's the use case here? Panfrost first probe clock, reset and regulator in device_init: https://elixir.bootlin.com/linux/v5.7-rc1/source/drivers/gpu/drm/panfrost/panfrost_drv.c#L602 Then it probe for optional devfreq, devfreq will get opp tables and also get regulator again. https://elixir.bootlin.com/linux/v5.7-rc1/source/drivers/gpu/drm/panfrost/panfrost_drv.c#L609 That's can be reworked and Panfrost can only probe regulator if there is no opp-table. But if multiple regulator is not an issue and as each request is logic. The first in device_init assure to enable the regulator and the second in OPP assure the voltage level. Maybe we can just fix this warning? Thanks, Clement ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH 2/2] drm/panfrost: add devfreq regulator support
Hi Liam and Mark,
On Tue, 14 Apr 2020 at 15:10, Steven Price wrote:
>
> Hi Clément,
>
> On 13/04/2020 18:28, Clément Péron wrote:
> > Hi Steven,
> >
> > On Mon, 13 Apr 2020 at 18:35, Clément Péron wrote:
> >>
> >> Hi Steven,
> >>
> >> On Mon, 13 Apr 2020 at 17:55, Steven Price wrote:
> >>>
> >>> On 13/04/2020 15:31, Clément Péron wrote:
> >>>> Hi,
> >>>>
> >>>> On Mon, 13 Apr 2020 at 16:18, Clément Péron wrote:
> >>>>>
> >>>>> Hi Steven,
> >>>>>
> >>>>> On Mon, 13 Apr 2020 at 15:18, Steven Price wrote:
> >>>>>>
> >>>>>> On 11/04/2020 21:06, Clément Péron wrote:
> >>>>>>> OPP table can defined both frequency and voltage.
> >>>>>>>
> >>>>>>> Register the mali regulator if it exist.
> >>>>>>>
> >>>>>>> Signed-off-by: Clément Péron
> >>>>>>> ---
> >>>>>>> drivers/gpu/drm/panfrost/panfrost_devfreq.c | 34
> >>>>>>> ++---
> >>>>>>> drivers/gpu/drm/panfrost/panfrost_device.h | 1 +
> >>>>>>> 2 files changed, 31 insertions(+), 4 deletions(-)
> >>>>>>>
> >>>>>>> diff --git a/drivers/gpu/drm/panfrost/panfrost_devfreq.c
> >>>>>>> b/drivers/gpu/drm/panfrost/panfrost_devfreq.c
> >>>>>>> index 62541f4edd81..2dc8e2355358 100644
> >>>>>>> --- a/drivers/gpu/drm/panfrost/panfrost_devfreq.c
> >>>>>>> +++ b/drivers/gpu/drm/panfrost/panfrost_devfreq.c
> >>>>>>> @@ -78,12 +78,26 @@ int panfrost_devfreq_init(struct panfrost_device
> >>>>>>> *pfdev)
> >>>>>>> struct device *dev = >pdev->dev;
> >>>>>>> struct devfreq *devfreq;
> >>>>>>> struct thermal_cooling_device *cooling;
> >>>>>>> + const char *mali = "mali";
> >>>>>>> + struct opp_table *opp_table = NULL;
> >>>>>>> +
> >>>>>>> + /* Regulator is optional */
> >>>>>>> + opp_table = dev_pm_opp_set_regulators(dev, , 1);
> >>>>>>
> >>>>>> This looks like it applies before 3e1399bccf51 ("drm/panfrost: Add
> >>>>>> support for multiple regulators") which is currently in drm-misc-next
> >>>>>> (and linux-next). You want something more like:
> >>>>>
> >>>>> Thanks for you review, indeed I didn't see that multiple regulators
> >>>>> support has been added.
> >>>>> Will update in v2.
> >>>>>
> >>>>>>
> >>>>>>opp_table = dev_pm_opp_set_regulators(dev,
> >>>>>> pfdev->comp->supply_names,
> >>>>>>
> >>>>>> pfdev->comp->num_supplies);
> >>>>>>
> >>>>>> Otherwise a platform with multiple regulators won't work correctly.
> >>>>>>
> >>>>>> Also running on my firefly (RK3288) board I get the following warning:
> >>>>>>
> >>>>>> debugfs: Directory 'ffa3.gpu-mali' with parent 'vdd_gpu'
> >>>>>> already
> >>>>>> present!
> >
> > I try to reproduce but it can't
Sorry, you're right I have indeed the same issue:
[2.903406] panfrost 180.gpu: Features: L2:0x07110206
Shader:0x Tiler:0x0809 Mem:0x1 MMU:0x2821 AS:0xf
JS:0x7
[2.913297] sunxi-ir 704.ir: initialized sunXi IR driver
[2.919901] panfrost 180.gpu: shader_present=0x3 l2_present=0x1
[2.920497] panfrost 180.gpu: Looking up mali-supply from device tree
[3.036568] vdd-gpu: could not add device link 180.gpu err -17
[3.036580] debugfs: Directory '180.gpu-mali' with parent
'vdd-gpu' already present!
[3.046312] panfrost 180.gpu: [drm:panfrost_devfreq_init
[panfrost]] Failed to register cooling device
[3.056322] [drm] Initialized panfrost 1.1.0 20180908 for
180.gpu on minor 0
> > regulator is mount at :
> > ./regulator/vdd-gpu
> > whereas OPP is mount :
> > ./opp/soc-180.gpu/opp:75600/supply-0/
>
Re: Multiple regulators for one device [was drm/panfrost: add devfreq regulator support]
Hi Robin, On Fri, 17 Apr 2020 at 13:10, Robin Murphy wrote: > > On 2020-04-16 2:42 pm, Steven Price wrote: > [...] > > Perhaps a better approach would be for Panfrost to hand over the struct > > regulator objects it has already got to the OPP framework. I.e. open > > code dev_pm_opp_set_regulators(), but instead of calling > > regulator_get_optional() simply populate the regulators we already have? > > > > The other benefit of that is it would provide a clear hand-over of > > responsibility between Panfrost handling it's own regulators and the OPP > > framework picking up the work. The disadvantage is that Panfrost would > > have to track whether the regulators have been handed over or not. > > Sounds like the most logical thing to do is to shuffle things around so > we start by trying to set up an OPP table, then fall back to explicitly > claiming clocks and regulators if necessary. Then we can easily make the > devfreq decision later in probe based on how that turned out. Ok I will propose a new serie with this behavior, Thanks Clement > > Robin. ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v2 1/2] drm/panfrost: missing remove opp table in case of failure
In case of failure we need to remove OPP table.
Use Linux classic error handling with goto usage.
Reviewed-by: Steven Price
Signed-off-by: Clément Péron
---
drivers/gpu/drm/panfrost/panfrost_devfreq.c | 16
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/panfrost/panfrost_devfreq.c
b/drivers/gpu/drm/panfrost/panfrost_devfreq.c
index 413987038fbf..62541f4edd81 100644
--- a/drivers/gpu/drm/panfrost/panfrost_devfreq.c
+++ b/drivers/gpu/drm/panfrost/panfrost_devfreq.c
@@ -90,8 +90,11 @@ int panfrost_devfreq_init(struct panfrost_device *pfdev)
cur_freq = clk_get_rate(pfdev->clock);
opp = devfreq_recommended_opp(dev, _freq, 0);
- if (IS_ERR(opp))
- return PTR_ERR(opp);
+ if (IS_ERR(opp)) {
+ DRM_DEV_ERROR(dev, "Failed to set recommended OPP\n");
+ ret = PTR_ERR(opp);
+ goto err_opp;
+ }
panfrost_devfreq_profile.initial_freq = cur_freq;
dev_pm_opp_put(opp);
@@ -100,8 +103,8 @@ int panfrost_devfreq_init(struct panfrost_device *pfdev)
DEVFREQ_GOV_SIMPLE_ONDEMAND, NULL);
if (IS_ERR(devfreq)) {
DRM_DEV_ERROR(dev, "Couldn't initialize GPU devfreq\n");
- dev_pm_opp_of_remove_table(dev);
- return PTR_ERR(devfreq);
+ ret = PTR_ERR(devfreq);
+ goto err_opp;
}
pfdev->devfreq.devfreq = devfreq;
@@ -112,6 +115,11 @@ int panfrost_devfreq_init(struct panfrost_device *pfdev)
pfdev->devfreq.cooling = cooling;
return 0;
+
+err_opp:
+ dev_pm_opp_of_remove_table(dev);
+
+ return ret;
}
void panfrost_devfreq_fini(struct panfrost_device *pfdev)
--
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Re: [PATCH 2/2] drm/panfrost: add devfreq regulator support
Hi Steven,
On Mon, 13 Apr 2020 at 15:18, Steven Price wrote:
>
> On 11/04/2020 21:06, Clément Péron wrote:
> > OPP table can defined both frequency and voltage.
> >
> > Register the mali regulator if it exist.
> >
> > Signed-off-by: Clément Péron
> > ---
> > drivers/gpu/drm/panfrost/panfrost_devfreq.c | 34 ++---
> > drivers/gpu/drm/panfrost/panfrost_device.h | 1 +
> > 2 files changed, 31 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/panfrost/panfrost_devfreq.c
> > b/drivers/gpu/drm/panfrost/panfrost_devfreq.c
> > index 62541f4edd81..2dc8e2355358 100644
> > --- a/drivers/gpu/drm/panfrost/panfrost_devfreq.c
> > +++ b/drivers/gpu/drm/panfrost/panfrost_devfreq.c
> > @@ -78,12 +78,26 @@ int panfrost_devfreq_init(struct panfrost_device *pfdev)
> > struct device *dev = >pdev->dev;
> > struct devfreq *devfreq;
> > struct thermal_cooling_device *cooling;
> > + const char *mali = "mali";
> > + struct opp_table *opp_table = NULL;
> > +
> > + /* Regulator is optional */
> > + opp_table = dev_pm_opp_set_regulators(dev, , 1);
>
> This looks like it applies before 3e1399bccf51 ("drm/panfrost: Add
> support for multiple regulators") which is currently in drm-misc-next
> (and linux-next). You want something more like:
Thanks for you review, indeed I didn't see that multiple regulators
support has been added.
Will update in v2.
>
> opp_table = dev_pm_opp_set_regulators(dev,
>pfdev->comp->supply_names,
>pfdev->comp->num_supplies);
>
> Otherwise a platform with multiple regulators won't work correctly.
>
> Also running on my firefly (RK3288) board I get the following warning:
>
> debugfs: Directory 'ffa3.gpu-mali' with parent 'vdd_gpu' already
> present!
>
> This is due to the regulator debugfs entries getting created twice (once
> in panfrost_regulator_init() and once here).
Is it a warning that should be consider as an error? Look's more an info no?
What should be the correct behavior if a device want to register two
times the same regulator?
Link to original discussion:
https://lore.kernel.org/patchwork/patch/1176717/
Thanks,
Clement
>
> I have been taking a look at doing the same thing (I picked up Martin
> Blumenstingl's patch series[1]), but haven't had much time to focus on
> this recently.
>
> Thanks,
>
> Steve
>
> [1]
> https://lore.kernel.org/dri-devel/20200112001623.2121227-1-martin.blumensti...@googlemail.com/
>
>
> > + if (IS_ERR(opp_table)) {
> > + ret = PTR_ERR(opp_table);
> > + if (ret != -ENODEV) {
> > + DRM_DEV_ERROR(dev, "Failed to set regulator: %d\n",
> > ret);
> > + return ret;
> > + }
> > + }
> > + pfdev->devfreq.opp_table = opp_table;
> >
> > ret = dev_pm_opp_of_add_table(dev);
> > - if (ret == -ENODEV) /* Optional, continue without devfreq */
> > - return 0;
> > - else if (ret)
> > - return ret;
> > + if (ret) {
> > + if (ret == -ENODEV) /* Optional, continue without devfreq */
> > + ret = 0;
> > + goto err_opp_reg;
> > + }
> >
> > panfrost_devfreq_reset(pfdev);
> >
> > @@ -119,6 +133,12 @@ int panfrost_devfreq_init(struct panfrost_device
> > *pfdev)
> > err_opp:
> > dev_pm_opp_of_remove_table(dev);
> >
> > +err_opp_reg:
> > + if (pfdev->devfreq.opp_table) {
> > + dev_pm_opp_put_regulators(pfdev->devfreq.opp_table);
> > + pfdev->devfreq.opp_table = NULL;
> > + }
> > +
> > return ret;
> > }
> >
> > @@ -126,7 +146,13 @@ void panfrost_devfreq_fini(struct panfrost_device
> > *pfdev)
> > {
> > if (pfdev->devfreq.cooling)
> > devfreq_cooling_unregister(pfdev->devfreq.cooling);
> > +
> > dev_pm_opp_of_remove_table(>pdev->dev);
> > +
> > + if (pfdev->devfreq.opp_table) {
> > + dev_pm_opp_put_regulators(pfdev->devfreq.opp_table);
> > + pfdev->devfreq.opp_table = NULL;
> > + }
> > }
> >
> > void panfrost_devfreq_resume(struct panfrost_device *pfdev)
> > diff --git a/drivers/gpu/drm/panfrost/panfrost_device.h
> > b/drivers/gpu/drm/panfrost/panfrost_device.h
> > index 06713811b92c..f6b0c779dfe5 100644
> > --- a/drivers/gpu/drm/panfrost/panfrost_device.h
> > +++ b/drivers/gpu/drm/panfrost/panfrost_device.h
> > @@ -86,6 +86,7 @@ struct panfrost_device {
> > struct {
> > struct devfreq *devfreq;
> > struct thermal_cooling_device *cooling;
> > + struct opp_table *opp_table;
> > ktime_t busy_time;
> > ktime_t idle_time;
> > ktime_t time_last_update;
> >
>
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Re: [PATCH 2/2] drm/panfrost: add devfreq regulator support
Hi,
On Mon, 13 Apr 2020 at 16:18, Clément Péron wrote:
>
> Hi Steven,
>
> On Mon, 13 Apr 2020 at 15:18, Steven Price wrote:
> >
> > On 11/04/2020 21:06, Clément Péron wrote:
> > > OPP table can defined both frequency and voltage.
> > >
> > > Register the mali regulator if it exist.
> > >
> > > Signed-off-by: Clément Péron
> > > ---
> > > drivers/gpu/drm/panfrost/panfrost_devfreq.c | 34 ++---
> > > drivers/gpu/drm/panfrost/panfrost_device.h | 1 +
> > > 2 files changed, 31 insertions(+), 4 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/panfrost/panfrost_devfreq.c
> > > b/drivers/gpu/drm/panfrost/panfrost_devfreq.c
> > > index 62541f4edd81..2dc8e2355358 100644
> > > --- a/drivers/gpu/drm/panfrost/panfrost_devfreq.c
> > > +++ b/drivers/gpu/drm/panfrost/panfrost_devfreq.c
> > > @@ -78,12 +78,26 @@ int panfrost_devfreq_init(struct panfrost_device
> > > *pfdev)
> > > struct device *dev = >pdev->dev;
> > > struct devfreq *devfreq;
> > > struct thermal_cooling_device *cooling;
> > > + const char *mali = "mali";
> > > + struct opp_table *opp_table = NULL;
> > > +
> > > + /* Regulator is optional */
> > > + opp_table = dev_pm_opp_set_regulators(dev, , 1);
> >
> > This looks like it applies before 3e1399bccf51 ("drm/panfrost: Add
> > support for multiple regulators") which is currently in drm-misc-next
> > (and linux-next). You want something more like:
>
> Thanks for you review, indeed I didn't see that multiple regulators
> support has been added.
> Will update in v2.
>
> >
> > opp_table = dev_pm_opp_set_regulators(dev,
> >pfdev->comp->supply_names,
> >pfdev->comp->num_supplies);
> >
> > Otherwise a platform with multiple regulators won't work correctly.
> >
> > Also running on my firefly (RK3288) board I get the following warning:
> >
> > debugfs: Directory 'ffa3.gpu-mali' with parent 'vdd_gpu' already
> > present!
> >
> > This is due to the regulator debugfs entries getting created twice (once
> > in panfrost_regulator_init() and once here).
>
> Is it a warning that should be consider as an error? Look's more an info no?
> What should be the correct behavior if a device want to register two
> times the same regulator?
Or we can change the name from vdd_XXX to opp_vdd_XXX ?
https://elixir.bootlin.com/linux/latest/source/drivers/opp/debugfs.c#L45
>
> Link to original discussion:
> https://lore.kernel.org/patchwork/patch/1176717/
>
> Thanks,
> Clement
>
> >
> > I have been taking a look at doing the same thing (I picked up Martin
> > Blumenstingl's patch series[1]), but haven't had much time to focus on
> > this recently.
> >
> > Thanks,
> >
> > Steve
> >
> > [1]
> > https://lore.kernel.org/dri-devel/20200112001623.2121227-1-martin.blumensti...@googlemail.com/
> >
> >
> > > + if (IS_ERR(opp_table)) {
> > > + ret = PTR_ERR(opp_table);
> > > + if (ret != -ENODEV) {
> > > + DRM_DEV_ERROR(dev, "Failed to set regulator: %d\n",
> > > ret);
> > > + return ret;
> > > + }
> > > + }
> > > + pfdev->devfreq.opp_table = opp_table;
> > >
> > > ret = dev_pm_opp_of_add_table(dev);
> > > - if (ret == -ENODEV) /* Optional, continue without devfreq */
> > > - return 0;
> > > - else if (ret)
> > > - return ret;
> > > + if (ret) {
> > > + if (ret == -ENODEV) /* Optional, continue without devfreq */
> > > + ret = 0;
> > > + goto err_opp_reg;
> > > + }
> > >
> > > panfrost_devfreq_reset(pfdev);
> > >
> > > @@ -119,6 +133,12 @@ int panfrost_devfreq_init(struct panfrost_device
> > > *pfdev)
> > > err_opp:
> > > dev_pm_opp_of_remove_table(dev);
> > >
> > > +err_opp_reg:
> > > + if (pfdev->devfreq.opp_table) {
> > > + dev_pm_opp_put_regulators(pfdev->devfreq.opp_table);
> > > + pfdev->devfreq.opp_table = NULL;
> > > + }
> > > +
> > > return ret;
> > > }
> > >
> > &
Re: [PATCH 2/2] drm/panfrost: add devfreq regulator support
Hi Panfrost and OPP Maintainers,
On Sat, 11 Apr 2020 at 22:06, Clément Péron wrote:
>
> OPP table can defined both frequency and voltage.
>
> Register the mali regulator if it exist.
After this patch, Panfrost update properly both voltage and frequency.
But the GPU is still not properly down-clocked when temperature is high.
I try to add a cooling map like this :
https://github.com/clementperon/linux/commit/955961c7c035abbf44e74f608fe8f059c06a2fbe
But got the following error:
[2.712082] panfrost 180.gpu: [drm:panfrost_devfreq_init
[panfrost]] Failed to register cooling device
Do you see what I'm missing?
Thanks for your help,
Clement
>
> Signed-off-by: Clément Péron
> ---
> drivers/gpu/drm/panfrost/panfrost_devfreq.c | 34 ++---
> drivers/gpu/drm/panfrost/panfrost_device.h | 1 +
> 2 files changed, 31 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/panfrost/panfrost_devfreq.c
> b/drivers/gpu/drm/panfrost/panfrost_devfreq.c
> index 62541f4edd81..2dc8e2355358 100644
> --- a/drivers/gpu/drm/panfrost/panfrost_devfreq.c
> +++ b/drivers/gpu/drm/panfrost/panfrost_devfreq.c
> @@ -78,12 +78,26 @@ int panfrost_devfreq_init(struct panfrost_device *pfdev)
> struct device *dev = >pdev->dev;
> struct devfreq *devfreq;
> struct thermal_cooling_device *cooling;
> + const char *mali = "mali";
> + struct opp_table *opp_table = NULL;
> +
> + /* Regulator is optional */
> + opp_table = dev_pm_opp_set_regulators(dev, , 1);
> + if (IS_ERR(opp_table)) {
> + ret = PTR_ERR(opp_table);
> + if (ret != -ENODEV) {
> + DRM_DEV_ERROR(dev, "Failed to set regulator: %d\n",
> ret);
> + return ret;
> + }
> + }
> + pfdev->devfreq.opp_table = opp_table;
>
> ret = dev_pm_opp_of_add_table(dev);
> - if (ret == -ENODEV) /* Optional, continue without devfreq */
> - return 0;
> - else if (ret)
> - return ret;
> + if (ret) {
> + if (ret == -ENODEV) /* Optional, continue without devfreq */
> + ret = 0;
> + goto err_opp_reg;
> + }
>
> panfrost_devfreq_reset(pfdev);
>
> @@ -119,6 +133,12 @@ int panfrost_devfreq_init(struct panfrost_device *pfdev)
> err_opp:
> dev_pm_opp_of_remove_table(dev);
>
> +err_opp_reg:
> + if (pfdev->devfreq.opp_table) {
> + dev_pm_opp_put_regulators(pfdev->devfreq.opp_table);
> + pfdev->devfreq.opp_table = NULL;
> + }
> +
> return ret;
> }
>
> @@ -126,7 +146,13 @@ void panfrost_devfreq_fini(struct panfrost_device *pfdev)
> {
> if (pfdev->devfreq.cooling)
> devfreq_cooling_unregister(pfdev->devfreq.cooling);
> +
> dev_pm_opp_of_remove_table(>pdev->dev);
> +
> + if (pfdev->devfreq.opp_table) {
> + dev_pm_opp_put_regulators(pfdev->devfreq.opp_table);
> + pfdev->devfreq.opp_table = NULL;
> + }
> }
>
> void panfrost_devfreq_resume(struct panfrost_device *pfdev)
> diff --git a/drivers/gpu/drm/panfrost/panfrost_device.h
> b/drivers/gpu/drm/panfrost/panfrost_device.h
> index 06713811b92c..f6b0c779dfe5 100644
> --- a/drivers/gpu/drm/panfrost/panfrost_device.h
> +++ b/drivers/gpu/drm/panfrost/panfrost_device.h
> @@ -86,6 +86,7 @@ struct panfrost_device {
> struct {
> struct devfreq *devfreq;
> struct thermal_cooling_device *cooling;
> + struct opp_table *opp_table;
> ktime_t busy_time;
> ktime_t idle_time;
> ktime_t time_last_update;
> --
> 2.20.1
>
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Re: [PATCH 2/2] drm/panfrost: add devfreq regulator support
Hi Steven,
On Mon, 13 Apr 2020 at 18:35, Clément Péron wrote:
>
> Hi Steven,
>
> On Mon, 13 Apr 2020 at 17:55, Steven Price wrote:
> >
> > On 13/04/2020 15:31, Clément Péron wrote:
> > > Hi,
> > >
> > > On Mon, 13 Apr 2020 at 16:18, Clément Péron wrote:
> > >>
> > >> Hi Steven,
> > >>
> > >> On Mon, 13 Apr 2020 at 15:18, Steven Price wrote:
> > >>>
> > >>> On 11/04/2020 21:06, Clément Péron wrote:
> > >>>> OPP table can defined both frequency and voltage.
> > >>>>
> > >>>> Register the mali regulator if it exist.
> > >>>>
> > >>>> Signed-off-by: Clément Péron
> > >>>> ---
> > >>>>drivers/gpu/drm/panfrost/panfrost_devfreq.c | 34
> > >>>> ++---
> > >>>>drivers/gpu/drm/panfrost/panfrost_device.h | 1 +
> > >>>>2 files changed, 31 insertions(+), 4 deletions(-)
> > >>>>
> > >>>> diff --git a/drivers/gpu/drm/panfrost/panfrost_devfreq.c
> > >>>> b/drivers/gpu/drm/panfrost/panfrost_devfreq.c
> > >>>> index 62541f4edd81..2dc8e2355358 100644
> > >>>> --- a/drivers/gpu/drm/panfrost/panfrost_devfreq.c
> > >>>> +++ b/drivers/gpu/drm/panfrost/panfrost_devfreq.c
> > >>>> @@ -78,12 +78,26 @@ int panfrost_devfreq_init(struct panfrost_device
> > >>>> *pfdev)
> > >>>>struct device *dev = >pdev->dev;
> > >>>>struct devfreq *devfreq;
> > >>>>struct thermal_cooling_device *cooling;
> > >>>> + const char *mali = "mali";
> > >>>> + struct opp_table *opp_table = NULL;
> > >>>> +
> > >>>> + /* Regulator is optional */
> > >>>> + opp_table = dev_pm_opp_set_regulators(dev, , 1);
> > >>>
> > >>> This looks like it applies before 3e1399bccf51 ("drm/panfrost: Add
> > >>> support for multiple regulators") which is currently in drm-misc-next
> > >>> (and linux-next). You want something more like:
> > >>
> > >> Thanks for you review, indeed I didn't see that multiple regulators
> > >> support has been added.
> > >> Will update in v2.
> > >>
> > >>>
> > >>> opp_table = dev_pm_opp_set_regulators(dev,
> > >>> pfdev->comp->supply_names,
> > >>> pfdev->comp->num_supplies);
> > >>>
> > >>> Otherwise a platform with multiple regulators won't work correctly.
> > >>>
> > >>> Also running on my firefly (RK3288) board I get the following warning:
> > >>>
> > >>> debugfs: Directory 'ffa3.gpu-mali' with parent 'vdd_gpu'
> > >>> already
> > >>> present!
I try to reproduce but it can't
regulator is mount at :
./regulator/vdd-gpu
whereas OPP is mount :
./opp/soc-180.gpu/opp:75600/supply-0/
I see that firefly as 2 regulators with the same name :
vdd_gpu from syr828
(https://github.com/mopplayer/Firefly-RK3288-Kernel-With-Mali764/blob/master/arch/arm/boot/dts/firefly-rk3288.dts#L453)
vdd_gpu from rk808_dcdc2_reg
(https://github.com/mopplayer/Firefly-RK3288-Kernel-With-Mali764/blob/master/arch/arm/boot/dts/firefly-rk3288.dts#L841)
So i think the issue is from the firefly device-tree.
Regards,
Clement
> > >>>
> > >>> This is due to the regulator debugfs entries getting created twice (once
> > >>> in panfrost_regulator_init() and once here).
> > >>
> > >> Is it a warning that should be consider as an error? Look's more an info
> > >> no?
> > >> What should be the correct behavior if a device want to register two
> > >> times the same regulator?
> > >
> > > Or we can change the name from vdd_XXX to opp_vdd_XXX ?
> > > https://elixir.bootlin.com/linux/latest/source/drivers/opp/debugfs.c#L45
> >
> > Yes, I'm not sure that it's actually a problem in practice. And it may
> > well be correct to change this in the generic code rather than try to
> > work around it in Panfrost. But we shouldn't spam the user with warnings
> > as that makes real issues harder to see.
> >
> > Your suggestion to change the name seems reasonable to me, but I don't
> > fully understand the opp code, so we'd need some review from the OPP
> > maintainers. Hopefully Viresh, Nishanth or Stephen can provide some insight.
>
> Agree, I will send a v2 with the rename and see if OPP Maintainers agree.
>
> Regards,
> Clement
>
> >
> > Steve
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[PATCH v2 2/2] drm/panfrost: add devfreq regulator support
OPP table can defined both frequency and voltage.
Register mali regulators to OPP driver.
Signed-off-by: Clément Péron
---
drivers/gpu/drm/panfrost/panfrost_devfreq.c | 34 ++---
drivers/gpu/drm/panfrost/panfrost_device.h | 1 +
2 files changed, 31 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/panfrost/panfrost_devfreq.c
b/drivers/gpu/drm/panfrost/panfrost_devfreq.c
index 62541f4edd81..54a109bbdc18 100644
--- a/drivers/gpu/drm/panfrost/panfrost_devfreq.c
+++ b/drivers/gpu/drm/panfrost/panfrost_devfreq.c
@@ -78,12 +78,26 @@ int panfrost_devfreq_init(struct panfrost_device *pfdev)
struct device *dev = >pdev->dev;
struct devfreq *devfreq;
struct thermal_cooling_device *cooling;
+ struct opp_table *opp_table;
+
+ /* Regulator is optional */
+ opp_table = dev_pm_opp_set_regulators(dev, pfdev->comp->supply_names,
+ pfdev->comp->num_supplies);
+ if (IS_ERR(opp_table)) {
+ ret = PTR_ERR(opp_table);
+ if (ret != -ENODEV) {
+ DRM_DEV_ERROR(dev, "Failed to set regulator: %d\n",
ret);
+ return ret;
+ }
+ }
+ pfdev->devfreq.opp_table = opp_table;
ret = dev_pm_opp_of_add_table(dev);
- if (ret == -ENODEV) /* Optional, continue without devfreq */
- return 0;
- else if (ret)
- return ret;
+ if (ret) {
+ if (ret == -ENODEV) /* Optional, continue without devfreq */
+ ret = 0;
+ goto err_opp_reg;
+ }
panfrost_devfreq_reset(pfdev);
@@ -119,6 +133,12 @@ int panfrost_devfreq_init(struct panfrost_device *pfdev)
err_opp:
dev_pm_opp_of_remove_table(dev);
+err_opp_reg:
+ if (pfdev->devfreq.opp_table) {
+ dev_pm_opp_put_regulators(pfdev->devfreq.opp_table);
+ pfdev->devfreq.opp_table = NULL;
+ }
+
return ret;
}
@@ -126,7 +146,13 @@ void panfrost_devfreq_fini(struct panfrost_device *pfdev)
{
if (pfdev->devfreq.cooling)
devfreq_cooling_unregister(pfdev->devfreq.cooling);
+
dev_pm_opp_of_remove_table(>pdev->dev);
+
+ if (pfdev->devfreq.opp_table) {
+ dev_pm_opp_put_regulators(pfdev->devfreq.opp_table);
+ pfdev->devfreq.opp_table = NULL;
+ }
}
void panfrost_devfreq_resume(struct panfrost_device *pfdev)
diff --git a/drivers/gpu/drm/panfrost/panfrost_device.h
b/drivers/gpu/drm/panfrost/panfrost_device.h
index c30c719a8059..c11d19430c0f 100644
--- a/drivers/gpu/drm/panfrost/panfrost_device.h
+++ b/drivers/gpu/drm/panfrost/panfrost_device.h
@@ -110,6 +110,7 @@ struct panfrost_device {
struct {
struct devfreq *devfreq;
struct thermal_cooling_device *cooling;
+ struct opp_table *opp_table;
ktime_t busy_time;
ktime_t idle_time;
ktime_t time_last_update;
--
2.20.1
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Re: [PATCH 2/2] drm/panfrost: add devfreq regulator support
Hi Steven,
On Mon, 13 Apr 2020 at 17:55, Steven Price wrote:
>
> On 13/04/2020 15:31, Clément Péron wrote:
> > Hi,
> >
> > On Mon, 13 Apr 2020 at 16:18, Clément Péron wrote:
> >>
> >> Hi Steven,
> >>
> >> On Mon, 13 Apr 2020 at 15:18, Steven Price wrote:
> >>>
> >>> On 11/04/2020 21:06, Clément Péron wrote:
> >>>> OPP table can defined both frequency and voltage.
> >>>>
> >>>> Register the mali regulator if it exist.
> >>>>
> >>>> Signed-off-by: Clément Péron
> >>>> ---
> >>>>drivers/gpu/drm/panfrost/panfrost_devfreq.c | 34 ++---
> >>>>drivers/gpu/drm/panfrost/panfrost_device.h | 1 +
> >>>>2 files changed, 31 insertions(+), 4 deletions(-)
> >>>>
> >>>> diff --git a/drivers/gpu/drm/panfrost/panfrost_devfreq.c
> >>>> b/drivers/gpu/drm/panfrost/panfrost_devfreq.c
> >>>> index 62541f4edd81..2dc8e2355358 100644
> >>>> --- a/drivers/gpu/drm/panfrost/panfrost_devfreq.c
> >>>> +++ b/drivers/gpu/drm/panfrost/panfrost_devfreq.c
> >>>> @@ -78,12 +78,26 @@ int panfrost_devfreq_init(struct panfrost_device
> >>>> *pfdev)
> >>>>struct device *dev = >pdev->dev;
> >>>>struct devfreq *devfreq;
> >>>>struct thermal_cooling_device *cooling;
> >>>> + const char *mali = "mali";
> >>>> + struct opp_table *opp_table = NULL;
> >>>> +
> >>>> + /* Regulator is optional */
> >>>> + opp_table = dev_pm_opp_set_regulators(dev, , 1);
> >>>
> >>> This looks like it applies before 3e1399bccf51 ("drm/panfrost: Add
> >>> support for multiple regulators") which is currently in drm-misc-next
> >>> (and linux-next). You want something more like:
> >>
> >> Thanks for you review, indeed I didn't see that multiple regulators
> >> support has been added.
> >> Will update in v2.
> >>
> >>>
> >>> opp_table = dev_pm_opp_set_regulators(dev,
> >>> pfdev->comp->supply_names,
> >>> pfdev->comp->num_supplies);
> >>>
> >>> Otherwise a platform with multiple regulators won't work correctly.
> >>>
> >>> Also running on my firefly (RK3288) board I get the following warning:
> >>>
> >>> debugfs: Directory 'ffa3.gpu-mali' with parent 'vdd_gpu' already
> >>> present!
> >>>
> >>> This is due to the regulator debugfs entries getting created twice (once
> >>> in panfrost_regulator_init() and once here).
> >>
> >> Is it a warning that should be consider as an error? Look's more an info
> >> no?
> >> What should be the correct behavior if a device want to register two
> >> times the same regulator?
> >
> > Or we can change the name from vdd_XXX to opp_vdd_XXX ?
> > https://elixir.bootlin.com/linux/latest/source/drivers/opp/debugfs.c#L45
>
> Yes, I'm not sure that it's actually a problem in practice. And it may
> well be correct to change this in the generic code rather than try to
> work around it in Panfrost. But we shouldn't spam the user with warnings
> as that makes real issues harder to see.
>
> Your suggestion to change the name seems reasonable to me, but I don't
> fully understand the opp code, so we'd need some review from the OPP
> maintainers. Hopefully Viresh, Nishanth or Stephen can provide some insight.
Agree, I will send a v2 with the rename and see if OPP Maintainers agree.
Regards,
Clement
>
> Steve
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Re: Multiple regulators for one device [was drm/panfrost: add devfreq regulator support]
Hi, On Fri, 17 Apr 2020 at 14:33, Clément Péron wrote: > > Hi Robin, > > On Fri, 17 Apr 2020 at 13:10, Robin Murphy wrote: > > > > On 2020-04-16 2:42 pm, Steven Price wrote: > > [...] > > > Perhaps a better approach would be for Panfrost to hand over the struct > > > regulator objects it has already got to the OPP framework. I.e. open > > > code dev_pm_opp_set_regulators(), but instead of calling > > > regulator_get_optional() simply populate the regulators we already have? Just saw that a Lima devfreq[0] has been also introduced with I think exactly the same logic. Is this something that hasn't been triggered by Maintainer or I am missing something? I will backport some remarks made on the lima devfreq to improve panfrost one. They are almost identical. Regards, Clement 0: https://cgit.freedesktop.org/drm-misc/commit/?id=1996970773a323533e1cc1b6b97f00a95d675f32 > > > > > > The other benefit of that is it would provide a clear hand-over of > > > responsibility between Panfrost handling it's own regulators and the OPP > > > framework picking up the work. The disadvantage is that Panfrost would > > > have to track whether the regulators have been handed over or not. > > > > Sounds like the most logical thing to do is to shuffle things around so > > we start by trying to set up an OPP table, then fall back to explicitly > > claiming clocks and regulators if necessary. Then we can easily make the > > devfreq decision later in probe based on how that turned out. > > Ok I will propose a new serie with this behavior, > > Thanks > Clement > > > > > Robin. ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 1/2] drm/panfrost: missing remove opp table in case of failure
In case of failure we need to remove OPP table.
Use Linux classic error handling with goto usage.
Signed-off-by: Clément Péron
---
drivers/gpu/drm/panfrost/panfrost_devfreq.c | 16
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/panfrost/panfrost_devfreq.c
b/drivers/gpu/drm/panfrost/panfrost_devfreq.c
index 413987038fbf..62541f4edd81 100644
--- a/drivers/gpu/drm/panfrost/panfrost_devfreq.c
+++ b/drivers/gpu/drm/panfrost/panfrost_devfreq.c
@@ -90,8 +90,11 @@ int panfrost_devfreq_init(struct panfrost_device *pfdev)
cur_freq = clk_get_rate(pfdev->clock);
opp = devfreq_recommended_opp(dev, _freq, 0);
- if (IS_ERR(opp))
- return PTR_ERR(opp);
+ if (IS_ERR(opp)) {
+ DRM_DEV_ERROR(dev, "Failed to set recommended OPP\n");
+ ret = PTR_ERR(opp);
+ goto err_opp;
+ }
panfrost_devfreq_profile.initial_freq = cur_freq;
dev_pm_opp_put(opp);
@@ -100,8 +103,8 @@ int panfrost_devfreq_init(struct panfrost_device *pfdev)
DEVFREQ_GOV_SIMPLE_ONDEMAND, NULL);
if (IS_ERR(devfreq)) {
DRM_DEV_ERROR(dev, "Couldn't initialize GPU devfreq\n");
- dev_pm_opp_of_remove_table(dev);
- return PTR_ERR(devfreq);
+ ret = PTR_ERR(devfreq);
+ goto err_opp;
}
pfdev->devfreq.devfreq = devfreq;
@@ -112,6 +115,11 @@ int panfrost_devfreq_init(struct panfrost_device *pfdev)
pfdev->devfreq.cooling = cooling;
return 0;
+
+err_opp:
+ dev_pm_opp_of_remove_table(dev);
+
+ return ret;
}
void panfrost_devfreq_fini(struct panfrost_device *pfdev)
--
2.20.1
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[PATCH 2/2] drm/panfrost: add devfreq regulator support
OPP table can defined both frequency and voltage.
Register the mali regulator if it exist.
Signed-off-by: Clément Péron
---
drivers/gpu/drm/panfrost/panfrost_devfreq.c | 34 ++---
drivers/gpu/drm/panfrost/panfrost_device.h | 1 +
2 files changed, 31 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/panfrost/panfrost_devfreq.c
b/drivers/gpu/drm/panfrost/panfrost_devfreq.c
index 62541f4edd81..2dc8e2355358 100644
--- a/drivers/gpu/drm/panfrost/panfrost_devfreq.c
+++ b/drivers/gpu/drm/panfrost/panfrost_devfreq.c
@@ -78,12 +78,26 @@ int panfrost_devfreq_init(struct panfrost_device *pfdev)
struct device *dev = >pdev->dev;
struct devfreq *devfreq;
struct thermal_cooling_device *cooling;
+ const char *mali = "mali";
+ struct opp_table *opp_table = NULL;
+
+ /* Regulator is optional */
+ opp_table = dev_pm_opp_set_regulators(dev, , 1);
+ if (IS_ERR(opp_table)) {
+ ret = PTR_ERR(opp_table);
+ if (ret != -ENODEV) {
+ DRM_DEV_ERROR(dev, "Failed to set regulator: %d\n",
ret);
+ return ret;
+ }
+ }
+ pfdev->devfreq.opp_table = opp_table;
ret = dev_pm_opp_of_add_table(dev);
- if (ret == -ENODEV) /* Optional, continue without devfreq */
- return 0;
- else if (ret)
- return ret;
+ if (ret) {
+ if (ret == -ENODEV) /* Optional, continue without devfreq */
+ ret = 0;
+ goto err_opp_reg;
+ }
panfrost_devfreq_reset(pfdev);
@@ -119,6 +133,12 @@ int panfrost_devfreq_init(struct panfrost_device *pfdev)
err_opp:
dev_pm_opp_of_remove_table(dev);
+err_opp_reg:
+ if (pfdev->devfreq.opp_table) {
+ dev_pm_opp_put_regulators(pfdev->devfreq.opp_table);
+ pfdev->devfreq.opp_table = NULL;
+ }
+
return ret;
}
@@ -126,7 +146,13 @@ void panfrost_devfreq_fini(struct panfrost_device *pfdev)
{
if (pfdev->devfreq.cooling)
devfreq_cooling_unregister(pfdev->devfreq.cooling);
+
dev_pm_opp_of_remove_table(>pdev->dev);
+
+ if (pfdev->devfreq.opp_table) {
+ dev_pm_opp_put_regulators(pfdev->devfreq.opp_table);
+ pfdev->devfreq.opp_table = NULL;
+ }
}
void panfrost_devfreq_resume(struct panfrost_device *pfdev)
diff --git a/drivers/gpu/drm/panfrost/panfrost_device.h
b/drivers/gpu/drm/panfrost/panfrost_device.h
index 06713811b92c..f6b0c779dfe5 100644
--- a/drivers/gpu/drm/panfrost/panfrost_device.h
+++ b/drivers/gpu/drm/panfrost/panfrost_device.h
@@ -86,6 +86,7 @@ struct panfrost_device {
struct {
struct devfreq *devfreq;
struct thermal_cooling_device *cooling;
+ struct opp_table *opp_table;
ktime_t busy_time;
ktime_t idle_time;
ktime_t time_last_update;
--
2.20.1
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[PATCH 13/15] arm64: dts: allwinner: h6: Add cooling map for GPU
Add a simple cooling map for the GPU.
Signed-off-by: Clément Péron
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 22
1 file changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index 2e31632c6ca8..b26f735201c7 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -173,6 +173,7 @@
clocks = < CLK_GPU>, < CLK_BUS_GPU>;
clock-names = "core", "bus";
resets = < RST_BUS_GPU>;
+ #cooling-cells = <2>;
status = "disabled";
};
@@ -1002,6 +1003,27 @@
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = < 1>;
+
+ trips {
+ gpu_alert: gpu-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ gpu-crit {
+ temperature = <10>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <_alert>;
+ cooling-device = < THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
+ };
+ };
};
};
};
--
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[PATCH 10/15] drm/panfrost: add regulators to devfreq
Some OPP tables specify voltage for each frequency. Devfreq can
handle these regulators but they should be get only 1 time to avoid
issue and know who is in charge.
If OPP table is probe don't init regulator.
Signed-off-by: Clément Péron
---
drivers/gpu/drm/panfrost/panfrost_devfreq.c | 19 +++
drivers/gpu/drm/panfrost/panfrost_devfreq.h | 2 ++
drivers/gpu/drm/panfrost/panfrost_device.c | 11 +++
3 files changed, 28 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/panfrost/panfrost_devfreq.c
b/drivers/gpu/drm/panfrost/panfrost_devfreq.c
index fce21c682414..9ffea0d4a087 100644
--- a/drivers/gpu/drm/panfrost/panfrost_devfreq.c
+++ b/drivers/gpu/drm/panfrost/panfrost_devfreq.c
@@ -93,6 +93,7 @@ int panfrost_devfreq_init(struct panfrost_device *pfdev)
unsigned long cur_freq;
struct device *dev = >pdev->dev;
struct devfreq *devfreq;
+ struct opp_table *opp_table;
struct thermal_cooling_device *cooling;
struct panfrost_devfreq *pfdevfreq = >pfdevfreq;
@@ -102,6 +103,19 @@ int panfrost_devfreq_init(struct panfrost_device *pfdev)
spin_lock_init(>lock);
+ opp_table = dev_pm_opp_set_regulators(dev, pfdev->comp->supply_names,
+ pfdev->comp->num_supplies);
+ if (IS_ERR(opp_table)) {
+ ret = PTR_ERR(opp_table);
+ /* Continue if the optional regulator is missing */
+ if (ret != -ENODEV) {
+ DRM_DEV_ERROR(dev, "Couldn't set OPP regulators\n");
+ goto err_fini;
+ }
+ } else {
+ pfdevfreq->regulators_opp_table = opp_table;
+ }
+
ret = dev_pm_opp_of_add_table(dev);
if (ret) {
DRM_DEV_ERROR(dev, "Couldn't add OPP table\n");
@@ -157,6 +171,11 @@ void panfrost_devfreq_fini(struct panfrost_device *pfdev)
dev_pm_opp_of_remove_table(>pdev->dev);
pfdevfreq->opp_of_table_added = false;
}
+
+ if (pfdevfreq->regulators_opp_table) {
+ dev_pm_opp_put_regulators(pfdevfreq->regulators_opp_table);
+ pfdevfreq->regulators_opp_table = NULL;
+ }
}
void panfrost_devfreq_resume(struct panfrost_device *pfdev)
diff --git a/drivers/gpu/drm/panfrost/panfrost_devfreq.h
b/drivers/gpu/drm/panfrost/panfrost_devfreq.h
index add203cb00c2..347cde4786cf 100644
--- a/drivers/gpu/drm/panfrost/panfrost_devfreq.h
+++ b/drivers/gpu/drm/panfrost/panfrost_devfreq.h
@@ -8,12 +8,14 @@
#include
struct devfreq;
+struct opp_table;
struct thermal_cooling_device;
struct panfrost_device;
struct panfrost_devfreq {
struct devfreq *devfreq;
+ struct opp_table *regulators_opp_table;
struct thermal_cooling_device *cooling;
bool opp_of_table_added;
diff --git a/drivers/gpu/drm/panfrost/panfrost_device.c
b/drivers/gpu/drm/panfrost/panfrost_device.c
index 67eedf64e82d..8b17fb2e3369 100644
--- a/drivers/gpu/drm/panfrost/panfrost_device.c
+++ b/drivers/gpu/drm/panfrost/panfrost_device.c
@@ -222,10 +222,13 @@ int panfrost_device_init(struct panfrost_device *pfdev)
goto err_out0;
}
- err = panfrost_regulator_init(pfdev);
- if (err) {
- dev_err(pfdev->dev, "regulator init failed %d\n", err);
- goto err_out1;
+ /* OPP will handle regulators */
+ if (!pfdev->pfdevfreq.opp_of_table_added) {
+ err = panfrost_regulator_init(pfdev);
+ if (err) {
+ dev_err(pfdev->dev, "regulator init failed %d\n", err);
+ goto err_out1;
+ }
}
err = panfrost_reset_init(pfdev);
--
2.20.1
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[PATCH 15/15] [DO NOT MERGE] arm64: dts: allwinner: force GPU regulator to be always
Signed-off-by: Clément Péron
---
arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
index 3f7ceeb1a767..14257f7476b8 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
@@ -245,6 +245,7 @@
};
reg_dcdcc: dcdcc {
+ regulator-always-on;
regulator-enable-ramp-delay = <32000>;
regulator-min-microvolt = <81>;
regulator-max-microvolt = <108>;
--
2.20.1
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[PATCH 14/15] [DO NOT MERGE] arm64: dts: allwinner: h6: Add GPU OPP table
Add an Operating Performance Points table for the GPU to
enable Dynamic Voltage & Frequency Scaling on the H6.
The voltage range is set with minival voltage set to the target
and the maximal voltage set to 1.2V. This allow DVFS framework to
work properly on board with fixed regulator.
Signed-off-by: Clément Péron
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 80
1 file changed, 80 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index b26f735201c7..85f43a4b651f 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -173,6 +173,7 @@
clocks = < CLK_GPU>, < CLK_BUS_GPU>;
clock-names = "core", "bus";
resets = < RST_BUS_GPU>;
+ operating-points-v2 = <_opp_table>;
#cooling-cells = <2>;
status = "disabled";
};
@@ -1026,4 +1027,83 @@
};
};
};
+
+ gpu_opp_table: gpu-opp-table {
+ compatible = "operating-points-v2";
+
+ opp@21600 {
+ opp-hz = /bits/ 64 <21600>;
+ opp-microvolt = <81 81 120>;
+ };
+
+ opp@26400 {
+ opp-hz = /bits/ 64 <26400>;
+ opp-microvolt = <81 81 120>;
+ };
+
+ opp@31200 {
+ opp-hz = /bits/ 64 <31200>;
+ opp-microvolt = <81 81 120>;
+ };
+
+ opp@33600 {
+ opp-hz = /bits/ 64 <33600>;
+ opp-microvolt = <81 81 120>;
+ };
+
+ opp@36000 {
+ opp-hz = /bits/ 64 <36000>;
+ opp-microvolt = <82 82 120>;
+ };
+
+ opp@38400 {
+ opp-hz = /bits/ 64 <38400>;
+ opp-microvolt = <83 83 120>;
+ };
+
+ opp@40800 {
+ opp-hz = /bits/ 64 <40800>;
+ opp-microvolt = <84 84 120>;
+ };
+
+ opp@42000 {
+ opp-hz = /bits/ 64 <42000>;
+ opp-microvolt = <85 85 120>;
+ };
+
+ opp@43200 {
+ opp-hz = /bits/ 64 <43200>;
+ opp-microvolt = <86 86 120>;
+ };
+
+ opp@45600 {
+ opp-hz = /bits/ 64 <45600>;
+ opp-microvolt = <87 87 120>;
+ };
+
+ opp@50400 {
+ opp-hz = /bits/ 64 <50400>;
+ opp-microvolt = <89 89 120>;
+ };
+
+ opp@54000 {
+ opp-hz = /bits/ 64 <54000>;
+ opp-microvolt = <91 91 120>;
+ };
+
+ opp@57600 {
+ opp-hz = /bits/ 64 <57600>;
+ opp-microvolt = <93 93 120>;
+ };
+
+ opp@62400 {
+ opp-hz = /bits/ 64 <62400>;
+ opp-microvolt = <95 95 120>;
+ };
+
+ opp@75600 {
+ opp-hz = /bits/ 64 <75600>;
+ opp-microvolt = <104 104 120>;
+ };
+ };
};
--
2.20.1
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[PATCH 06/15] drm/panfrost: properly handle error in probe
Introduce a boolean to know if opp table has been added.
With this, we can call panfrost_devfreq_fini() in case of error
and release what has been initialised.
Signed-off-by: Clément Péron
---
drivers/gpu/drm/panfrost/panfrost_devfreq.c | 25 -
drivers/gpu/drm/panfrost/panfrost_devfreq.h | 1 +
2 files changed, 20 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/panfrost/panfrost_devfreq.c
b/drivers/gpu/drm/panfrost/panfrost_devfreq.c
index 78753cfb59fb..d9007f44b772 100644
--- a/drivers/gpu/drm/panfrost/panfrost_devfreq.c
+++ b/drivers/gpu/drm/panfrost/panfrost_devfreq.c
@@ -101,6 +101,7 @@ int panfrost_devfreq_init(struct panfrost_device *pfdev)
return 0;
else if (ret)
return ret;
+ pfdevfreq->opp_of_table_added = true;
spin_lock_init(>lock);
@@ -109,8 +110,10 @@ int panfrost_devfreq_init(struct panfrost_device *pfdev)
cur_freq = clk_get_rate(pfdev->clock);
opp = devfreq_recommended_opp(dev, _freq, 0);
- if (IS_ERR(opp))
- return PTR_ERR(opp);
+ if (IS_ERR(opp)) {
+ ret = PTR_ERR(opp);
+ goto err_fini;
+ }
panfrost_devfreq_profile.initial_freq = cur_freq;
dev_pm_opp_put(opp);
@@ -119,8 +122,8 @@ int panfrost_devfreq_init(struct panfrost_device *pfdev)
DEVFREQ_GOV_SIMPLE_ONDEMAND, NULL);
if (IS_ERR(devfreq)) {
DRM_DEV_ERROR(dev, "Couldn't initialize GPU devfreq\n");
- dev_pm_opp_of_remove_table(dev);
- return PTR_ERR(devfreq);
+ ret = PTR_ERR(devfreq);
+ goto err_fini;
}
pfdevfreq->devfreq = devfreq;
@@ -131,15 +134,25 @@ int panfrost_devfreq_init(struct panfrost_device *pfdev)
pfdevfreq->cooling = cooling;
return 0;
+
+err_fini:
+ panfrost_devfreq_fini(pfdev);
+ return ret;
}
void panfrost_devfreq_fini(struct panfrost_device *pfdev)
{
struct panfrost_devfreq *pfdevfreq = >pfdevfreq;
- if (pfdevfreq->cooling)
+ if (pfdevfreq->cooling) {
devfreq_cooling_unregister(pfdevfreq->cooling);
- dev_pm_opp_of_remove_table(>pdev->dev);
+ pfdevfreq->cooling = NULL;
+ }
+
+ if (pfdevfreq->opp_of_table_added) {
+ dev_pm_opp_of_remove_table(>pdev->dev);
+ pfdevfreq->opp_of_table_added = false;
+ }
}
void panfrost_devfreq_resume(struct panfrost_device *pfdev)
diff --git a/drivers/gpu/drm/panfrost/panfrost_devfreq.h
b/drivers/gpu/drm/panfrost/panfrost_devfreq.h
index e6629900a618..add203cb00c2 100644
--- a/drivers/gpu/drm/panfrost/panfrost_devfreq.h
+++ b/drivers/gpu/drm/panfrost/panfrost_devfreq.h
@@ -15,6 +15,7 @@ struct panfrost_device;
struct panfrost_devfreq {
struct devfreq *devfreq;
struct thermal_cooling_device *cooling;
+ bool opp_of_table_added;
ktime_t busy_time;
ktime_t idle_time;
--
2.20.1
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[PATCH 04/15] drm/panfrost: introduce panfrost_devfreq struct
Introduce a proper panfrost_devfreq to deal with devfreq variables.
Signed-off-by: Clément Péron
---
drivers/gpu/drm/panfrost/panfrost_devfreq.c | 76 -
drivers/gpu/drm/panfrost/panfrost_devfreq.h | 20 +-
drivers/gpu/drm/panfrost/panfrost_device.h | 11 +--
drivers/gpu/drm/panfrost/panfrost_job.c | 6 +-
4 files changed, 66 insertions(+), 47 deletions(-)
diff --git a/drivers/gpu/drm/panfrost/panfrost_devfreq.c
b/drivers/gpu/drm/panfrost/panfrost_devfreq.c
index df7b71da9a84..962550363391 100644
--- a/drivers/gpu/drm/panfrost/panfrost_devfreq.c
+++ b/drivers/gpu/drm/panfrost/panfrost_devfreq.c
@@ -10,23 +10,23 @@
#include "panfrost_device.h"
#include "panfrost_devfreq.h"
-static void panfrost_devfreq_update_utilization(struct panfrost_device *pfdev)
+static void panfrost_devfreq_update_utilization(struct panfrost_devfreq
*pfdevfreq)
{
ktime_t now;
ktime_t last;
- if (!pfdev->devfreq.devfreq)
+ if (!pfdevfreq->devfreq)
return;
now = ktime_get();
- last = pfdev->devfreq.time_last_update;
+ last = pfdevfreq->time_last_update;
- if (atomic_read(>devfreq.busy_count) > 0)
- pfdev->devfreq.busy_time += ktime_sub(now, last);
+ if (atomic_read(>busy_count) > 0)
+ pfdevfreq->busy_time += ktime_sub(now, last);
else
- pfdev->devfreq.idle_time += ktime_sub(now, last);
+ pfdevfreq->idle_time += ktime_sub(now, last);
- pfdev->devfreq.time_last_update = now;
+ pfdevfreq->time_last_update = now;
}
static int panfrost_devfreq_target(struct device *dev, unsigned long *freq,
@@ -47,30 +47,31 @@ static int panfrost_devfreq_target(struct device *dev,
unsigned long *freq,
return 0;
}
-static void panfrost_devfreq_reset(struct panfrost_device *pfdev)
+static void panfrost_devfreq_reset(struct panfrost_devfreq *pfdevfreq)
{
- pfdev->devfreq.busy_time = 0;
- pfdev->devfreq.idle_time = 0;
- pfdev->devfreq.time_last_update = ktime_get();
+ pfdevfreq->busy_time = 0;
+ pfdevfreq->idle_time = 0;
+ pfdevfreq->time_last_update = ktime_get();
}
static int panfrost_devfreq_get_dev_status(struct device *dev,
struct devfreq_dev_status *status)
{
struct panfrost_device *pfdev = dev_get_drvdata(dev);
+ struct panfrost_devfreq *pfdevfreq = >pfdevfreq;
- panfrost_devfreq_update_utilization(pfdev);
+ panfrost_devfreq_update_utilization(pfdevfreq);
status->current_frequency = clk_get_rate(pfdev->clock);
- status->total_time = ktime_to_ns(ktime_add(pfdev->devfreq.busy_time,
- pfdev->devfreq.idle_time));
+ status->total_time = ktime_to_ns(ktime_add(pfdevfreq->busy_time,
+ pfdevfreq->idle_time));
- status->busy_time = ktime_to_ns(pfdev->devfreq.busy_time);
+ status->busy_time = ktime_to_ns(pfdevfreq->busy_time);
- panfrost_devfreq_reset(pfdev);
+ panfrost_devfreq_reset(pfdevfreq);
- dev_dbg(pfdev->dev, "busy %lu total %lu %lu %% freq %lu MHz\n",
status->busy_time,
- status->total_time,
+ dev_dbg(pfdev->dev, "busy %lu total %lu %lu %% freq %lu MHz\n",
+ status->busy_time, status->total_time,
status->busy_time / (status->total_time / 100),
status->current_frequency / 1000 / 1000);
@@ -91,6 +92,7 @@ int panfrost_devfreq_init(struct panfrost_device *pfdev)
struct device *dev = >pdev->dev;
struct devfreq *devfreq;
struct thermal_cooling_device *cooling;
+ struct panfrost_devfreq *pfdevfreq = >pfdevfreq;
ret = dev_pm_opp_of_add_table(dev);
if (ret == -ENODEV) /* Optional, continue without devfreq */
@@ -98,7 +100,7 @@ int panfrost_devfreq_init(struct panfrost_device *pfdev)
else if (ret)
return ret;
- panfrost_devfreq_reset(pfdev);
+ panfrost_devfreq_reset(pfdevfreq);
cur_freq = clk_get_rate(pfdev->clock);
@@ -116,53 +118,59 @@ int panfrost_devfreq_init(struct panfrost_device *pfdev)
dev_pm_opp_of_remove_table(dev);
return PTR_ERR(devfreq);
}
- pfdev->devfreq.devfreq = devfreq;
+ pfdevfreq->devfreq = devfreq;
cooling = of_devfreq_cooling_register(dev->of_node, devfreq);
if (IS_ERR(cooling))
DRM_DEV_INFO(dev, "Failed to register cooling device\n");
else
- pfdev->devfreq.cooling = cooling;
+ pfdevfreq->cooling = cooling;
return 0;
}
void panfrost_devfreq_fini(struct panfrost_device *
[PATCH 12/15] arm64: defconfig: Enable devfreq cooling device
Devfreq cooling device framework is used in Panfrost to throttle GPU in order to regulate its temperature. Enable this driver for ARM64 SoC. Signed-off-by: Clément Péron --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 66941024418c..42d85c2c0945 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -496,6 +496,7 @@ CONFIG_SENSORS_INA2XX=m CONFIG_SENSORS_INA3221=m CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y CONFIG_CPU_THERMAL=y +CONFIG_DEVFREQ_THERMAL=y CONFIG_THERMAL_EMULATION=y CONFIG_QORIQ_THERMAL=m CONFIG_SUN8I_THERMAL=y -- 2.20.1 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 11/15] drm/panfrost: set devfreq clock name
Some SoCs have several clocks defined and the OPP core
needs to know the exact name of the clk to use.
Set the clock name to "core".
Signed-off-by: Clément Péron
---
drivers/gpu/drm/panfrost/panfrost_devfreq.c | 13 +
drivers/gpu/drm/panfrost/panfrost_devfreq.h | 1 +
2 files changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/panfrost/panfrost_devfreq.c
b/drivers/gpu/drm/panfrost/panfrost_devfreq.c
index 9ffea0d4a087..6bf3541b4d53 100644
--- a/drivers/gpu/drm/panfrost/panfrost_devfreq.c
+++ b/drivers/gpu/drm/panfrost/panfrost_devfreq.c
@@ -103,6 +103,14 @@ int panfrost_devfreq_init(struct panfrost_device *pfdev)
spin_lock_init(>lock);
+ opp_table = dev_pm_opp_set_clkname(dev, "core");
+ if (IS_ERR(opp_table)) {
+ ret = PTR_ERR(opp_table);
+ goto err_fini;
+ }
+
+ pfdevfreq->clkname_opp_table = opp_table;
+
opp_table = dev_pm_opp_set_regulators(dev, pfdev->comp->supply_names,
pfdev->comp->num_supplies);
if (IS_ERR(opp_table)) {
@@ -176,6 +184,11 @@ void panfrost_devfreq_fini(struct panfrost_device *pfdev)
dev_pm_opp_put_regulators(pfdevfreq->regulators_opp_table);
pfdevfreq->regulators_opp_table = NULL;
}
+
+ if (pfdevfreq->clkname_opp_table) {
+ dev_pm_opp_put_clkname(pfdevfreq->clkname_opp_table);
+ pfdevfreq->clkname_opp_table = NULL;
+ }
}
void panfrost_devfreq_resume(struct panfrost_device *pfdev)
diff --git a/drivers/gpu/drm/panfrost/panfrost_devfreq.h
b/drivers/gpu/drm/panfrost/panfrost_devfreq.h
index 347cde4786cf..1f2475e1d034 100644
--- a/drivers/gpu/drm/panfrost/panfrost_devfreq.h
+++ b/drivers/gpu/drm/panfrost/panfrost_devfreq.h
@@ -16,6 +16,7 @@ struct panfrost_device;
struct panfrost_devfreq {
struct devfreq *devfreq;
struct opp_table *regulators_opp_table;
+ struct opp_table *clkname_opp_table;
struct thermal_cooling_device *cooling;
bool opp_of_table_added;
--
2.20.1
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[PATCH 02/15] drm/panfrost: clean headers in devfreq
Don't include not required headers and sort them.
Signed-off-by: Clément Péron
---
drivers/gpu/drm/panfrost/panfrost_devfreq.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/panfrost/panfrost_devfreq.c
b/drivers/gpu/drm/panfrost/panfrost_devfreq.c
index 1b560b903ea6..df7b71da9a84 100644
--- a/drivers/gpu/drm/panfrost/panfrost_devfreq.c
+++ b/drivers/gpu/drm/panfrost/panfrost_devfreq.c
@@ -1,18 +1,14 @@
// SPDX-License-Identifier: GPL-2.0
/* Copyright 2019 Collabora ltd. */
+
+#include
#include
#include
#include
#include
-#include
-#include
#include "panfrost_device.h"
#include "panfrost_devfreq.h"
-#include "panfrost_features.h"
-#include "panfrost_issues.h"
-#include "panfrost_gpu.h"
-#include "panfrost_regs.h"
static void panfrost_devfreq_update_utilization(struct panfrost_device *pfdev)
{
--
2.20.1
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[PATCH 07/15] drm/panfrost: use device_property_present to check for OPP
Instead of expecting an error from dev_pm_opp_of_add_table()
do a simple device_property_present() check.
Signed-off-by: Clément Péron
---
drivers/gpu/drm/panfrost/panfrost_devfreq.c | 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/panfrost/panfrost_devfreq.c
b/drivers/gpu/drm/panfrost/panfrost_devfreq.c
index d9007f44b772..fce21c682414 100644
--- a/drivers/gpu/drm/panfrost/panfrost_devfreq.c
+++ b/drivers/gpu/drm/panfrost/panfrost_devfreq.c
@@ -96,15 +96,19 @@ int panfrost_devfreq_init(struct panfrost_device *pfdev)
struct thermal_cooling_device *cooling;
struct panfrost_devfreq *pfdevfreq = >pfdevfreq;
- ret = dev_pm_opp_of_add_table(dev);
- if (ret == -ENODEV) /* Optional, continue without devfreq */
+ if (!device_property_present(dev, "operating-points-v2"))
+ /* Optional, continue without devfreq */
return 0;
- else if (ret)
- return ret;
- pfdevfreq->opp_of_table_added = true;
spin_lock_init(>lock);
+ ret = dev_pm_opp_of_add_table(dev);
+ if (ret) {
+ DRM_DEV_ERROR(dev, "Couldn't add OPP table\n");
+ goto err_fini;
+ }
+ pfdevfreq->opp_of_table_added = true;
+
panfrost_devfreq_reset(pfdevfreq);
cur_freq = clk_get_rate(pfdev->clock);
--
2.20.1
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Re: [PATCH 2/2] drm/panfrost: add devfreq regulator support
On Sat, 9 May 2020 at 18:28, Clément Péron wrote: > > Hi Steven, > > On Thu, 7 May 2020 at 16:30, Steven Price wrote: > > > > On 02/05/2020 23:07, Clément Péron wrote: > > > Hi Steven, > > > > > > On Tue, 14 Apr 2020 at 15:10, Steven Price wrote: > > >> > > >> Hi Clément, > > >> > > >> On 13/04/2020 18:28, Clément Péron wrote: > > >>> Hi Steven, > > >>> > > > > > > > > Since you've got a reproduction - can you get a backtrace where the > > regulator is getting disabled? > > Regulator is disabled from regulator_late_cleanup() > > [ 33.757650] vdd-gpu: disabling > [ 33.760718] CPU: 2 PID: 31 Comm: kworker/2:1 Not tainted > 5.7.0-rc2-next-20200424 #8 > [ 33.768362] Hardware name: Beelink GS1 (DT) > [ 33.772553] Workqueue: events regulator_init_complete_work_function > [ 33.778813] Call trace: > [ 33.781261] dump_backtrace+0x0/0x1a0 > [ 33.784922] show_stack+0x18/0x30 > [ 33.788238] dump_stack+0xc0/0x114 > [ 33.791638] regulator_late_cleanup+0x164/0x1f0 > [ 33.796165] class_for_each_device+0x64/0xe0 > [ 33.800431] regulator_init_complete_work_function+0x4c/0x60 > [ 33.806084] process_one_work+0x19c/0x330 > [ 33.810090] worker_thread+0x4c/0x430 > [ 33.813748] kthread+0x138/0x160 > [ 33.816973] ret_from_fork+0x10/0x24 > > the use_count is at 0... > > I have check and the regulator_get is called and regulator_put is > never called for vdd-gpu. > Not sure what is happening here... Looks like the OPP framework only get the regulator but never enable it... I will send a question to OPP Maintainer about this. Regards, CLement > > > > > > > - The Cooling map is not probe correctly : > > > [2.545756] panfrost 180.gpu: [drm:panfrost_devfreq_init > > > [panfrost]] Failed to register cooling device > > > Introduce in this commit : > > > https://github.com/clementperon/linux/commit/0252c38fd55ad78366ac4b1714e285c88db34557 > > > > > > Do you have an hint about what I'm missing ? > > > > Sorry, my knowledge of the cooling framework is very limited. What > > you've got looks plausible, but I'm afraid I can't really help beyond > > that! As before - can you try adding some printk()s in e.g. > > of_devfreq_cooling_register_power() and find out where it is bailing out? > > Dumb issue, I was missing the CONFIG_DEVFREQ_THERMAL -_-, I will make > a patch to enable it in arm64 defconfig. > > Regards, > Clement > > > > > Steve ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 05/15] drm/panfrost: use spinlock instead of atomic
Convert busy_count to a simple int protected by spinlock.
Signed-off-by: Clément Péron
---
drivers/gpu/drm/panfrost/panfrost_devfreq.c | 43 +++--
drivers/gpu/drm/panfrost/panfrost_devfreq.h | 10 -
2 files changed, 41 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/panfrost/panfrost_devfreq.c
b/drivers/gpu/drm/panfrost/panfrost_devfreq.c
index 962550363391..78753cfb59fb 100644
--- a/drivers/gpu/drm/panfrost/panfrost_devfreq.c
+++ b/drivers/gpu/drm/panfrost/panfrost_devfreq.c
@@ -12,16 +12,12 @@
static void panfrost_devfreq_update_utilization(struct panfrost_devfreq
*pfdevfreq)
{
- ktime_t now;
- ktime_t last;
-
- if (!pfdevfreq->devfreq)
- return;
+ ktime_t now, last;
now = ktime_get();
last = pfdevfreq->time_last_update;
- if (atomic_read(>busy_count) > 0)
+ if (pfdevfreq->busy_count > 0)
pfdevfreq->busy_time += ktime_sub(now, last);
else
pfdevfreq->idle_time += ktime_sub(now, last);
@@ -59,10 +55,14 @@ static int panfrost_devfreq_get_dev_status(struct device
*dev,
{
struct panfrost_device *pfdev = dev_get_drvdata(dev);
struct panfrost_devfreq *pfdevfreq = >pfdevfreq;
+ unsigned long irqflags;
+
+ status->current_frequency = clk_get_rate(pfdev->clock);
+
+ spin_lock_irqsave(>lock, irqflags);
panfrost_devfreq_update_utilization(pfdevfreq);
- status->current_frequency = clk_get_rate(pfdev->clock);
status->total_time = ktime_to_ns(ktime_add(pfdevfreq->busy_time,
pfdevfreq->idle_time));
@@ -70,6 +70,8 @@ static int panfrost_devfreq_get_dev_status(struct device *dev,
panfrost_devfreq_reset(pfdevfreq);
+ spin_unlock_irqrestore(>lock, irqflags);
+
dev_dbg(pfdev->dev, "busy %lu total %lu %lu %% freq %lu MHz\n",
status->busy_time, status->total_time,
status->busy_time / (status->total_time / 100),
@@ -100,6 +102,8 @@ int panfrost_devfreq_init(struct panfrost_device *pfdev)
else if (ret)
return ret;
+ spin_lock_init(>lock);
+
panfrost_devfreq_reset(pfdevfreq);
cur_freq = clk_get_rate(pfdev->clock);
@@ -162,15 +166,32 @@ void panfrost_devfreq_suspend(struct panfrost_device
*pfdev)
void panfrost_devfreq_record_busy(struct panfrost_devfreq *pfdevfreq)
{
+ unsigned long irqflags;
+
+ if (!pfdevfreq->devfreq)
+ return;
+
+ spin_lock_irqsave(>lock, irqflags);
+
panfrost_devfreq_update_utilization(pfdevfreq);
- atomic_inc(>busy_count);
+
+ pfdevfreq->busy_count++;
+
+ spin_unlock_irqrestore(>lock, irqflags);
}
void panfrost_devfreq_record_idle(struct panfrost_devfreq *pfdevfreq)
{
- int count;
+ unsigned long irqflags;
+
+ if (!pfdevfreq->devfreq)
+ return;
+
+ spin_lock_irqsave(>lock, irqflags);
panfrost_devfreq_update_utilization(pfdevfreq);
- count = atomic_dec_if_positive(>busy_count);
- WARN_ON(count < 0);
+
+ WARN_ON(--pfdevfreq->busy_count < 0);
+
+ spin_unlock_irqrestore(>lock, irqflags);
}
diff --git a/drivers/gpu/drm/panfrost/panfrost_devfreq.h
b/drivers/gpu/drm/panfrost/panfrost_devfreq.h
index 0697f8d5aa34..e6629900a618 100644
--- a/drivers/gpu/drm/panfrost/panfrost_devfreq.h
+++ b/drivers/gpu/drm/panfrost/panfrost_devfreq.h
@@ -4,6 +4,7 @@
#ifndef __PANFROST_DEVFREQ_H__
#define __PANFROST_DEVFREQ_H__
+#include
#include
struct devfreq;
@@ -14,10 +15,17 @@ struct panfrost_device;
struct panfrost_devfreq {
struct devfreq *devfreq;
struct thermal_cooling_device *cooling;
+
ktime_t busy_time;
ktime_t idle_time;
ktime_t time_last_update;
- atomic_t busy_count;
+ int busy_count;
+ /*
+* Protect busy_time, idle_time, time_last_update and busy_count
+* because these can be updated concurrently, for example by the GP
+* and PP interrupts.
+*/
+ spinlock_t lock;
};
int panfrost_devfreq_init(struct panfrost_device *pfdev);
--
2.20.1
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[PATCH 09/15] drm/panfrost: dynamically alloc regulators
We will later introduce regulators managed by OPP.
Only alloc regulators when it's needed. This also help use
to release the regulators only when they are allocated.
Signed-off-by: Clément Péron
---
drivers/gpu/drm/panfrost/panfrost_device.c | 14 +-
drivers/gpu/drm/panfrost/panfrost_device.h | 3 +--
2 files changed, 10 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/panfrost/panfrost_device.c
b/drivers/gpu/drm/panfrost/panfrost_device.c
index f480127205d6..67eedf64e82d 100644
--- a/drivers/gpu/drm/panfrost/panfrost_device.c
+++ b/drivers/gpu/drm/panfrost/panfrost_device.c
@@ -90,9 +90,11 @@ static int panfrost_regulator_init(struct panfrost_device
*pfdev)
{
int ret, i;
- if (WARN(pfdev->comp->num_supplies > ARRAY_SIZE(pfdev->regulators),
- "Too many supplies in compatible structure.\n"))
- return -EINVAL;
+ pfdev->regulators = devm_kcalloc(pfdev->dev, pfdev->comp->num_supplies,
+sizeof(*pfdev->regulators),
+GFP_KERNEL);
+ if (!pfdev->regulators)
+ return -ENOMEM;
for (i = 0; i < pfdev->comp->num_supplies; i++)
pfdev->regulators[i].supply = pfdev->comp->supply_names[i];
@@ -117,8 +119,10 @@ static int panfrost_regulator_init(struct panfrost_device
*pfdev)
static void panfrost_regulator_fini(struct panfrost_device *pfdev)
{
- regulator_bulk_disable(pfdev->comp->num_supplies,
- pfdev->regulators);
+ if (!pfdev->regulators)
+ return;
+
+ regulator_bulk_disable(pfdev->comp->num_supplies, pfdev->regulators);
}
static void panfrost_pm_domain_fini(struct panfrost_device *pfdev)
diff --git a/drivers/gpu/drm/panfrost/panfrost_device.h
b/drivers/gpu/drm/panfrost/panfrost_device.h
index 2efa59c9d1c5..953f7536a773 100644
--- a/drivers/gpu/drm/panfrost/panfrost_device.h
+++ b/drivers/gpu/drm/panfrost/panfrost_device.h
@@ -22,7 +22,6 @@ struct panfrost_job;
struct panfrost_perfcnt;
#define NUM_JOB_SLOTS 3
-#define MAX_REGULATORS 2
#define MAX_PM_DOMAINS 3
struct panfrost_features {
@@ -81,7 +80,7 @@ struct panfrost_device {
void __iomem *iomem;
struct clk *clock;
struct clk *bus_clock;
- struct regulator_bulk_data regulators[MAX_REGULATORS];
+ struct regulator_bulk_data *regulators;
struct reset_control *rstc;
/* pm_domains for devices with more than one. */
struct device *pm_domain_devs[MAX_PM_DOMAINS];
--
2.20.1
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[PATCH 03/15] drm/panfrost: don't use pfdevfreq.busy_count to know if hw is idle
This use devfreq variable that will be lock with spinlock in future
patches. We should either introduce a function to access this one
but as devfreq is optional let's just remove it.
Signed-off-by: Clément Péron
---
drivers/gpu/drm/panfrost/panfrost_job.c | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/gpu/drm/panfrost/panfrost_job.c
b/drivers/gpu/drm/panfrost/panfrost_job.c
index 7914b1570841..63e32a9f2749 100644
--- a/drivers/gpu/drm/panfrost/panfrost_job.c
+++ b/drivers/gpu/drm/panfrost/panfrost_job.c
@@ -581,10 +581,6 @@ int panfrost_job_is_idle(struct panfrost_device *pfdev)
struct panfrost_job_slot *js = pfdev->js;
int i;
- /* Check whether the hardware is idle */
- if (atomic_read(>devfreq.busy_count))
- return false;
-
for (i = 0; i < NUM_JOB_SLOTS; i++) {
/* If there are any jobs in the HW queue, we're not idle */
if (atomic_read(>queue[i].sched.hw_rq_count))
--
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[PATCH 00/15][RFC] Add regulator devfreq support to Panfrost
Hi, This serie cleans and adds regulator support to Panfrost devfreq. This is mostly based on comment for the freshly introduced lima devfreq. We need to add regulator support because on Allwinner the GPU OPP table defines both frequencies and voltages. First patches [01-08] should not change the actual behavior and introduce a proper panfrost_devfreq struct. Fatches after are WIP and add regulator support. However I got several issues first we need to avoid getting regulator if devfreq get by itself the regulator, but as of today the OPP framework only get and don't enable the regulator... An HACK for now is to add regulator-always-on in the device-tree. Then when I enable devfreq I got several faults like. I'm totally noob on GPU sched/fault and couldn't be helpfull with this. I got this running glmark2 on T720 (Allwinner H6) with Mesa 20.0.5. # glmark2-es2-drm === glmark2 2017.07 === OpenGL Information GL_VENDOR: Panfrost GL_RENDERER: Mali T720 (Panfrost) GL_VERSION:OpenGL ES 2.0 Mesa 20.0.5 === [ 93.550063] panfrost 180.gpu: GPU Fault 0x0088 (UNKNOWN) at 0x80117100 [ 94.045401] panfrost 180.gpu: gpu sched timeout, js=0, config=0x3700, status=0x8, head=0x21d6c00, tail=0x21d6c00, sched_job=e3c2132f [ 328.871070] panfrost 180.gpu: Unhandled Page fault in AS0 at VA 0x [ 328.871070] Reason: TODO [ 328.871070] raw fault status: 0xAA0003C2 [ 328.871070] decoded fault status: SLAVE FAULT [ 328.871070] exception type 0xC2: TRANSLATION_FAULT_LEVEL2 [ 328.871070] access type 0x3: WRITE [ 328.871070] source id 0xAA00 [ 329.373327] panfrost 180.gpu: gpu sched timeout, js=1, config=0x3700, status=0x8, head=0xa1a4900, tail=0xa1a4900, sched_job=7ac31097 [ 329.386527] panfrost 180.gpu: js fault, js=0, status=DATA_INVALID_FAULT, head=0xa1a4c00, tail=0xa1a4c00 [ 329.396293] panfrost 180.gpu: gpu sched timeout, js=0, config=0x3700, status=0x58, head=0xa1a4c00, tail=0xa1a4c00, sched_job=04c90381 [ 329.411521] panfrost 180.gpu: Unhandled Page fault in AS0 at VA 0x [ 329.411521] Reason: TODO [ 329.411521] raw fault status: 0xAA0003C2 [ 329.411521] decoded fault status: SLAVE FAULT [ 329.411521] exception type 0xC2: TRANSLATION_FAULT_LEVEL2 [ 329.411521] access type 0x3: WRITE [ 329.411521] source id 0xAA00 Thanks for your reviews, help on this serie, Clement Clément Péron (15): drm/panfrost: avoid static declaration drm/panfrost: clean headers in devfreq drm/panfrost: don't use pfdevfreq.busy_count to know if hw is idle drm/panfrost: introduce panfrost_devfreq struct drm/panfrost: use spinlock instead of atomic drm/panfrost: properly handle error in probe drm/panfrost: use device_property_present to check for OPP drm/panfrost: move devfreq_init()/fini() in device drm/panfrost: dynamically alloc regulators drm/panfrost: add regulators to devfreq drm/panfrost: set devfreq clock name arm64: defconfig: Enable devfreq cooling device arm64: dts: allwinner: h6: Add cooling map for GPU [DO NOT MERGE] arm64: dts: allwinner: h6: Add GPU OPP table [DO NOT MERGE] arm64: dts: allwinner: force GPU regulator to be always .../dts/allwinner/sun50i-h6-beelink-gs1.dts | 1 + arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 102 ++ arch/arm64/configs/defconfig | 1 + drivers/gpu/drm/panfrost/panfrost_devfreq.c | 190 -- drivers/gpu/drm/panfrost/panfrost_devfreq.h | 32 ++- drivers/gpu/drm/panfrost/panfrost_device.c| 56 -- drivers/gpu/drm/panfrost/panfrost_device.h| 14 +- drivers/gpu/drm/panfrost/panfrost_drv.c | 15 +- drivers/gpu/drm/panfrost/panfrost_job.c | 10 +- 9 files changed, 310 insertions(+), 111 deletions(-) -- 2.20.1 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 08/15] drm/panfrost: move devfreq_init()/fini() in device
Later we will introduce devfreq probing regulator if they
are present. As regulator should be probe only one time we
need to get this logic in the device_init().
panfrost_device is already taking care of devfreq_resume()
and devfreq_suspend(), so it's not totally illogic to move
the devfreq_init() and devfreq_fini() here.
Signed-off-by: Clément Péron
---
drivers/gpu/drm/panfrost/panfrost_device.c | 37 ++
drivers/gpu/drm/panfrost/panfrost_drv.c| 15 ++---
2 files changed, 25 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/panfrost/panfrost_device.c
b/drivers/gpu/drm/panfrost/panfrost_device.c
index 8136babd3ba9..f480127205d6 100644
--- a/drivers/gpu/drm/panfrost/panfrost_device.c
+++ b/drivers/gpu/drm/panfrost/panfrost_device.c
@@ -212,59 +212,67 @@ int panfrost_device_init(struct panfrost_device *pfdev)
return err;
}
+ err = panfrost_devfreq_init(pfdev);
+ if (err) {
+ dev_err(pfdev->dev, "devfreq init failed %d\n", err);
+ goto err_out0;
+ }
+
err = panfrost_regulator_init(pfdev);
if (err) {
dev_err(pfdev->dev, "regulator init failed %d\n", err);
- goto err_out0;
+ goto err_out1;
}
err = panfrost_reset_init(pfdev);
if (err) {
dev_err(pfdev->dev, "reset init failed %d\n", err);
- goto err_out1;
+ goto err_out2;
}
err = panfrost_pm_domain_init(pfdev);
if (err)
- goto err_out2;
+ goto err_out3;
res = platform_get_resource(pfdev->pdev, IORESOURCE_MEM, 0);
pfdev->iomem = devm_ioremap_resource(pfdev->dev, res);
if (IS_ERR(pfdev->iomem)) {
dev_err(pfdev->dev, "failed to ioremap iomem\n");
err = PTR_ERR(pfdev->iomem);
- goto err_out3;
+ goto err_out4;
}
err = panfrost_gpu_init(pfdev);
if (err)
- goto err_out3;
+ goto err_out4;
err = panfrost_mmu_init(pfdev);
if (err)
- goto err_out4;
+ goto err_out5;
err = panfrost_job_init(pfdev);
if (err)
- goto err_out5;
+ goto err_out6;
err = panfrost_perfcnt_init(pfdev);
if (err)
- goto err_out6;
+ goto err_out7;
return 0;
-err_out6:
+err_out7:
panfrost_job_fini(pfdev);
-err_out5:
+err_out6:
panfrost_mmu_fini(pfdev);
-err_out4:
+err_out5:
panfrost_gpu_fini(pfdev);
-err_out3:
+err_out4:
panfrost_pm_domain_fini(pfdev);
-err_out2:
+err_out3:
panfrost_reset_fini(pfdev);
-err_out1:
+err_out2:
panfrost_regulator_fini(pfdev);
+err_out1:
+ panfrost_devfreq_fini(pfdev);
err_out0:
panfrost_clk_fini(pfdev);
return err;
@@ -278,6 +286,7 @@ void panfrost_device_fini(struct panfrost_device *pfdev)
panfrost_gpu_fini(pfdev);
panfrost_pm_domain_fini(pfdev);
panfrost_reset_fini(pfdev);
+ panfrost_devfreq_fini(pfdev);
panfrost_regulator_fini(pfdev);
panfrost_clk_fini(pfdev);
}
diff --git a/drivers/gpu/drm/panfrost/panfrost_drv.c
b/drivers/gpu/drm/panfrost/panfrost_drv.c
index 882fecc33fdb..4dda68689015 100644
--- a/drivers/gpu/drm/panfrost/panfrost_drv.c
+++ b/drivers/gpu/drm/panfrost/panfrost_drv.c
@@ -14,7 +14,6 @@
#include
#include "panfrost_device.h"
-#include "panfrost_devfreq.h"
#include "panfrost_gem.h"
#include "panfrost_mmu.h"
#include "panfrost_job.h"
@@ -606,13 +605,6 @@ static int panfrost_probe(struct platform_device *pdev)
goto err_out0;
}
- err = panfrost_devfreq_init(pfdev);
- if (err) {
- if (err != -EPROBE_DEFER)
- dev_err(>dev, "Fatal error during devfreq
init\n");
- goto err_out1;
- }
-
pm_runtime_set_active(pfdev->dev);
pm_runtime_mark_last_busy(pfdev->dev);
pm_runtime_enable(pfdev->dev);
@@ -625,16 +617,14 @@ static int panfrost_probe(struct platform_device *pdev)
*/
err = drm_dev_register(ddev, 0);
if (err < 0)
- goto err_out2;
+ goto err_out1;
panfrost_gem_shrinker_init(ddev);
return 0;
-err_out2:
- pm_runtime_disable(pfdev->dev);
- panfrost_devfreq_fini(pfdev);
err_out1:
+ pm_runtime_disable(pfdev->dev);
panfrost_device_fini(pfdev);
err_out0:
drm_dev_put(ddev);
@@ -650,7 +640,6 @@ static int panfrost_remove(struct platform_device *pdev)
panfrost_gem_shrinker_cleanup(ddev);
pm_runtime_get_sync(pfdev->dev);
- panfrost_devfre
Re: [PATCH 2/2] drm/panfrost: add devfreq regulator support
Hi Steven, On Thu, 7 May 2020 at 16:30, Steven Price wrote: > > On 02/05/2020 23:07, Clément Péron wrote: > > Hi Steven, > > > > On Tue, 14 Apr 2020 at 15:10, Steven Price wrote: > >> > >> Hi Clément, > >> > >> On 13/04/2020 18:28, Clément Péron wrote: > >>> Hi Steven, > >>> > > > > Since you've got a reproduction - can you get a backtrace where the > regulator is getting disabled? Regulator is disabled from regulator_late_cleanup() [ 33.757650] vdd-gpu: disabling [ 33.760718] CPU: 2 PID: 31 Comm: kworker/2:1 Not tainted 5.7.0-rc2-next-20200424 #8 [ 33.768362] Hardware name: Beelink GS1 (DT) [ 33.772553] Workqueue: events regulator_init_complete_work_function [ 33.778813] Call trace: [ 33.781261] dump_backtrace+0x0/0x1a0 [ 33.784922] show_stack+0x18/0x30 [ 33.788238] dump_stack+0xc0/0x114 [ 33.791638] regulator_late_cleanup+0x164/0x1f0 [ 33.796165] class_for_each_device+0x64/0xe0 [ 33.800431] regulator_init_complete_work_function+0x4c/0x60 [ 33.806084] process_one_work+0x19c/0x330 [ 33.810090] worker_thread+0x4c/0x430 [ 33.813748] kthread+0x138/0x160 [ 33.816973] ret_from_fork+0x10/0x24 the use_count is at 0... I have check and the regulator_get is called and regulator_put is never called for vdd-gpu. Not sure what is happening here... > > > - The Cooling map is not probe correctly : > > [2.545756] panfrost 180.gpu: [drm:panfrost_devfreq_init > > [panfrost]] Failed to register cooling device > > Introduce in this commit : > > https://github.com/clementperon/linux/commit/0252c38fd55ad78366ac4b1714e285c88db34557 > > > > Do you have an hint about what I'm missing ? > > Sorry, my knowledge of the cooling framework is very limited. What > you've got looks plausible, but I'm afraid I can't really help beyond > that! As before - can you try adding some printk()s in e.g. > of_devfreq_cooling_register_power() and find out where it is bailing out? Dumb issue, I was missing the CONFIG_DEVFREQ_THERMAL -_-, I will make a patch to enable it in arm64 defconfig. Regards, Clement > > Steve ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 01/15] drm/panfrost: avoid static declaration
This declaration can be avoided so change it.
Signed-off-by: Clément Péron
---
drivers/gpu/drm/panfrost/panfrost_devfreq.c | 38 ++---
1 file changed, 18 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/panfrost/panfrost_devfreq.c
b/drivers/gpu/drm/panfrost/panfrost_devfreq.c
index 413987038fbf..1b560b903ea6 100644
--- a/drivers/gpu/drm/panfrost/panfrost_devfreq.c
+++ b/drivers/gpu/drm/panfrost/panfrost_devfreq.c
@@ -14,7 +14,24 @@
#include "panfrost_gpu.h"
#include "panfrost_regs.h"
-static void panfrost_devfreq_update_utilization(struct panfrost_device *pfdev);
+static void panfrost_devfreq_update_utilization(struct panfrost_device *pfdev)
+{
+ ktime_t now;
+ ktime_t last;
+
+ if (!pfdev->devfreq.devfreq)
+ return;
+
+ now = ktime_get();
+ last = pfdev->devfreq.time_last_update;
+
+ if (atomic_read(>devfreq.busy_count) > 0)
+ pfdev->devfreq.busy_time += ktime_sub(now, last);
+ else
+ pfdev->devfreq.idle_time += ktime_sub(now, last);
+
+ pfdev->devfreq.time_last_update = now;
+}
static int panfrost_devfreq_target(struct device *dev, unsigned long *freq,
u32 flags)
@@ -139,25 +156,6 @@ void panfrost_devfreq_suspend(struct panfrost_device
*pfdev)
devfreq_suspend_device(pfdev->devfreq.devfreq);
}
-static void panfrost_devfreq_update_utilization(struct panfrost_device *pfdev)
-{
- ktime_t now;
- ktime_t last;
-
- if (!pfdev->devfreq.devfreq)
- return;
-
- now = ktime_get();
- last = pfdev->devfreq.time_last_update;
-
- if (atomic_read(>devfreq.busy_count) > 0)
- pfdev->devfreq.busy_time += ktime_sub(now, last);
- else
- pfdev->devfreq.idle_time += ktime_sub(now, last);
-
- pfdev->devfreq.time_last_update = now;
-}
-
void panfrost_devfreq_record_busy(struct panfrost_device *pfdev)
{
panfrost_devfreq_update_utilization(pfdev);
--
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Re: [PATCH 2/2] drm/panfrost: add devfreq regulator support
Hi Steven, On Tue, 14 Apr 2020 at 15:10, Steven Price wrote: > > Hi Clément, > > On 13/04/2020 18:28, Clément Péron wrote: > > Hi Steven, > > > Getting a backtrace from the two occurrences, I see one added from: > >(debugfs_create_dir) from [] (create_regulator+0xe0/0x220) >(create_regulator) from [] (_regulator_get+0x168/0x204) >(_regulator_get) from [] (regulator_bulk_get+0x64/0xf4) >(regulator_bulk_get) from [] > (devm_regulator_bulk_get+0x40/0x74) >(devm_regulator_bulk_get) from [] > (panfrost_device_init+0x1b4/0x48c [panfrost]) >(panfrost_device_init [panfrost]) from [] > (panfrost_probe+0x94/0x184 [panfrost]) >(panfrost_probe [panfrost]) from [] > (platform_drv_probe+0x48/0x94) > > And the other: > >(debugfs_create_dir) from [] (create_regulator+0xe0/0x220) >(create_regulator) from [] (_regulator_get+0x168/0x204) >(_regulator_get) from [] (dev_pm_opp_set_regulators+0x6c/0x184) >(dev_pm_opp_set_regulators) from [] > (panfrost_devfreq_init+0x38/0x1ac [panfrost]) >(panfrost_devfreq_init [panfrost]) from [] > (panfrost_probe+0xc8/0x184 [panfrost]) >(panfrost_probe [panfrost]) from [] > (platform_drv_probe+0x48/0x94) > > Both are created at /regulator/vdd_gpu I'm preparing a new version with some clean from lima devfreq. My working branch : https://github.com/clementperon/linux/commits/panfrost_devfreq Two strange things I observe: - After 30sec the regulator is released by OPP ??? [ 33.757627] vdd-gpu: disabling Introduce the regulator support in this commit: https://github.com/clementperon/linux/commit/be310c37b82010e293b7f129ccdcb711a2abb2ce - The Cooling map is not probe correctly : [2.545756] panfrost 180.gpu: [drm:panfrost_devfreq_init [panfrost]] Failed to register cooling device Introduce in this commit : https://github.com/clementperon/linux/commit/0252c38fd55ad78366ac4b1714e285c88db34557 Do you have an hint about what I'm missing ? Thanks for your help, Clement ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: devfreq and panfrost on Allwinner H6
Hi Tomeu, On Wed, 7 Oct 2020 at 10:58, Tomeu Vizoso wrote: > > Hi Clément, > > Have just noticed that my Pine H64 board hangs when I try to set the > performance governor for the GPU devfreq. > > Is this a known bug? Yes it is. I try to summarize everything in this message: https://lkml.org/lkml/2020/8/3/153 Clement > > Thanks, > > Tomeu ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v2 13/14] [DO NOT MERGE] arm64: dts: allwinner: h6: Add GPU OPP table
Hi Maxime, On Tue, 25 Aug 2020 at 15:35, Maxime Ripard wrote: > > Hi Clement, > > On Mon, Aug 03, 2020 at 09:54:05AM +0200, Clément Péron wrote: > > Hi Maxime and All, > > > > On Sat, 4 Jul 2020 at 16:56, Clément Péron wrote: > > > > > > Hi Maxime, > > > > > > On Sat, 4 Jul 2020 at 14:13, Maxime Ripard wrote: > > > > > > > > Hi, > > > > > > > > On Sat, Jul 04, 2020 at 12:25:34PM +0200, Clément Péron wrote: > > > > > Add an Operating Performance Points table for the GPU to > > > > > enable Dynamic Voltage & Frequency Scaling on the H6. > > > > > > > > > > The voltage range is set with minival voltage set to the target > > > > > and the maximal voltage set to 1.2V. This allow DVFS framework to > > > > > work properly on board with fixed regulator. > > > > > > > > > > Signed-off-by: Clément Péron > > > > > > > > That patch seems reasonable, why shouldn't we merge it? > > > > > > I didn't test it a lot and last time I did, some frequencies looked > > > unstable. > > > https://lore.kernel.org/patchwork/cover/1239739/ > > > > > > This series adds regulator support to Panfrost devfreq, I will send a > > > new one if DVFS on the H6 GPU is stable. > > > > > > I got this running glmark2 last time > > > # glmark2-es2-drm > > > === > > > glmark2 2017.07 > > > === > > > OpenGL Information > > > GL_VENDOR: Panfrost > > > GL_RENDERER: Mali T720 (Panfrost) > > > GL_VERSION:OpenGL ES 2.0 Mesa 20.0.5 > > > === > > > > > > [ 93.550063] panfrost 180.gpu: GPU Fault 0x0088 (UNKNOWN) at > > > 0x80117100 > > > [ 94.045401] panfrost 180.gpu: gpu sched timeout, js=0, > > > config=0x3700, status=0x8, head=0x21d6c00, tail=0x21d6c00, > > > sched_job=e3c2132f > > > > > > [ 328.871070] panfrost 180.gpu: Unhandled Page fault in AS0 at VA > > > 0x > > > [ 328.871070] Reason: TODO > > > [ 328.871070] raw fault status: 0xAA0003C2 > > > [ 328.871070] decoded fault status: SLAVE FAULT > > > [ 328.871070] exception type 0xC2: TRANSLATION_FAULT_LEVEL2 > > > [ 328.871070] access type 0x3: WRITE > > > [ 328.871070] source id 0xAA00 > > > [ 329.373327] panfrost 180.gpu: gpu sched timeout, js=1, > > > config=0x3700, status=0x8, head=0xa1a4900, tail=0xa1a4900, > > > sched_job=7ac31097 > > > [ 329.386527] panfrost 180.gpu: js fault, js=0, > > > status=DATA_INVALID_FAULT, head=0xa1a4c00, tail=0xa1a4c00 > > > [ 329.396293] panfrost 180.gpu: gpu sched timeout, js=0, > > > config=0x3700, status=0x58, head=0xa1a4c00, tail=0xa1a4c00, > > > sched_job=04c90381 > > > [ 329.411521] panfrost 180.gpu: Unhandled Page fault in AS0 at VA > > > 0x > > > [ 329.411521] Reason: TODO > > > [ 329.411521] raw fault status: 0xAA0003C2 > > > [ 329.411521] decoded fault status: SLAVE FAULT > > > [ 329.411521] exception type 0xC2: TRANSLATION_FAULT_LEVEL2 > > > [ 329.411521] access type 0x3: WRITE > > > [ 329.411521] source id 0xAA00 > > > > Just to keep a track of this issue. > > > > Piotr Oniszczuk give more test and seems to be software related: > > https://www.spinics.net/lists/dri-devel/msg264279.html > > > > Ondrej gave a great explanation about a possible origin of this issue: > > https://freenode.irclog.whitequark.org/linux-sunxi/2020-07-11 > > > > 20:12 looks like gpu pll on H6 is NKMP clock, and those are > > implemented in such a way in mainline that they are prone to > > overshooting the frequency during output divider reduction > > 20:13 so disabling P divider may help > > 20:13 or fixing the dividers > > 20:14 and just allowing N to change > > 20:22 hmm, I haven't looked at this for quite some time, but H6 > > BSP way of setting PLL factors actually makes the most sense out of > > everything I've seen/tested so far > > 20:23 it waits for lock not after setting NK factors, but after > > reducing the M factor (pre-divider) > > 20:24 I might as well re-run my CPU PLL tester with this > > algorithm, to see if it fixes the lockups
Re: [PATCH 07/15] drm/panfrost: use device_property_present to check for OPP
Hi Steven,
On Thu, 28 May 2020 at 15:22, Steven Price wrote:
>
> On 10/05/2020 17:55, Clément Péron wrote:
> > Instead of expecting an error from dev_pm_opp_of_add_table()
> > do a simple device_property_present() check.
> >
> > Signed-off-by: Clément Péron
>
> I'm not sure I understand why this is better. We seem to have more code
> to do roughly the same thing just with the hard-coded
> "operating-points-v2" name (if there's ever a 'v3' we'll then have to
> update this).
>
> Is the desire just to get an error on probe if the table is malformed?
> Have you hit this situation? If so this sounds like something which
> would be better fixed in the generic OPP code rather than Panfrost itself.
The idea was to avoid calling devfreq if there is no opp table.
But I think you're right we don't have to check for malformed
device-tree in the driver.
I will drop this patch,
Regards,
Clement
>
> Steve
>
> > ---
> > drivers/gpu/drm/panfrost/panfrost_devfreq.c | 14 +-
> > 1 file changed, 9 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/panfrost/panfrost_devfreq.c
> > b/drivers/gpu/drm/panfrost/panfrost_devfreq.c
> > index d9007f44b772..fce21c682414 100644
> > --- a/drivers/gpu/drm/panfrost/panfrost_devfreq.c
> > +++ b/drivers/gpu/drm/panfrost/panfrost_devfreq.c
> > @@ -96,15 +96,19 @@ int panfrost_devfreq_init(struct panfrost_device *pfdev)
> > struct thermal_cooling_device *cooling;
> > struct panfrost_devfreq *pfdevfreq = >pfdevfreq;
> >
> > - ret = dev_pm_opp_of_add_table(dev);
> > - if (ret == -ENODEV) /* Optional, continue without devfreq */
> > + if (!device_property_present(dev, "operating-points-v2"))
> > + /* Optional, continue without devfreq */
> > return 0;
> > - else if (ret)
> > - return ret;
> > - pfdevfreq->opp_of_table_added = true;
> >
> > spin_lock_init(>lock);
> >
> > + ret = dev_pm_opp_of_add_table(dev);
> > + if (ret) {
> > + DRM_DEV_ERROR(dev, "Couldn't add OPP table\n");
> > + goto err_fini;
> > + }
> > + pfdevfreq->opp_of_table_added = true;
> > +
> > panfrost_devfreq_reset(pfdevfreq);
> >
> > cur_freq = clk_get_rate(pfdev->clock);
> >
>
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Re: [PATCH 10/15] drm/panfrost: add regulators to devfreq
Hi Steven,
On Thu, 28 May 2020 at 15:23, Steven Price wrote:
>
> On 10/05/2020 17:55, Clément Péron wrote:
> > Some OPP tables specify voltage for each frequency. Devfreq can
> > handle these regulators but they should be get only 1 time to avoid
> > issue and know who is in charge.
> >
> > If OPP table is probe don't init regulator.
> >
> > Signed-off-by: Clément Péron
>
> This looks like it should work - thanks for doing this!
Yes but I'm not really happy how it's implemented.
Looks like a bit a workaround but didn't found a better solution.
Thanks for your review,
Clement
>
> Reviewed-by: Steven Price
>
> > ---
> > drivers/gpu/drm/panfrost/panfrost_devfreq.c | 19 +++
> > drivers/gpu/drm/panfrost/panfrost_devfreq.h | 2 ++
> > drivers/gpu/drm/panfrost/panfrost_device.c | 11 +++
> > 3 files changed, 28 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/panfrost/panfrost_devfreq.c
> > b/drivers/gpu/drm/panfrost/panfrost_devfreq.c
> > index fce21c682414..9ffea0d4a087 100644
> > --- a/drivers/gpu/drm/panfrost/panfrost_devfreq.c
> > +++ b/drivers/gpu/drm/panfrost/panfrost_devfreq.c
> > @@ -93,6 +93,7 @@ int panfrost_devfreq_init(struct panfrost_device *pfdev)
> > unsigned long cur_freq;
> > struct device *dev = >pdev->dev;
> > struct devfreq *devfreq;
> > + struct opp_table *opp_table;
> > struct thermal_cooling_device *cooling;
> > struct panfrost_devfreq *pfdevfreq = >pfdevfreq;
> >
> > @@ -102,6 +103,19 @@ int panfrost_devfreq_init(struct panfrost_device
> > *pfdev)
> >
> > spin_lock_init(>lock);
> >
> > + opp_table = dev_pm_opp_set_regulators(dev, pfdev->comp->supply_names,
> > + pfdev->comp->num_supplies);
> > + if (IS_ERR(opp_table)) {
> > + ret = PTR_ERR(opp_table);
> > + /* Continue if the optional regulator is missing */
> > + if (ret != -ENODEV) {
> > + DRM_DEV_ERROR(dev, "Couldn't set OPP regulators\n");
> > + goto err_fini;
> > + }
> > + } else {
> > + pfdevfreq->regulators_opp_table = opp_table;
> > + }
> > +
> > ret = dev_pm_opp_of_add_table(dev);
> > if (ret) {
> > DRM_DEV_ERROR(dev, "Couldn't add OPP table\n");
> > @@ -157,6 +171,11 @@ void panfrost_devfreq_fini(struct panfrost_device
> > *pfdev)
> > dev_pm_opp_of_remove_table(>pdev->dev);
> > pfdevfreq->opp_of_table_added = false;
> > }
> > +
> > + if (pfdevfreq->regulators_opp_table) {
> > + dev_pm_opp_put_regulators(pfdevfreq->regulators_opp_table);
> > + pfdevfreq->regulators_opp_table = NULL;
> > + }
> > }
> >
> > void panfrost_devfreq_resume(struct panfrost_device *pfdev)
> > diff --git a/drivers/gpu/drm/panfrost/panfrost_devfreq.h
> > b/drivers/gpu/drm/panfrost/panfrost_devfreq.h
> > index add203cb00c2..347cde4786cf 100644
> > --- a/drivers/gpu/drm/panfrost/panfrost_devfreq.h
> > +++ b/drivers/gpu/drm/panfrost/panfrost_devfreq.h
> > @@ -8,12 +8,14 @@
> > #include
> >
> > struct devfreq;
> > +struct opp_table;
> > struct thermal_cooling_device;
> >
> > struct panfrost_device;
> >
> > struct panfrost_devfreq {
> > struct devfreq *devfreq;
> > + struct opp_table *regulators_opp_table;
> > struct thermal_cooling_device *cooling;
> > bool opp_of_table_added;
> >
> > diff --git a/drivers/gpu/drm/panfrost/panfrost_device.c
> > b/drivers/gpu/drm/panfrost/panfrost_device.c
> > index 67eedf64e82d..8b17fb2e3369 100644
> > --- a/drivers/gpu/drm/panfrost/panfrost_device.c
> > +++ b/drivers/gpu/drm/panfrost/panfrost_device.c
> > @@ -222,10 +222,13 @@ int panfrost_device_init(struct panfrost_device
> > *pfdev)
> > goto err_out0;
> > }
> >
> > - err = panfrost_regulator_init(pfdev);
> > - if (err) {
> > - dev_err(pfdev->dev, "regulator init failed %d\n", err);
> > - goto err_out1;
> > + /* OPP will handle regulators */
> > + if (!pfdev->pfdevfreq.opp_of_table_added) {
> > + err = panfrost_regulator_init(pfdev);
> > + if (err) {
> > + dev_err(pfdev->dev, "regulator init failed %d\n",
> > err);
> > + goto err_out1;
> > + }
> > }
> >
> > err = panfrost_reset_init(pfdev);
> >
>
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Re: [PATCH 11/15] drm/panfrost: set devfreq clock name
Hi Steven,
On Thu, 28 May 2020 at 15:23, Steven Price wrote:
>
> On 10/05/2020 17:55, Clément Péron wrote:
> > Some SoCs have several clocks defined and the OPP core
> > needs to know the exact name of the clk to use.
> >
> > Set the clock name to "core".
> >
> > Signed-off-by: Clément Péron
>
> This is unfortunately a regression for the RK3288. The device tree
> binding doesn't require "clock-names", and for the RK3288 it currently
> isn't specified. So this breaks the platform.
>
> Adding the "clock-names" to the device tree 'fixes' it, but we really
> need to keep backwards compatibility.
Yes you're right, thanks for cathing this.
Regards,
Clement
>
> Steve
>
> > ---
> > drivers/gpu/drm/panfrost/panfrost_devfreq.c | 13 +
> > drivers/gpu/drm/panfrost/panfrost_devfreq.h | 1 +
> > 2 files changed, 14 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/panfrost/panfrost_devfreq.c
> > b/drivers/gpu/drm/panfrost/panfrost_devfreq.c
> > index 9ffea0d4a087..6bf3541b4d53 100644
> > --- a/drivers/gpu/drm/panfrost/panfrost_devfreq.c
> > +++ b/drivers/gpu/drm/panfrost/panfrost_devfreq.c
> > @@ -103,6 +103,14 @@ int panfrost_devfreq_init(struct panfrost_device
> > *pfdev)
> >
> > spin_lock_init(>lock);
> >
> > + opp_table = dev_pm_opp_set_clkname(dev, "core");
> > + if (IS_ERR(opp_table)) {
> > + ret = PTR_ERR(opp_table);
> > + goto err_fini;
> > + }
> > +
> > + pfdevfreq->clkname_opp_table = opp_table;
> > +
> > opp_table = dev_pm_opp_set_regulators(dev, pfdev->comp->supply_names,
> > pfdev->comp->num_supplies);
> > if (IS_ERR(opp_table)) {
> > @@ -176,6 +184,11 @@ void panfrost_devfreq_fini(struct panfrost_device
> > *pfdev)
> > dev_pm_opp_put_regulators(pfdevfreq->regulators_opp_table);
> > pfdevfreq->regulators_opp_table = NULL;
> > }
> > +
> > + if (pfdevfreq->clkname_opp_table) {
> > + dev_pm_opp_put_clkname(pfdevfreq->clkname_opp_table);
> > + pfdevfreq->clkname_opp_table = NULL;
> > + }
> > }
> >
> > void panfrost_devfreq_resume(struct panfrost_device *pfdev)
> > diff --git a/drivers/gpu/drm/panfrost/panfrost_devfreq.h
> > b/drivers/gpu/drm/panfrost/panfrost_devfreq.h
> > index 347cde4786cf..1f2475e1d034 100644
> > --- a/drivers/gpu/drm/panfrost/panfrost_devfreq.h
> > +++ b/drivers/gpu/drm/panfrost/panfrost_devfreq.h
> > @@ -16,6 +16,7 @@ struct panfrost_device;
> > struct panfrost_devfreq {
> > struct devfreq *devfreq;
> > struct opp_table *regulators_opp_table;
> > + struct opp_table *clkname_opp_table;
> > struct thermal_cooling_device *cooling;
> > bool opp_of_table_added;
> >
> >
>
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Re: [PATCH 08/15] drm/panfrost: move devfreq_init()/fini() in device
Hi Steven
On Thu, 28 May 2020 at 15:22, Steven Price wrote:
>
> On 10/05/2020 17:55, Clément Péron wrote:
> > Later we will introduce devfreq probing regulator if they
> > are present. As regulator should be probe only one time we
> > need to get this logic in the device_init().
> >
> > panfrost_device is already taking care of devfreq_resume()
> > and devfreq_suspend(), so it's not totally illogic to move
> > the devfreq_init() and devfreq_fini() here.
> >
> > Signed-off-by: Clément Péron
> > ---
> > drivers/gpu/drm/panfrost/panfrost_device.c | 37 ++
> > drivers/gpu/drm/panfrost/panfrost_drv.c| 15 ++---
> > 2 files changed, 25 insertions(+), 27 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/panfrost/panfrost_device.c
> > b/drivers/gpu/drm/panfrost/panfrost_device.c
> > index 8136babd3ba9..f480127205d6 100644
> > --- a/drivers/gpu/drm/panfrost/panfrost_device.c
> > +++ b/drivers/gpu/drm/panfrost/panfrost_device.c
> > @@ -212,59 +212,67 @@ int panfrost_device_init(struct panfrost_device
> > *pfdev)
> > return err;
> > }
> >
> > + err = panfrost_devfreq_init(pfdev);
> > + if (err) {
> > + dev_err(pfdev->dev, "devfreq init failed %d\n", err);
> > + goto err_out0;
> > + }
> > +
> > err = panfrost_regulator_init(pfdev);
> > if (err) {
> > dev_err(pfdev->dev, "regulator init failed %d\n", err);
> > - goto err_out0;
> > + goto err_out1;
>
> NIT: Rather than just renumbering these can we give them sensible names
> so we don't have this sort of refactoring in future?
Agree, I will change that in v2
>
> > }
> >
> > err = panfrost_reset_init(pfdev);
> > if (err) {
> > dev_err(pfdev->dev, "reset init failed %d\n", err);
> > - goto err_out1;
> > + goto err_out2;
> > }
> >
> > err = panfrost_pm_domain_init(pfdev);
> > if (err)
> > - goto err_out2;
> > + goto err_out3;
> >
> > res = platform_get_resource(pfdev->pdev, IORESOURCE_MEM, 0);
> > pfdev->iomem = devm_ioremap_resource(pfdev->dev, res);
> > if (IS_ERR(pfdev->iomem)) {
> > dev_err(pfdev->dev, "failed to ioremap iomem\n");
> > err = PTR_ERR(pfdev->iomem);
> > - goto err_out3;
> > + goto err_out4;
> > }
> >
> > err = panfrost_gpu_init(pfdev);
> > if (err)
> > - goto err_out3;
> > + goto err_out4;
> >
> > err = panfrost_mmu_init(pfdev);
> > if (err)
> > - goto err_out4;
> > + goto err_out5;
> >
> > err = panfrost_job_init(pfdev);
> > if (err)
> > - goto err_out5;
> > + goto err_out6;
> >
> > err = panfrost_perfcnt_init(pfdev);
> > if (err)
> > - goto err_out6;
> > + goto err_out7;
> >
> > return 0;
> > -err_out6:
> > +err_out7:
> > panfrost_job_fini(pfdev);
> > -err_out5:
> > +err_out6:
> > panfrost_mmu_fini(pfdev);
> > -err_out4:
> > +err_out5:
> > panfrost_gpu_fini(pfdev);
> > -err_out3:
> > +err_out4:
> > panfrost_pm_domain_fini(pfdev);
> > -err_out2:
> > +err_out3:
> > panfrost_reset_fini(pfdev);
> > -err_out1:
> > +err_out2:
> > panfrost_regulator_fini(pfdev);
> > +err_out1:
> > + panfrost_devfreq_fini(pfdev);
> > err_out0:
> > panfrost_clk_fini(pfdev);
> > return err;
> > @@ -278,6 +286,7 @@ void panfrost_device_fini(struct panfrost_device *pfdev)
> > panfrost_gpu_fini(pfdev);
> > panfrost_pm_domain_fini(pfdev);
> > panfrost_reset_fini(pfdev);
> > + panfrost_devfreq_fini(pfdev);
> > panfrost_regulator_fini(pfdev);
> > panfrost_clk_fini(pfdev);
> > }
> > diff --git a/drivers/gpu/drm/panfrost/panfrost_drv.c
> > b/drivers/gpu/drm/panfrost/panfrost_drv.c
> > index 882fecc33fdb..4dda68689015 100644
> > --- a/drivers/gpu/drm/panfrost/panfrost_drv.c
> > +++ b/drivers/gpu/drm/panfrost/panfrost_drv.c
> > @@ -14,7 +14,6 @@
> > #include
> >
> > #include "panfrost_device.h"
> > -#include "panfrost_devfreq.
Re: [PATCH 05/15] drm/panfrost: use spinlock instead of atomic
Hi Robin,
On Fri, 29 May 2020 at 14:20, Robin Murphy wrote:
>
> On 2020-05-10 17:55, Clément Péron wrote:
> > Convert busy_count to a simple int protected by spinlock.
>
> A little more reasoning might be nice.
I have follow the modification requested for lima devfreq and clearly
don't have any argument to switch to spinlock.
The Lima Maintainer asked to change witht the following reason :
"Better make this count a normal int which is also protected by the spinlock,
because current implementation can't protect atomic ops for state change
and busy idle check and we are using spinlock already"
>
> > Signed-off-by: Clément Péron
> > ---
> [...]
> > diff --git a/drivers/gpu/drm/panfrost/panfrost_devfreq.h
> > b/drivers/gpu/drm/panfrost/panfrost_devfreq.h
> > index 0697f8d5aa34..e6629900a618 100644
> > --- a/drivers/gpu/drm/panfrost/panfrost_devfreq.h
> > +++ b/drivers/gpu/drm/panfrost/panfrost_devfreq.h
> > @@ -4,6 +4,7 @@
> > #ifndef __PANFROST_DEVFREQ_H__
> > #define __PANFROST_DEVFREQ_H__
> >
> > +#include
> > #include
> >
> > struct devfreq;
> > @@ -14,10 +15,17 @@ struct panfrost_device;
> > struct panfrost_devfreq {
> > struct devfreq *devfreq;
> > struct thermal_cooling_device *cooling;
> > +
> > ktime_t busy_time;
> > ktime_t idle_time;
> > ktime_t time_last_update;
> > - atomic_t busy_count;
> > + int busy_count;
> > + /*
> > + * Protect busy_time, idle_time, time_last_update and busy_count
> > + * because these can be updated concurrently, for example by the GP
> > + * and PP interrupts.
> > + */
>
> Nit: this comment is clearly wrong, since we only have Job, GPU and MMU
> interrupts here. I guess if there is a race it would be between
> submission/completion/timeout on different job slots.
It's copy/paste from lima I will update it,
>
> Given that, should this actually be considered a fix for 9e62b885f715
> ("drm/panfrost: Simplify devfreq utilisation tracking")?
I can't say if it can be considered as a fix, I didn't see any
improvement on my board before and after this patch.
I'm still facing some issue and didn't have time to fully investigate it.
Thanks for you review,
>
> Robin.
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Re: [PATCH v5 00/14] Add regulator devfreq support to Panfrost
Hi Rob, On Fri, 7 Aug 2020 at 18:13, Rob Herring wrote: > > On Fri, Jul 10, 2020 at 3:54 AM Clément Péron wrote: > > > > Hi, > > > > This serie cleans and adds regulator support to Panfrost devfreq. > > This is mostly based on comment for the freshly introduced lima > > devfreq. > > > > We need to add regulator support because on Allwinner the GPU OPP > > table defines both frequencies and voltages. > > > > First patches [01-07] should not change the actual behavior > > and introduce a proper panfrost_devfreq struct. > > > > Regards, > > Clément > > > > Changes since v4: > > - Fix missed a pfdev to >devfreq during rebase > > > > Changes since v3: > > - Collect Steven Price reviewed-by tags > > - Rebase on next/master (next-20200709) > > > > Changes since v2: > > - Collect Alyssa Rosenzweig reviewed-by tags > > - Fix opp_set_regulator before adding opp_table (introduce in v2) > > - Call err_fini in case opp_add_table failed > > > > Changes since v1: > > - Collect Steven Price reviewed-by tags > > - Fix spinlock comment > > - Drop OPP clock-name patch > > - Drop device_property_test patch > > - Add rename error labels patch > > > > Clément Péron (14): > > drm/panfrost: avoid static declaration > > drm/panfrost: clean headers in devfreq > > drm/panfrost: don't use pfdevfreq.busy_count to know if hw is idle > > drm/panfrost: introduce panfrost_devfreq struct > > drm/panfrost: use spinlock instead of atomic > > drm/panfrost: properly handle error in probe > > drm/panfrost: rename error labels in device_init > > drm/panfrost: move devfreq_init()/fini() in device > > drm/panfrost: dynamically alloc regulators > > drm/panfrost: add regulators to devfreq > > arm64: defconfig: Enable devfreq cooling device > > arm64: dts: allwinner: h6: Add cooling map for GPU > > [DO NOT MERGE] arm64: dts: allwinner: h6: Add GPU OPP table > > [DO NOT MERGE] arm64: dts: allwinner: force GPU regulator to be always > > Patches 1-10 applied to drm-misc. This serie has been superseded by v5. Could you apply the v5 instead. Thanks Clément > > Rob ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v5 00/14] Add regulator devfreq support to Panfrost
On Fri, 7 Aug 2020 at 18:28, Clément Péron wrote: > > Hi Rob, > > On Fri, 7 Aug 2020 at 18:13, Rob Herring wrote: > > > > On Fri, Jul 10, 2020 at 3:54 AM Clément Péron wrote: > > > > > > Hi, > > > > > > This serie cleans and adds regulator support to Panfrost devfreq. > > > This is mostly based on comment for the freshly introduced lima > > > devfreq. > > > > > > We need to add regulator support because on Allwinner the GPU OPP > > > table defines both frequencies and voltages. > > > > > > First patches [01-07] should not change the actual behavior > > > and introduce a proper panfrost_devfreq struct. > > > > > > Regards, > > > Clément > > > > > > Changes since v4: > > > - Fix missed a pfdev to >devfreq during rebase > > > > > > Changes since v3: > > > - Collect Steven Price reviewed-by tags > > > - Rebase on next/master (next-20200709) > > > > > > Changes since v2: > > > - Collect Alyssa Rosenzweig reviewed-by tags > > > - Fix opp_set_regulator before adding opp_table (introduce in v2) > > > - Call err_fini in case opp_add_table failed > > > > > > Changes since v1: > > > - Collect Steven Price reviewed-by tags > > > - Fix spinlock comment > > > - Drop OPP clock-name patch > > > - Drop device_property_test patch > > > - Add rename error labels patch > > > > > > Clément Péron (14): > > > drm/panfrost: avoid static declaration > > > drm/panfrost: clean headers in devfreq > > > drm/panfrost: don't use pfdevfreq.busy_count to know if hw is idle > > > drm/panfrost: introduce panfrost_devfreq struct > > > drm/panfrost: use spinlock instead of atomic > > > drm/panfrost: properly handle error in probe > > > drm/panfrost: rename error labels in device_init > > > drm/panfrost: move devfreq_init()/fini() in device > > > drm/panfrost: dynamically alloc regulators > > > drm/panfrost: add regulators to devfreq > > > arm64: defconfig: Enable devfreq cooling device > > > arm64: dts: allwinner: h6: Add cooling map for GPU > > > [DO NOT MERGE] arm64: dts: allwinner: h6: Add GPU OPP table > > > [DO NOT MERGE] arm64: dts: allwinner: force GPU regulator to be always > > > > Patches 1-10 applied to drm-misc. > > This serie has been superseded by v5. > > Could you apply the v5 instead. Oups forget my email I got an issue with my gmail... Thanks > > Thanks > Clément > > > > > Rob ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v2 13/14] [DO NOT MERGE] arm64: dts: allwinner: h6: Add GPU OPP table
Hi Maxime and All,
On Sat, 4 Jul 2020 at 16:56, Clément Péron wrote:
>
> Hi Maxime,
>
> On Sat, 4 Jul 2020 at 14:13, Maxime Ripard wrote:
> >
> > Hi,
> >
> > On Sat, Jul 04, 2020 at 12:25:34PM +0200, Clément Péron wrote:
> > > Add an Operating Performance Points table for the GPU to
> > > enable Dynamic Voltage & Frequency Scaling on the H6.
> > >
> > > The voltage range is set with minival voltage set to the target
> > > and the maximal voltage set to 1.2V. This allow DVFS framework to
> > > work properly on board with fixed regulator.
> > >
> > > Signed-off-by: Clément Péron
> >
> > That patch seems reasonable, why shouldn't we merge it?
>
> I didn't test it a lot and last time I did, some frequencies looked unstable.
> https://lore.kernel.org/patchwork/cover/1239739/
>
> This series adds regulator support to Panfrost devfreq, I will send a
> new one if DVFS on the H6 GPU is stable.
>
> I got this running glmark2 last time
> # glmark2-es2-drm
> ===
> glmark2 2017.07
> ===
> OpenGL Information
> GL_VENDOR: Panfrost
> GL_RENDERER: Mali T720 (Panfrost)
> GL_VERSION:OpenGL ES 2.0 Mesa 20.0.5
> ===
>
> [ 93.550063] panfrost 180.gpu: GPU Fault 0x0088 (UNKNOWN) at
> 0x80117100
> [ 94.045401] panfrost 180.gpu: gpu sched timeout, js=0,
> config=0x3700, status=0x8, head=0x21d6c00, tail=0x21d6c00,
> sched_job=e3c2132f
>
> [ 328.871070] panfrost 180.gpu: Unhandled Page fault in AS0 at VA
> 0x
> [ 328.871070] Reason: TODO
> [ 328.871070] raw fault status: 0xAA0003C2
> [ 328.871070] decoded fault status: SLAVE FAULT
> [ 328.871070] exception type 0xC2: TRANSLATION_FAULT_LEVEL2
> [ 328.871070] access type 0x3: WRITE
> [ 328.871070] source id 0xAA00
> [ 329.373327] panfrost 180.gpu: gpu sched timeout, js=1,
> config=0x3700, status=0x8, head=0xa1a4900, tail=0xa1a4900,
> sched_job=7ac31097
> [ 329.386527] panfrost 180.gpu: js fault, js=0,
> status=DATA_INVALID_FAULT, head=0xa1a4c00, tail=0xa1a4c00
> [ 329.396293] panfrost 180.gpu: gpu sched timeout, js=0,
> config=0x3700, status=0x58, head=0xa1a4c00, tail=0xa1a4c00,
> sched_job=04c90381
> [ 329.411521] panfrost 180.gpu: Unhandled Page fault in AS0 at VA
> 0x
> [ 329.411521] Reason: TODO
> [ 329.411521] raw fault status: 0xAA0003C2
> [ 329.411521] decoded fault status: SLAVE FAULT
> [ 329.411521] exception type 0xC2: TRANSLATION_FAULT_LEVEL2
> [ 329.411521] access type 0x3: WRITE
> [ 329.411521] source id 0xAA00
Just to keep a track of this issue.
Piotr Oniszczuk give more test and seems to be software related:
https://www.spinics.net/lists/dri-devel/msg264279.html
Ondrej gave a great explanation about a possible origin of this issue:
https://freenode.irclog.whitequark.org/linux-sunxi/2020-07-11
20:12 looks like gpu pll on H6 is NKMP clock, and those are
implemented in such a way in mainline that they are prone to
overshooting the frequency during output divider reduction
20:13 so disabling P divider may help
20:13 or fixing the dividers
20:14 and just allowing N to change
20:22 hmm, I haven't looked at this for quite some time, but H6
BSP way of setting PLL factors actually makes the most sense out of
everything I've seen/tested so far
20:23 it waits for lock not after setting NK factors, but after
reducing the M factor (pre-divider)
20:24 I might as well re-run my CPU PLL tester with this
algorithm, to see if it fixes the lockups
20:26 it makes sense to wait for PLL to stabilize "after"
changing all the factors that actually affect the VCO, and not just
some of them
20:27 warpme_: ^
20:28 it may be the same thing that plagues the CPU PLL rate
changes at runtime
Regards,
Clement
>
> Regards,
> Clement
>
> >
> > > ---
> > > arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 80
> > > 1 file changed, 80 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> > > b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> > > index 8f514a2169aa..a69f9e09a829 100644
> > > --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> > > +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> > > @@ -174,6 +174,7 @@ gpu: gpu@180 {
> > > clocks = < CLK_GPU>, < CLK_BUS_GPU>;
> > > clock-names = "core", "bus";
> > > resets =
[PATCH v2 11/14] arm64: defconfig: Enable devfreq cooling device
Devfreq cooling device framework is used in Panfrost to throttle GPU in order to regulate its temperature. Enable this driver for ARM64 SoC. Signed-off-by: Clément Péron --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 883e8bace3ed..1b7f9ffdc314 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -501,6 +501,7 @@ CONFIG_SENSORS_INA2XX=m CONFIG_SENSORS_INA3221=m CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y CONFIG_CPU_THERMAL=y +CONFIG_DEVFREQ_THERMAL=y CONFIG_THERMAL_EMULATION=y CONFIG_QORIQ_THERMAL=m CONFIG_SUN8I_THERMAL=y -- 2.25.1 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v2 14/14] [DO NOT MERGE] arm64: dts: allwinner: force GPU regulator to be always
Hi,
On Sat, 4 Jul 2020 at 12:25, Clément Péron wrote:
>
> Signed-off-by: Clément Péron
> ---
> arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
> b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
> index 3f7ceeb1a767..14257f7476b8 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
> @@ -245,6 +245,7 @@ reg_dcdca: dcdca {
> };
>
> reg_dcdcc: dcdcc {
> + regulator-always-on;
This patch is normally no more required since this serie:
https://lore.kernel.org/linux-pm/cover.1589528491.git.viresh.ku...@linaro.org/
> regulator-enable-ramp-delay = <32000>;
> regulator-min-microvolt = <81>;
> regulator-max-microvolt = <108>;
> --
> 2.25.1
>
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[PATCH v2 02/14] drm/panfrost: clean headers in devfreq
Don't include not required headers and sort them.
Signed-off-by: Clément Péron
Reviewed-by: Steven Price
---
drivers/gpu/drm/panfrost/panfrost_devfreq.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/panfrost/panfrost_devfreq.c
b/drivers/gpu/drm/panfrost/panfrost_devfreq.c
index 1b560b903ea6..df7b71da9a84 100644
--- a/drivers/gpu/drm/panfrost/panfrost_devfreq.c
+++ b/drivers/gpu/drm/panfrost/panfrost_devfreq.c
@@ -1,18 +1,14 @@
// SPDX-License-Identifier: GPL-2.0
/* Copyright 2019 Collabora ltd. */
+
+#include
#include
#include
#include
#include
-#include
-#include
#include "panfrost_device.h"
#include "panfrost_devfreq.h"
-#include "panfrost_features.h"
-#include "panfrost_issues.h"
-#include "panfrost_gpu.h"
-#include "panfrost_regs.h"
static void panfrost_devfreq_update_utilization(struct panfrost_device *pfdev)
{
--
2.25.1
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[PATCH v2 05/14] drm/panfrost: use spinlock instead of atomic
Convert busy_count to a simple int protected by spinlock.
Signed-off-by: Clément Péron
Reviewed-by: Steven Price
---
drivers/gpu/drm/panfrost/panfrost_devfreq.c | 43 +++--
drivers/gpu/drm/panfrost/panfrost_devfreq.h | 9 -
2 files changed, 40 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/panfrost/panfrost_devfreq.c
b/drivers/gpu/drm/panfrost/panfrost_devfreq.c
index 962550363391..78753cfb59fb 100644
--- a/drivers/gpu/drm/panfrost/panfrost_devfreq.c
+++ b/drivers/gpu/drm/panfrost/panfrost_devfreq.c
@@ -12,16 +12,12 @@
static void panfrost_devfreq_update_utilization(struct panfrost_devfreq
*pfdevfreq)
{
- ktime_t now;
- ktime_t last;
-
- if (!pfdevfreq->devfreq)
- return;
+ ktime_t now, last;
now = ktime_get();
last = pfdevfreq->time_last_update;
- if (atomic_read(>busy_count) > 0)
+ if (pfdevfreq->busy_count > 0)
pfdevfreq->busy_time += ktime_sub(now, last);
else
pfdevfreq->idle_time += ktime_sub(now, last);
@@ -59,10 +55,14 @@ static int panfrost_devfreq_get_dev_status(struct device
*dev,
{
struct panfrost_device *pfdev = dev_get_drvdata(dev);
struct panfrost_devfreq *pfdevfreq = >pfdevfreq;
+ unsigned long irqflags;
+
+ status->current_frequency = clk_get_rate(pfdev->clock);
+
+ spin_lock_irqsave(>lock, irqflags);
panfrost_devfreq_update_utilization(pfdevfreq);
- status->current_frequency = clk_get_rate(pfdev->clock);
status->total_time = ktime_to_ns(ktime_add(pfdevfreq->busy_time,
pfdevfreq->idle_time));
@@ -70,6 +70,8 @@ static int panfrost_devfreq_get_dev_status(struct device *dev,
panfrost_devfreq_reset(pfdevfreq);
+ spin_unlock_irqrestore(>lock, irqflags);
+
dev_dbg(pfdev->dev, "busy %lu total %lu %lu %% freq %lu MHz\n",
status->busy_time, status->total_time,
status->busy_time / (status->total_time / 100),
@@ -100,6 +102,8 @@ int panfrost_devfreq_init(struct panfrost_device *pfdev)
else if (ret)
return ret;
+ spin_lock_init(>lock);
+
panfrost_devfreq_reset(pfdevfreq);
cur_freq = clk_get_rate(pfdev->clock);
@@ -162,15 +166,32 @@ void panfrost_devfreq_suspend(struct panfrost_device
*pfdev)
void panfrost_devfreq_record_busy(struct panfrost_devfreq *pfdevfreq)
{
+ unsigned long irqflags;
+
+ if (!pfdevfreq->devfreq)
+ return;
+
+ spin_lock_irqsave(>lock, irqflags);
+
panfrost_devfreq_update_utilization(pfdevfreq);
- atomic_inc(>busy_count);
+
+ pfdevfreq->busy_count++;
+
+ spin_unlock_irqrestore(>lock, irqflags);
}
void panfrost_devfreq_record_idle(struct panfrost_devfreq *pfdevfreq)
{
- int count;
+ unsigned long irqflags;
+
+ if (!pfdevfreq->devfreq)
+ return;
+
+ spin_lock_irqsave(>lock, irqflags);
panfrost_devfreq_update_utilization(pfdevfreq);
- count = atomic_dec_if_positive(>busy_count);
- WARN_ON(count < 0);
+
+ WARN_ON(--pfdevfreq->busy_count < 0);
+
+ spin_unlock_irqrestore(>lock, irqflags);
}
diff --git a/drivers/gpu/drm/panfrost/panfrost_devfreq.h
b/drivers/gpu/drm/panfrost/panfrost_devfreq.h
index 0697f8d5aa34..3392df1020be 100644
--- a/drivers/gpu/drm/panfrost/panfrost_devfreq.h
+++ b/drivers/gpu/drm/panfrost/panfrost_devfreq.h
@@ -4,6 +4,7 @@
#ifndef __PANFROST_DEVFREQ_H__
#define __PANFROST_DEVFREQ_H__
+#include
#include
struct devfreq;
@@ -14,10 +15,16 @@ struct panfrost_device;
struct panfrost_devfreq {
struct devfreq *devfreq;
struct thermal_cooling_device *cooling;
+
ktime_t busy_time;
ktime_t idle_time;
ktime_t time_last_update;
- atomic_t busy_count;
+ int busy_count;
+ /*
+* Protect busy_time, idle_time, time_last_update and busy_count
+* because these can be updated concurrently between multiple jobs.
+*/
+ spinlock_t lock;
};
int panfrost_devfreq_init(struct panfrost_device *pfdev);
--
2.25.1
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[PATCH v2 03/14] drm/panfrost: don't use pfdevfreq.busy_count to know if hw is idle
This use devfreq variable that will be lock with spinlock in future
patches. We should either introduce a function to access this one
but as devfreq is optional let's just remove it.
Signed-off-by: Clément Péron
Reviewed-by: Steven Price
---
drivers/gpu/drm/panfrost/panfrost_job.c | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/gpu/drm/panfrost/panfrost_job.c
b/drivers/gpu/drm/panfrost/panfrost_job.c
index 7914b1570841..63e32a9f2749 100644
--- a/drivers/gpu/drm/panfrost/panfrost_job.c
+++ b/drivers/gpu/drm/panfrost/panfrost_job.c
@@ -581,10 +581,6 @@ int panfrost_job_is_idle(struct panfrost_device *pfdev)
struct panfrost_job_slot *js = pfdev->js;
int i;
- /* Check whether the hardware is idle */
- if (atomic_read(>devfreq.busy_count))
- return false;
-
for (i = 0; i < NUM_JOB_SLOTS; i++) {
/* If there are any jobs in the HW queue, we're not idle */
if (atomic_read(>queue[i].sched.hw_rq_count))
--
2.25.1
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[PATCH v2 04/14] drm/panfrost: introduce panfrost_devfreq struct
Introduce a proper panfrost_devfreq to deal with devfreq variables.
Signed-off-by: Clément Péron
Reviewed-by: Steven Price
---
drivers/gpu/drm/panfrost/panfrost_devfreq.c | 76 -
drivers/gpu/drm/panfrost/panfrost_devfreq.h | 20 +-
drivers/gpu/drm/panfrost/panfrost_device.h | 11 +--
drivers/gpu/drm/panfrost/panfrost_job.c | 6 +-
4 files changed, 66 insertions(+), 47 deletions(-)
diff --git a/drivers/gpu/drm/panfrost/panfrost_devfreq.c
b/drivers/gpu/drm/panfrost/panfrost_devfreq.c
index df7b71da9a84..962550363391 100644
--- a/drivers/gpu/drm/panfrost/panfrost_devfreq.c
+++ b/drivers/gpu/drm/panfrost/panfrost_devfreq.c
@@ -10,23 +10,23 @@
#include "panfrost_device.h"
#include "panfrost_devfreq.h"
-static void panfrost_devfreq_update_utilization(struct panfrost_device *pfdev)
+static void panfrost_devfreq_update_utilization(struct panfrost_devfreq
*pfdevfreq)
{
ktime_t now;
ktime_t last;
- if (!pfdev->devfreq.devfreq)
+ if (!pfdevfreq->devfreq)
return;
now = ktime_get();
- last = pfdev->devfreq.time_last_update;
+ last = pfdevfreq->time_last_update;
- if (atomic_read(>devfreq.busy_count) > 0)
- pfdev->devfreq.busy_time += ktime_sub(now, last);
+ if (atomic_read(>busy_count) > 0)
+ pfdevfreq->busy_time += ktime_sub(now, last);
else
- pfdev->devfreq.idle_time += ktime_sub(now, last);
+ pfdevfreq->idle_time += ktime_sub(now, last);
- pfdev->devfreq.time_last_update = now;
+ pfdevfreq->time_last_update = now;
}
static int panfrost_devfreq_target(struct device *dev, unsigned long *freq,
@@ -47,30 +47,31 @@ static int panfrost_devfreq_target(struct device *dev,
unsigned long *freq,
return 0;
}
-static void panfrost_devfreq_reset(struct panfrost_device *pfdev)
+static void panfrost_devfreq_reset(struct panfrost_devfreq *pfdevfreq)
{
- pfdev->devfreq.busy_time = 0;
- pfdev->devfreq.idle_time = 0;
- pfdev->devfreq.time_last_update = ktime_get();
+ pfdevfreq->busy_time = 0;
+ pfdevfreq->idle_time = 0;
+ pfdevfreq->time_last_update = ktime_get();
}
static int panfrost_devfreq_get_dev_status(struct device *dev,
struct devfreq_dev_status *status)
{
struct panfrost_device *pfdev = dev_get_drvdata(dev);
+ struct panfrost_devfreq *pfdevfreq = >pfdevfreq;
- panfrost_devfreq_update_utilization(pfdev);
+ panfrost_devfreq_update_utilization(pfdevfreq);
status->current_frequency = clk_get_rate(pfdev->clock);
- status->total_time = ktime_to_ns(ktime_add(pfdev->devfreq.busy_time,
- pfdev->devfreq.idle_time));
+ status->total_time = ktime_to_ns(ktime_add(pfdevfreq->busy_time,
+ pfdevfreq->idle_time));
- status->busy_time = ktime_to_ns(pfdev->devfreq.busy_time);
+ status->busy_time = ktime_to_ns(pfdevfreq->busy_time);
- panfrost_devfreq_reset(pfdev);
+ panfrost_devfreq_reset(pfdevfreq);
- dev_dbg(pfdev->dev, "busy %lu total %lu %lu %% freq %lu MHz\n",
status->busy_time,
- status->total_time,
+ dev_dbg(pfdev->dev, "busy %lu total %lu %lu %% freq %lu MHz\n",
+ status->busy_time, status->total_time,
status->busy_time / (status->total_time / 100),
status->current_frequency / 1000 / 1000);
@@ -91,6 +92,7 @@ int panfrost_devfreq_init(struct panfrost_device *pfdev)
struct device *dev = >pdev->dev;
struct devfreq *devfreq;
struct thermal_cooling_device *cooling;
+ struct panfrost_devfreq *pfdevfreq = >pfdevfreq;
ret = dev_pm_opp_of_add_table(dev);
if (ret == -ENODEV) /* Optional, continue without devfreq */
@@ -98,7 +100,7 @@ int panfrost_devfreq_init(struct panfrost_device *pfdev)
else if (ret)
return ret;
- panfrost_devfreq_reset(pfdev);
+ panfrost_devfreq_reset(pfdevfreq);
cur_freq = clk_get_rate(pfdev->clock);
@@ -116,53 +118,59 @@ int panfrost_devfreq_init(struct panfrost_device *pfdev)
dev_pm_opp_of_remove_table(dev);
return PTR_ERR(devfreq);
}
- pfdev->devfreq.devfreq = devfreq;
+ pfdevfreq->devfreq = devfreq;
cooling = of_devfreq_cooling_register(dev->of_node, devfreq);
if (IS_ERR(cooling))
DRM_DEV_INFO(dev, "Failed to register cooling device\n");
else
- pfdev->devfreq.cooling = cooling;
+ pfdevfreq->cooling = cooling;
return 0;
}
void panfrost_dev
