radeon framebuffer tiling

2016-01-04 Thread Jay Cornwall
architecture? i.e. All surfaces provided to drmModePageFlip should match the initial framebuffer layout, or should EVERGREEN_GRPH_CONTROL be updated on every page flip? -- Jay Cornwall

radeon framebuffer tiling

2016-01-04 Thread Jay Cornwall
On 2016-01-04 12:14, Alex Deucher wrote: > On Mon, Jan 4, 2016 at 12:57 PM, Jay Cornwall wrote: >> Hi, >> >> dce4_crtc_do_set_base is the only location in which >> EVERGREEN_GRPH_CONTROL >> is updated. This currently configures a non-tiled framebuffer on my

[PATCH 1/2] drm/radeon: add large PTE support for NI, SI and CIK v4

2014-05-01 Thread Jay Cornwall
verage improvement from 24.7 to 27.7 FPS > on default settings at 1920x1200 resolution with vsync disabled. > > See main comment in radeon_gart.c gives a technical description. > > v2 (chk): rebased and simplified. > v3 (chk): add missing hw setup > v4 (chk): rebased on current

[PATCH] drm/amdgpu: Fix default page access routing

2015-11-05 Thread Jay Cornwall
The VM default page (used when a VM translation fails) is allocated in system memory. The VM is misconfigured to interpret the physical address as referencing a VRAM physical page. Route default page accesses to system memory. Signed-off-by: Jay Cornwall Cc: # v4.2+ --- drivers/gpu/drm/amd

[PATCH] drm/amdgpu: Fix default page access routing

2015-11-06 Thread Jay Cornwall
On 2015-11-06 02:28, Christian König wrote: > On 05.11.2015 20:06, Jay Cornwall wrote: >> The VM default page (used when a VM translation fails) is allocated in >> system memory. The VM is misconfigured to interpret the physical >> address >> as referencing a VRAM