Hi,
Dne petek, 24. februar 2017 ob 14:30:36 CET je Rob Herring napisal(a):
> On Wed, Feb 22, 2017 at 2:09 PM, Maxime Ripard
>
> wrote:
> > Hi,
> >
> > On Wed, Feb 22, 2017 at 11:23:06PM +0800, Icenowy Zheng wrote:
> >> Allwinner have a new "Display Engine 2.0"
Hi,
Dne sreda, 22. februar 2017 ob 16:18:50 CET je Icenowy Zheng napisal(a):
> Allwinner have a new "Display Engine 2.0" in there new SoCs, which comes
> in a new "Display Engine" (mixers instead of old backends and
> frontends).
>
> Add support for the mixer on Allwinner V3s SoC; it's the
Hi,
Dne sreda, 22. februar 2017 ob 21:17:29 CET je Icenowy Zheng napisal(a):
> 2017年2月23日 03:09于 Maxime Ripard 写道:
>
> > Hi,
> >
> > On Wed, Feb 22, 2017 at 11:18:48PM +0800, Icenowy Zheng wrote:
> > > +config SUNXI_DE2_CCU
> > > + bool "Support for the
Hi,
Dne sreda, 29. marec 2017 ob 21:46:08 CEST je Icenowy Zheng napisal(a):
> Allwinner have a new "Display Engine 2.0" in their new SoCs, which comes
> with mixers to do graphic processing and feed data to TCON, like the old
> backends and frontends.
>
> Add support for the mixer on Allwinner
Hi,
Dne sreda, 02. avgust 2017 ob 07:02:39 CEST je icen...@aosc.io napisal(a):
> 在 2017-08-02 12:53,Jernej Škrabec 写道:
>
> > Hi Icenowy,
> >
> > Dne torek, 01. avgust 2017 ob 15:12:52 CEST je Icenowy Zheng
> >
> > napisal(a):
> >> Allwinner H3 fe
Hi,
Dne četrtek, 10. avgust 2017 ob 02:21:21 CEST je Rob Herring napisal(a):
> On Wed, Aug 02, 2017 at 09:06:26PM +0200, Jernej Škrabec wrote:
> > Hi,
> >
> > Dne sreda, 02. avgust 2017 ob 07:02:39 CEST je icen...@aosc.io napisal(a):
> > > 在 2017-08-02 12:53,Jernej
Hi Icenowy,
Dne torek, 01. avgust 2017 ob 15:12:58 CEST je Icenowy Zheng napisal(a):
> As we have already the support for the DE2 on Allwinner H3, add the
> display engine pipeline device tree nodes to its DTSI file.
>
> The H5 pipeline has some differences and will be enabled later.
>
>
Hi Icenowy,
Dne torek, 01. avgust 2017 ob 15:12:52 CEST je Icenowy Zheng napisal(a):
> Allwinner H3 features a "Display Engine 2.0".
>
> Add device tree bindings for the following parts:
> - H3 TCONs
> - H3 Mixers
> - H3 Display engine
>
> Signed-off-by: Icenowy Zheng
> ---
>
Hi,
Dne sreda, 17. maj 2017 ob 18:43:53 CEST je Icenowy Zheng napisal(a):
> As we have already the support for the TV encoder on Allwinner H3, add
> the display engine pipeline device tree nodes to its DTSI file.
>
> The H5 pipeline has some differences and will be enabled later.
>
> The
Hi,
Dne sreda, 17. maj 2017 ob 18:43:49 CEST je Icenowy Zheng napisal(a):
> The DE2 mixer can do color space correction needed by TV Encoder with
> its DCSC sub-engine.
>
> Add support for it.
>
> Signed-off-by: Icenowy Zheng
> ---
> drivers/gpu/drm/sun4i/sun8i_mixer.c | 35
>
Hi!
Dne petek, 19. maj 2017 ob 19:49:58 CEST je Icenowy Zheng napisal(a):
> 于 2017年5月20日 GMT+08:00 上午1:47:29, Maxime Ripard 写到:
> >On Thu, May 18, 2017 at 12:43:45AM +0800, Icenowy Zheng wrote:
> >> From: Icenowy Zheng
> >>
> >> Allwinner H3
Hi,
Dne petek, 19. maj 2017 ob 20:08:18 CEST je Icenowy Zheng napisal(a):
> 于 2017年5月20日 GMT+08:00 上午2:03:30, Maxime Ripard 写到:
> >On Thu, May 18, 2017 at 12:43:50AM +0800, Icenowy Zheng wrote:
> >> Allwinner H3 features a TV encoder similar to the one in
Hi,
Dne sobota, 20. maj 2017 ob 03:37:53 CEST je Chen-Yu Tsai napisal(a):
> On Sat, May 20, 2017 at 2:23 AM, Jernej Škrabec <jernej.skra...@siol.net>
wrote:
> > Hi,
> >
> > Dne petek, 19. maj 2017 ob 20:08:18 CEST je Icenowy Zheng napisal(a):
> >> 于 2017年5月20
写道:
> >>
> >> > On Mon, May 22, 2017 at 07:55:56PM +0200, Jernej Škrabec wrote:
> >> > > Hi,
> >> > >
> >> > > Dne sobota, 20. maj 2017 ob 03:37:53 CEST je Chen-Yu Tsai
> >
> >napisal(a):
> >> > > &
Hi,
Dne nedelja, 04. junij 2017 ob 18:01:42 CEST je Icenowy Zheng napisal(a):
> From: Icenowy Zheng
>
> Allwinner H3 has two special TCONs, both come without channel0. And the
> TCON1 of H3 has no special clocks even for the channel1.
>
> Add support for these kinds of TCON.
Hi!
Dne sreda, 07. junij 2017 ob 16:38:27 CEST je Maxime Ripard napisal(a):
> On Wed, Jun 07, 2017 at 06:01:02PM +0800, Icenowy Zheng wrote:
> > >I have no idea what this is supposed to be doing either.
> > >
> > >I might be wrong, but I really feel like there's a big mismatch
> > >between your
Hi!
Dne petek, 09. junij 2017 ob 18:51:02 CEST je Icenowy Zheng napisal(a):
> 于 2017年6月10日 GMT+08:00 上午12:49:15, Maxime Ripard 写到:
> >On Wed, Jun 07, 2017 at 04:48:50PM +0800, Icenowy Zheng wrote:
> >> >> @@ -189,6 +211,8 @@ supported.
> >> >>
> >> >>
Hi,
Dne sobota, 30. september 2017 ob 13:58:03 CEST je Alexey Kardashevskiy
napisal(a):
> On 21/09/17 06:01, Jernej Skrabec wrote:
> > [added media mailing list due to CEC question]
> >
> > This patch series adds a HDMI glue driver for Allwinner H3 SoC. For now,
> > only video and CEC
Hi Maxime,
Dne ponedeljek, 27. november 2017 ob 16:41:29 CET je Maxime Ripard napisal(a):
> It seems like the mixer can only run properly when clocked at 150MHz. In
> order to have something more robust than simply a fire-and-forget
> assigned-clocks-rate, let's put that in the code.
>
>
Hi Maxime,
Dne ponedeljek, 27. november 2017 ob 16:41:35 CET je Maxime Ripard napisal(a):
> Add support for the A83T display pipeline.
>
> Reviewed-by: Chen-Yu Tsai
> Signed-off-by: Maxime Ripard
> ---
>
Hi,
Dne ponedeljek, 27. november 2017 ob 16:41:24 CET je Maxime Ripard napisal(a):
> Hi,
>
> Here is an attempt at supporting the LVDS output in our DRM driver. This
> has been tested on the A83T (with DE2), but since everything is basically
> in the TCON, it should also be usable on the older
Hi!
Dne torek, 28. november 2017 ob 21:55:50 CET je Maxime Ripard napisal(a):
> On Mon, Nov 27, 2017 at 09:57:46PM +0100, Jernej Skrabec wrote:
> > DE2 have many CSC units - channel input CSC, channel output CSC and
> > mixer output CSC and maybe more.
> >
> > Fortunately, they have all same
Hi!
Dne torek, 28. november 2017 ob 09:58:26 CET je Maxime Ripard napisal(a):
> On Mon, Nov 27, 2017 at 05:07:04PM +0100, Jernej Škrabec wrote:
> > Hi Maxime,
> >
> > Dne ponedeljek, 27. november 2017 ob 16:41:29 CET je Maxime Ripard
napisal(a):
> > > It see
Hi!
Dne torek, 28. november 2017 ob 23:00:14 CET je Maxime Ripard napisal(a):
> On Tue, Nov 28, 2017 at 04:48:55PM +0100, Jernej Škrabec wrote:
> > > On Mon, Nov 27, 2017 at 05:01:49PM +0100, Jernej Škrabec wrote:
> > > > Dne ponedeljek, 27. november 2017 ob 16:41
Hi,
Dne torek, 28. november 2017 ob 10:02:23 CET je Maxime Ripard napisal(a):
> Hi,
>
> On Mon, Nov 27, 2017 at 05:01:49PM +0100, Jernej Škrabec wrote:
> > Dne ponedeljek, 27. november 2017 ob 16:41:35 CET je Maxime Ripard
napisal(a):
> > > Add support for t
Hi!
Dne torek, 28. november 2017 ob 22:00:01 CET je Maxime Ripard napisal(a):
> Hi,
>
> On Mon, Nov 27, 2017 at 09:57:41PM +0100, Jernej Skrabec wrote:
> > This commit adds basic support for VI planes. They are meant for video
> > overlay and because of that they support YUV formats too.
Hi!
Dne torek, 28. november 2017 ob 16:54:42 CET je Maxime Ripard napisal(a):
> Hi,
>
> On Mon, Nov 27, 2017 at 09:57:34PM +0100, Jernej Skrabec wrote:
> > Since the time initial DE2 driver was written, some knowledge was gained
> > what setting are really necessary and what most of the magic
Hi Julian,
Dne sreda, 29. november 2017 ob 22:48:34 CET je Julian Calaby napisal(a):
> Hi Jernej,
>
> On Tue, Nov 28, 2017 at 7:57 AM, Jernej Skrabec
wrote:
> > Calculate scaling parameters and call appropriate scaler set up
> > function.
> >
> > Signed-off-by: Jernej
Hi,
Dne torek, 28. november 2017 ob 22:00:01 CET je Maxime Ripard napisal(a):
> Hi,
>
> On Mon, Nov 27, 2017 at 09:57:41PM +0100, Jernej Skrabec wrote:
> > This commit adds basic support for VI planes. They are meant for video
> > overlay and because of that they support YUV formats too.
Dne četrtek, 30. november 2017 ob 16:33:12 CET je Maxime Ripard napisal(a):
> On Tue, Nov 28, 2017 at 11:33:44PM +0100, Jernej Škrabec wrote:
> > Hi!
> >
> > Dne torek, 28. november 2017 ob 23:00:14 CET je Maxime Ripard napisal(a):
> > > On Tue, Nov 28, 2017 at 04
Hi Maxime,
Dne torek, 05. december 2017 ob 11:36:18 CET je Maxime Ripard napisal(a):
> Hi,
>
> On Fri, Dec 01, 2017 at 07:05:23AM +0100, Jernej Skrabec wrote:
> > Current DE2 driver is very basic and uses a lot of magic constants since
> > there is no documentation and knowledge about it was
Hi Maxime,
Dne torek, 05. december 2017 ob 16:10:21 CET je Maxime Ripard napisal(a):
> Add support for the A83T display pipeline.
>
> Reviewed-by: Chen-Yu Tsai
> Signed-off-by: Maxime Ripard
> ---
> drivers/gpu/drm/sun4i/sun4i_drv.c | 1 +
>
Hi,
Dne torek, 05. december 2017 ob 16:42:55 CET je Jernej Škrabec napisal(a):
> Hi Maxime,
>
> Dne torek, 05. december 2017 ob 16:10:21 CET je Maxime Ripard napisal(a):
> > Add support for the A83T display pipeline.
> >
> > Reviewed-by: Chen-Yu Tsai <w...@csie.
Hi,
Dne četrtek, 24. maj 2018 ob 10:43:51 CEST je Maxime Ripard napisal(a):
> Hi,
>
> On Mon, May 21, 2018 at 05:15:15PM +0200, Jernej Škrabec wrote:
> > > > + /*
> > > > +* Default register values might have some reserved bits set,
which
> >
Hi,
Dne petek, 18. maj 2018 ob 12:01:16 CEST je Maxime Ripard napisal(a):
> On Fri, May 18, 2018 at 03:15:22PM +0530, Jagan Teki wrote:
> > From: Jernej Skrabec
> >
> > Some SoCs with DW HDMI have multiple possible clock parents, like A64
> > and R40.
> >
> > Expand
Hi,
Dne petek, 18. maj 2018 ob 17:09:40 CEST je Sergey Suloev napisal(a):
> Hi, guys,
>
> On 05/18/2018 05:46 PM, Jernej Škrabec wrote:
> > Hi,
> >
> > Dne petek, 18. maj 2018 ob 12:01:16 CEST je Maxime Ripard napisal(a):
> >> On Fri, May 18, 2018 a
Hi,
Dne nedelja, 20. maj 2018 ob 04:09:52 CEST je Julian Calaby napisal(a):
> Hi Jernej,
>
> On Sun, May 20, 2018 at 11:57 AM, Julian Calaby
wrote:
> > Hi Jernej,
> >
> > On Sun, May 20, 2018 at 4:31 AM, Jernej Skrabec
wrote:
> >> R40
Hi,
Dne petek, 18. maj 2018 ob 17:26:51 CEST je Maxime Ripard napisal(a):
> On Fri, May 18, 2018 at 04:46:41PM +0200, Jernej Škrabec wrote:
> > > And this is a bit sloppy, since if phy_clk_num == 3, you won't try to
> > > lookup pll-2 either.
> >
> > It is hi
Hi,
Dne petek, 18. maj 2018 ob 17:26:51 CEST je Maxime Ripard napisal(a):
> On Fri, May 18, 2018 at 04:46:41PM +0200, Jernej Škrabec wrote:
> > > And this is a bit sloppy, since if phy_clk_num == 3, you won't try to
> > > lookup pll-2 either.
> >
> > It is hi
Hi,
Dne ponedeljek, 21. maj 2018 ob 10:01:47 CEST je Maxime Ripard napisal(a):
> Hi,
>
> On Sat, May 19, 2018 at 08:31:16PM +0200, Jernej Skrabec wrote:
> > TCON TOP main purpose is to configure whole display pipeline. It
> > determines relationships between mixers and TCONs, selects source TCON
Hi,
Dne ponedeljek, 21. maj 2018 ob 10:05:17 CEST je Maxime Ripard napisal(a):
> On Sat, May 19, 2018 at 08:31:17PM +0200, Jernej Skrabec wrote:
> > As already described in DT binding, TCON TOP is responsible for
> > configuring display pipeline. In this initial driver focus is on HDMI
> >
Hi,
Dne ponedeljek, 21. maj 2018 ob 10:12:53 CEST je Maxime Ripard napisal(a):
> On Sat, May 19, 2018 at 08:31:24PM +0200, Jernej Skrabec wrote:
> > Expand HDMI PHY clock driver to support second clock parent.
> >
> > Signed-off-by: Jernej Skrabec
> > ---
> >
> >
Hi,
Dne ponedeljek, 21. maj 2018 ob 10:07:59 CEST je Maxime Ripard napisal(a):
> On Sat, May 19, 2018 at 08:31:18PM +0200, Jernej Skrabec wrote:
> > If SoC has TCON TOP unit, it has to be configured from TCON, since it
> > has all information needed. Additionally, if it is TCON TV, it must also
>
Dne četrtek, 07. junij 2018 ob 00:30:24 CEST je Jernej Škrabec napisal(a):
> Dne ponedeljek, 04. junij 2018 ob 18:23:57 CEST je Maxime Ripard napisal(a):
> > On Mon, Jun 04, 2018 at 05:09:56PM +0200, Jernej Škrabec wrote:
> > > Dne ponedeljek, 04. junij 2018 ob 13:50:34 CES
Dne ponedeljek, 18. junij 2018 ob 14:58:02 CEST je Jagan Teki napisal(a):
> On Thu, Jun 14, 2018 at 10:59 PM, Jernej Škrabec
>
> wrote:
> > Dne četrtek, 14. junij 2018 ob 19:16:46 CEST je Jagan Teki napisal(a):
> >> On Thu, Jun 14, 2018 at 8:04 PM, Jernej Škrabec
&g
Hi,
Dne petek, 15. junij 2018 ob 10:31:10 CEST je Maxime Ripard napisal(a):
> Hi,
>
> On Tue, Jun 12, 2018 at 10:00:20PM +0200, Jernej Skrabec wrote:
> > TV TCONs connected to TCON TOP have to enable additional gate in order
> > to work.
> >
> > Add support for such TCONs.
> >
> >
Dne petek, 15. junij 2018 ob 19:13:17 CEST je Chen-Yu Tsai napisal(a):
> On Sat, Jun 16, 2018 at 12:41 AM, Jernej Škrabec
>
> wrote:
> > Hi,
> >
> > Dne petek, 15. junij 2018 ob 10:31:10 CEST je Maxime Ripard napisal(a):
> >> Hi,
> >>
> >
Dne torek, 12. junij 2018 ob 22:00:29 CEST je Jernej Skrabec napisal(a):
> DW HDMI PHY driver and PHY clock driver share same registers. Make sure
> that DW HDMI PHY setup code doesn't change any clock related bits and
> set them to 0 during initialization.
>
> Signed-off-by: Jernej Skrabec
>
Hi,
Dne sreda, 13. junij 2018 ob 09:34:56 CEST je Maxime Ripard napisal(a):
> Hi,
>
> Thanks for working on this!
>
> On Tue, Jun 12, 2018 at 10:00:13PM +0200, Jernej Skrabec wrote:
> > TCON TOP main purpose is to configure whole display pipeline. It
> > determines relationships between mixers
Dne sreda, 13. junij 2018 ob 09:36:05 CEST je Maxime Ripard napisal(a):
> On Tue, Jun 12, 2018 at 10:00:33PM +0200, Jernej Skrabec wrote:
> > Function is useful when drm_of_find_possible_crtcs() can't be used and
> > custom parsing is needed. This can happen for example when there is a
> > node
Dne sreda, 13. junij 2018 ob 10:04:20 CEST je Chen-Yu Tsai napisal(a):
> On Wed, Jun 13, 2018 at 3:46 PM, Maxime Ripard
>
> wrote:
> > On Tue, Jun 12, 2018 at 10:00:23PM +0200, Jernej Skrabec wrote:
> >> TV TCONs are always connected to TV or HDMI encoder, so it doesn't make
> >> sense to check
Dne četrtek, 14. junij 2018 ob 19:16:46 CEST je Jagan Teki napisal(a):
> On Thu, Jun 14, 2018 at 8:04 PM, Jernej Škrabec
wrote:
> > Dne četrtek, 14. junij 2018 ob 09:12:41 CEST je Jagan Teki napisal(a):
> >> On Wed, Jun 13, 2018 at 1:30 AM, Jernej Skrabec
> >
> >
Dne četrtek, 14. junij 2018 ob 09:12:41 CEST je Jagan Teki napisal(a):
> On Wed, Jun 13, 2018 at 1:30 AM, Jernej Skrabec
wrote:
> > This series adds support for R40 HDMI pipeline. It is a bit special
> > than other already supported pipelines because it has additional unit
> > called TCON TOP
Dne četrtek, 31. maj 2018 ob 11:21:33 CEST je Maxime Ripard napisal(a):
> On Thu, May 24, 2018 at 03:01:09PM -0700, Chen-Yu Tsai wrote:
> > >> > > + if (tcon->quirks->needs_tcon_top) {
> > >> > > + struct device_node *np;
> > >> > > +
> > >> > > + np =
Dne ponedeljek, 04. junij 2018 ob 18:23:57 CEST je Maxime Ripard napisal(a):
> On Mon, Jun 04, 2018 at 05:09:56PM +0200, Jernej Škrabec wrote:
> > Dne ponedeljek, 04. junij 2018 ob 13:50:34 CEST je Maxime Ripard
napisal(a):
> > > On Fri, Jun 01, 2018 at 09:19:43AM -0700,
Dne ponedeljek, 04. junij 2018 ob 13:50:34 CEST je Maxime Ripard napisal(a):
> On Fri, Jun 01, 2018 at 09:19:43AM -0700, Chen-Yu Tsai wrote:
> > On Fri, Jun 1, 2018 at 8:29 AM, Maxime Ripard
wrote:
> > > On Thu, May 31, 2018 at 07:54:08PM +0200, Jernej Škrabec wrote:
> >
Dne nedelja, 01. julij 2018 ob 15:52:55 CEST je Chen-Yu Tsai napisal(a):
> On Sun, Jul 1, 2018 at 6:41 PM, Jernej Škrabec
wrote:
> > Dne četrtek, 28. junij 2018 ob 08:51:07 CEST je Chen-Yu Tsai napisal(a):
> >> On Thu, Jun 28, 2018 at 1:15 PM, Jernej Škrabec
> >
>
Dne nedelja, 01. julij 2018 ob 17:35:28 CEST je Chen-Yu Tsai napisal(a):
> On Sun, Jul 1, 2018 at 11:13 PM, Jernej Škrabec
wrote:
> > Dne nedelja, 01. julij 2018 ob 15:52:55 CEST je Chen-Yu Tsai napisal(a):
> >> On Sun, Jul 1, 2018 at 6:41 PM, Jernej Škrabec
> >
>
Dne petek, 29. junij 2018 ob 21:06:09 CEST je Jernej Škrabec napisal(a):
> Dne četrtek, 28. junij 2018 ob 20:25:43 CEST je Maxime Ripard napisal(a):
> > On Thu, Jun 28, 2018 at 06:48:50AM +0200, Jernej Škrabec wrote:
> > > Dne četrtek, 28. junij 2018 ob 04:06:52 CEST je Ch
Dne ponedeljek, 25. junij 2018 ob 05:51:41 CEST je Chen-Yu Tsai napisal(a):
> On Mon, Jun 25, 2018 at 3:52 AM, Jernej Škrabec
>
> wrote:
> > Dne četrtek, 21. junij 2018 ob 17:35:45 CEST je Jernej Škrabec napisal(a):
> >> Dne četrtek, 21. junij 2018 ob 03:23:27 CEST
Dne ponedeljek, 25. junij 2018 ob 14:02:40 CEST je Jernej Skrabec napisal(a):
> This series adds support for R40 HDMI pipeline. It is a bit special
> than other already supported pipelines because it has additional unit
> called TCON TOP responsible for relationship configuration between
> mixers,
Dne ponedeljek, 25. junij 2018 ob 10:14:52 CEST je Chen-Yu Tsai napisal(a):
> On Mon, Jun 25, 2018 at 3:58 PM, Jernej Škrabec
>
> wrote:
> > Dne ponedeljek, 25. junij 2018 ob 05:51:41 CEST je Chen-Yu Tsai
napisal(a):
> >> On Mon, Jun 25, 2018 at 3:52 AM, Jernej Š
Dne četrtek, 21. junij 2018 ob 17:35:45 CEST je Jernej Škrabec napisal(a):
> Dne četrtek, 21. junij 2018 ob 03:23:27 CEST je Chen-Yu Tsai napisal(a):
> > On Thu, Jun 21, 2018 at 3:37 AM, Jernej Škrabec
>
> wrote:
> > > Dne sobota, 16. junij 2018 ob 07:48:38 CEST
Dne sobota, 16. junij 2018 ob 07:48:38 CEST je Chen-Yu Tsai napisal(a):
> On Sat, Jun 16, 2018 at 1:33 AM, Jernej Škrabec
wrote:
> > Dne petek, 15. junij 2018 ob 19:13:17 CEST je Chen-Yu Tsai napisal(a):
> >> On Sat, Jun 16, 2018 at 12:41 AM, Jernej Škrabec
> >&
Dne nedelja, 01. julij 2018 ob 21:25:57 CEST je Jernej Škrabec napisal(a):
> Dne nedelja, 01. julij 2018 ob 17:35:28 CEST je Chen-Yu Tsai napisal(a):
> > On Sun, Jul 1, 2018 at 11:13 PM, Jernej Škrabec
>
> wrote:
> > > Dne nedelja, 01. julij 2018 ob 15:52:55 CEST
Dne petek, 29. junij 2018 ob 09:17:46 CEST je Maxime Ripard napisal(a):
> On Wed, Jun 27, 2018 at 10:58:28PM +0200, Jernej Škrabec wrote:
> > Dne sreda, 27. junij 2018 ob 20:25:00 CEST je Maxime Ripard napisal(a):
> > > Hi!
> > >
> > > On Wed, Jun 27, 2018
Dne četrtek, 28. junij 2018 ob 20:25:43 CEST je Maxime Ripard napisal(a):
> On Thu, Jun 28, 2018 at 06:48:50AM +0200, Jernej Škrabec wrote:
> > Dne četrtek, 28. junij 2018 ob 04:06:52 CEST je Chen-Yu Tsai napisal(a):
> > > On Mon, Jun 25, 2018 at 8:02 PM, Jernej Skrabec
>
Dne četrtek, 28. junij 2018 ob 04:22:36 CEST je Chen-Yu Tsai napisal(a):
> On Mon, Jun 25, 2018 at 8:02 PM, Jernej Skrabec
wrote:
> > Current DW HDMI PHY code never prepares and enables PHY clock after it is
> > created. It's just used as it is. This may work in some cases, but it's
> > clearly
Dne četrtek, 28. junij 2018 ob 04:24:02 CEST je Chen-Yu Tsai napisal(a):
> On Mon, Jun 25, 2018 at 8:02 PM, Jernej Skrabec
wrote:
> > DW HDMI PHY driver and PHY clock driver share same registers. Make sure
> > that DW HDMI PHY setup code doesn't change any clock related bits.
> > During
Dne četrtek, 28. junij 2018 ob 08:24:34 CEST je Chen-Yu Tsai napisal(a):
> On Thu, Jun 28, 2018 at 12:45 PM, Jernej Škrabec
>
> wrote:
> > Dne četrtek, 28. junij 2018 ob 03:51:31 CEST je Chen-Yu Tsai napisal(a):
> >> On Mon, Jun 25, 2018 at 8:02 PM, Jernej Skrabec
&
Dne četrtek, 28. junij 2018 ob 03:47:20 CEST je Chen-Yu Tsai napisal(a):
> Hi,
>
> So I'm late to the party, but...
>
> On Mon, Jun 25, 2018 at 8:02 PM, Jernej Skrabec
wrote:
> > As already described in DT binding, TCON TOP is responsible for
> > configuring display pipeline. In this initial
Dne četrtek, 28. junij 2018 ob 09:00:32 CEST je Chen-Yu Tsai napisal(a):
> On Thu, Jun 28, 2018 at 12:51 PM, Jernej Škrabec
>
> wrote:
> > Dne četrtek, 28. junij 2018 ob 04:19:55 CEST je Chen-Yu Tsai napisal(a):
> >> On Mon, Jun 25, 2018 at 8:02 PM, Jernej Skrabec
&g
Dne četrtek, 28. junij 2018 ob 03:53:36 CEST je Chen-Yu Tsai napisal(a):
> On Mon, Jun 25, 2018 at 8:02 PM, Jernej Skrabec
wrote:
> > sun4i_drv_add_endpoints() has a memory leak since it uses of_node_put()
> > when remote is equal to NULL and does nothing when remote has a valid
> > pointer.
> >
Dne četrtek, 28. junij 2018 ob 08:51:07 CEST je Chen-Yu Tsai napisal(a):
> On Thu, Jun 28, 2018 at 1:15 PM, Jernej Škrabec
wrote:
> > Dne četrtek, 28. junij 2018 ob 04:50:09 CEST je Chen-Yu Tsai napisal(a):
> >> On Mon, Jun 25, 2018 at 8:03 PM, Jernej Skrabec
> >
&
Hi,
Dne četrtek, 04. januar 2018 ob 15:45:18 CET je Chen-Yu Tsai napisal(a):
> On Sun, Dec 31, 2017 at 5:01 AM, Jernej Skrabec
wrote:
> > For example, A83T have nmp plls which are modelled as nkmp plls. Since k
> > is not specified, it has offset 0, shift 0 and lowest
Hi,
Dne petek, 05. januar 2018 ob 03:49:09 CET je Icenowy Zheng napisal(a):
> 于 2018年1月5日 GMT+08:00 上午2:52:10, Maxime Ripard <maxime.ripard@free-
electrons.com> 写到:
> >On Wed, Jan 03, 2018 at 10:32:26PM +0100, Jernej Škrabec wrote:
> >> Hi Rob,
> >>
> >&
Hi Rob,
Dne sreda, 03. januar 2018 ob 21:21:54 CET je Rob Herring napisal(a):
> On Sat, Dec 30, 2017 at 10:01:58PM +0100, Jernej Skrabec wrote:
> > This commit adds all necessary compatibles and descriptions needed to
> > implement A83T HDMI pipeline.
> >
> > Mixer is already properly described,
Hi,
Dne četrtek, 18. januar 2018 ob 11:58:41 CET je Maxime Ripard napisal(a):
> Hi,
>
> On Wed, Jan 17, 2018 at 09:14:11PM +0100, Jernej Skrabec wrote:
> > This commit changes formula from this:
> >
> > Freq = (parent_freq * N * K) / (M * P)
> >
> > to this:
> >
> > Freq = (parent_freq / M) *
Hi all,
Dne sreda, 10. januar 2018 ob 20:25:04 CET je Jernej Skrabec napisal(a):
> Parts of PHY code could be useful also for custom PHYs. For example,
> Allwinner A83T has custom PHY which is probably Synopsys gen2 PHY
> with few additional memory mapped registers, so most of the Synopsys PHY
>
Hi Laurent,
Dne torek, 09. januar 2018 ob 17:08:55 CET je Laurent Pinchart napisal(a):
> Hello,
>
> On Tuesday, 9 January 2018 17:58:46 EET Jernej Škrabec wrote:
> > Dne torek, 09. januar 2018 ob 11:43:08 CET je Archit Taneja napisal(a):
> > > On 12/31/2017 02:31
Hi Laurent,
Dne torek, 09. januar 2018 ob 14:30:22 CET je Laurent Pinchart napisal(a):
> Hi Jernej,
>
> Thank you for the patch.
>
> On Saturday, 30 December 2017 23:01:56 EET Jernej Skrabec wrote:
> > Parts of PHY code could be useful also for custom PHYs. For example,
> > Allwinner A83T has
Hi,
Dne torek, 09. januar 2018 ob 17:08:55 CET je Laurent Pinchart napisal(a):
> Hello,
>
> On Tuesday, 9 January 2018 17:58:46 EET Jernej Škrabec wrote:
> > Dne torek, 09. januar 2018 ob 11:43:08 CET je Archit Taneja napisal(a):
> > > On 12/31/2017 02:31 AM, Jernej Skr
Hi Archit,
Dne torek, 09. januar 2018 ob 11:43:08 CET je Archit Taneja napisal(a):
> On 12/31/2017 02:31 AM, Jernej Skrabec wrote:
> > Parts of PHY code could be useful also for custom PHYs. For example,
> > Allwinner A83T has custom PHY which is probably Synopsys gen2 PHY
> > with few additional
Hi Chen-Yu,
Dne ponedeljek, 08. januar 2018 ob 10:19:47 CET je Chen-Yu Tsai napisal(a):
> On Fri, Jan 5, 2018 at 3:28 AM, Jernej Škrabec <jernej.skra...@siol.net>
wrote:
> > Hi,
> >
> > Dne četrtek, 04. januar 2018 ob 15:45:18 CET je Chen-Yu Tsai napisal(a):
> >
Hi,
Dne ponedeljek, 29. januar 2018 ob 19:05:26 CET je Rob Herring napisal(a):
> On Wed, Jan 17, 2018 at 09:14:15PM +0100, Jernej Skrabec wrote:
> > This commit adds all necessary compatibles and descriptions needed to
> > implement A83T HDMI pipeline.
> >
> > Mixer is already properly
Hi Maxime,
Dne četrtek, 21. december 2017 ob 12:02:29 CET je Maxime Ripard napisal(a):
> Some clocks and resets supposed to drive the LVDS logic in the display
> engine have been overlooked when the driver was first introduced.
>
> Add those additional resources to the binding, and we'll deal
Dne četrtek, 21. junij 2018 ob 03:23:27 CEST je Chen-Yu Tsai napisal(a):
> On Thu, Jun 21, 2018 at 3:37 AM, Jernej Škrabec
wrote:
> > Dne sobota, 16. junij 2018 ob 07:48:38 CEST je Chen-Yu Tsai napisal(a):
> >> On Sat, Jun 16, 2018 at 1:33 AM, Jernej Škrabec
> >
> &g
Dne petek, 27. julij 2018 ob 17:42:08 CEST je Icenowy Zheng napisal(a):
> 在 2018-07-27 22:00,Maxime Ripard 写道:
>
> > On Fri, Jul 27, 2018 at 09:26:11PM +0800, Icenowy Zheng wrote:
> >> 于 2018年7月27日 GMT+08:00 下午8:56:15, Maxime Ripard
> >>
> >> 写到:
> >> >On Fri, Jul 27, 2018 at 01:12:57AM +0800,
Dne četrtek, 26. julij 2018 ob 19:12:50 CEST je Icenowy Zheng napisal(a):
> From: Jagan Teki
>
> Mixers in Allwinner have similar capabilities as others SoCs with DE2.
>
> Add support for them.
>
> Signed-off-by: Jagan Teki
> [Icenowy: Add mixer0]
> Signed-off-by: Icenowy Zheng
Reviewed-by:
Dne četrtek, 26. julij 2018 ob 19:12:54 CEST je Icenowy Zheng napisal(a):
> From: Jagan Teki
>
> Allwinner A64 have a display pipeline with 2 mixers/TCONs, the first
> TCON is connected to LCD and the second is to HDMI.
>
> The HDMI controller/PHY pair is similar to the one on H3/H5, but have
>
Dne četrtek, 26. julij 2018 ob 19:12:53 CEST je Icenowy Zheng napisal(a):
> From: Jagan Teki
>
> Allwinner A64 has two clock parents PLL_VIDEO0 and PLL_VIDEO1.
>
> Include these macros on dt-bindings so-that the same can be
> used while defining CCU clock phadles.
>
> Signed-off-by: Jagan Teki
Dne četrtek, 26. julij 2018 ob 19:12:57 CEST je Icenowy Zheng napisal(a):
> From: Jagan Teki
>
> Enable all necessary device tree nodes and add connector node to device
> trees for all supported A64 boards with HDMI.
>
> Signed-off-by: Jagan Teki
> [Icenowy: squash all board patches altogether
Dne četrtek, 26. julij 2018 ob 19:12:48 CEST je Icenowy Zheng napisal(a):
> From: Jagan Teki
>
> According to documentation and experience with other similar SoCs, video
> PLLs don't work stable if their output frequency is set below 192 MHz.
>
> Because of that, set minimal rate to both A64
Hi!
Dne sreda, 15. avgust 2018 ob 15:43:19 CEST je Icenowy Zheng napisal(a):
> 于 2018年8月15日 GMT+08:00 下午9:39:44, "Jernej Škrabec"
写到:
> >Hi!
> >
> >Dne sreda, 15. avgust 2018 ob 14:07:45 CEST je Icenowy Zheng
> >
> >napisal(a):
> >> Th
Hi!
Dne sreda, 15. avgust 2018 ob 14:07:45 CEST je Icenowy Zheng napisal(a):
> The glue in sun4i-drm of dw-hdmi currently doesn't set the clocks of
> dw-hdmi exclusively, which will lead the display fails to initialize in
> some situations.
>
> Add the exclusivity to sun8i-dw-hdmi and
Hi Maxime,
Dne sreda, 11. julij 2018 ob 10:30:36 CEST je Maxime Ripard napisal(a):
> On Tue, Jul 10, 2018 at 10:34:53PM +0200, Jernej Skrabec wrote:
> > This series fixes several issues found in R40 HDMI patch series after
> > it was applied. Conversation can be found here:
> >
Dne torek, 24. julij 2018 ob 18:04:49 CEST je Icenowy Zheng napisal(a):
> 在 2018-07-24二的 14:37 +0200,Maxime Ripard写道:
>
> > On Sun, Jul 22, 2018 at 04:43:56PM +0200, Jernej Škrabec wrote:
> > > Hi Maxime,
> > >
> > > Dne sreda, 11. julij
Dne torek, 04. september 2018 ob 11:04:21 CEST je Chen-Yu Tsai napisal(a):
> On Sun, Sep 2, 2018 at 3:27 PM Jernej Skrabec
wrote:
> > Support for mixer0, mixer1, writeback and rotation units is added.
> >
> > Signed-off-by: Jernej Skrabec
> > Signed-off-by: Icenowy Zheng
> > ---
> >
> >
Dne torek, 04. september 2018 ob 11:18:47 CEST je Chen-Yu Tsai napisal(a):
> On Sun, Sep 2, 2018 at 3:27 PM Jernej Skrabec
wrote:
> > Allwinner H6 SoC has multiplier N range between 1 and 254. Since parent
> > rate is 24MHz, intermediate result when calculating final rate easily
> > overflows 32
Hi Jagan,
Dne sreda, 05. september 2018 ob 09:57:54 CEST je Jagan Teki napisal(a):
> On Wed, Sep 5, 2018 at 1:21 PM, Maxime Ripard
wrote:
> > On Wed, Sep 05, 2018 at 12:56:03PM +0530, Jagan Teki wrote:
> >> On Tue, Sep 4, 2018 at 10:10 AM, Icenowy Zheng wrote:
> >> > From: Jagan Teki
> >> >
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