Hi Laurent,
Dne sreda, 30. november 2016 09.08.22 UTC+1 je oseba Laurent Pinchart
napisala:
>
> Hi Jernej,
>
> On Tuesday 29 Nov 2016 15:24:25 Jernej Skrabec wrote:
> > Dne torek, 29. november 2016 23.56.31 UTC+1 je oseba Laurent Pinchart
> > napisala:
> > >
Hi Maxime,
Dne torek, 29. november 2016 22.37.03 UTC+1 je oseba Maxime Ripard napisala:
>
> On Tue, Nov 29, 2016 at 11:18:35AM +0100, Jean-Francois Moine wrote:
> > This patchset series adds HDMI video support to the Allwinner
> > sun8i SoCs which include the display engine 2 (DE2).
> > The
Hi Jean-François,
Dne petek, 25. november 2016 11.22.20 UTC+1 je oseba Jean-François Moine
napisala:
>
> On Fri, 25 Nov 2016 17:41:51 +0800
> Icenowy Zheng > wrote:
>
> > After removing CLK_PLL_DE's assigned-clock, the kernel passes
> compilation.
>
> The 'pll-de' and 'de' must have a
Hi Laurent,
Dne torek, 29. november 2016 23.56.31 UTC+1 je oseba Laurent Pinchart
napisala:
>
> Hi Jernej,
>
> (CC'ing Kieran Bingham)
>
> On Tuesday 29 Nov 2016 14:47:20 Jernej Skrabec wrote:
> > Dne torek, 29. november 2016 22.37.03 UTC+1 je oseba Maxime Ripard
&
Add documentation about Allwinner DWC HDMI TX node, found in H3 SoC.
Signed-off-by: Jernej Skrabec <jernej.skra...@siol.net>
---
.../bindings/display/sunxi/sun4i-drm.txt | 158 -
1 file changed, 157 insertions(+), 1 deletion(-)
diff --git a/Documentation/devi
From: Icenowy Zheng <icen...@aosc.io>
The H3 SoC has a DesignWare HDMI controller with some Allwinner-specific
glue and custom PHY.
Since H3 and H5 have same HDMI controller, add related device node in
shared dtsi file.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
Signed-of
Enable HDMI output on all boards which include HDMI connector.
Signed-off-by: Jernej Skrabec <jernej.skra...@siol.net>
---
arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts | 33 +
arch/arm/boot/dts/sun8i-h3-beelink-x2.dts | 33 +
arch/ar
Allwinner H3 features DesignWare HDMI Transmitter paired with custom
PHY.
Add a glue driver for it.
For now, only video and CEC are supported. Audio will be supported at
a later time.
Signed-off-by: Jernej Skrabec <jernej.skra...@siol.net>
---
drivers/gpu/drm/sun4i/Kconfig
Thanks to Jens Kuske, who figured out that it is actually DW HDMI controller
and mapped scrambled register offsets to original ones.
Icenowy Zheng (1):
ARM: sun8i: h3: Add DesignWare HDMI controller node
Jernej Skrabec (6):
drm: bridge: Enable polling hpd event in dw_hdmi
drm: bridge: Enable
Some custom phys don't support hpd interrupts. Add support for polling
such events.
Signed-off-by: Jernej Skrabec <jernej.skra...@siol.net>
---
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/bridge/synop
.
Signed-off-by: Jernej Skrabec <jernej.skra...@siol.net>
---
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
index 09cb5a3e4c71..729692
When setting the HDMI clock of H3, the PLL_VIDEO clock needs to be set.
Add CLK_SET_RATE_PARENT flag for H3 HDMI clock.
Signed-off-by: Jernej Skrabec <jernej.skra...@siol.net>
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 2 +-
1 fil
/linux-1/commits/de2_impr_for_next
Best regards,
Jernej
Jernej Skrabec (17):
drm/sun4i: Refactor DE2 code
drm/sun4i: Start using layer id in DE2 driver
drm/sun4i: Add constraints checking to DE2 driver
drm/sun4i: Use values calculated by atomic check
drm/sun4i: Reorder some code in DE2
Now that we have all required bits, add support for YUV formats.
DRM subsystem doesn't know YUV411 semi-planar format, so leave that out
for now.
Signed-off-by: Jernej Skrabec <jernej.skra...@siol.net>
---
drivers/gpu/drm/sun4i/sun8i_layer.c | 56 +-
drivers/gpu/drm
Scaler library currently supports scaling only RGB planes on VI planes.
Coefficients and algorithm which ones to select are taken from BSP driver.
Signed-off-by: Jernej Skrabec <jernej.skra...@siol.net>
---
drivers/gpu/drm/sun4i/Makefile | 2 +-
drivers/gpu/drm/sun4i/sun8i_sc
Change zpos of VI plane so it is above primary.
Clearly this works only if mixer supports only one VI plane, but it is
good enough for testing and developing.
Proper solution with zpos property should be developed instead.
Signed-off-by: Jernej Skrabec <jernej.skra...@siol.net>
---
drive
Support for multiple UI planes can now be easily enabled just by adding
more planes with different index.
For now, add immutable zpos property.
Signed-off-by: Jernej Skrabec <jernej.skra...@siol.net>
---
drivers/gpu/drm/sun4i/sun8i_layer.c | 38 +
This commit adds basic support for VI planes. They are meant for video
overlay and because of that they support YUV formats too. However, using
YUV planes is not straightforward, so only RGB support for now.
Signed-off-by: Jernej Skrabec <jernej.skra...@siol.net>
---
drivers/gpu/drm
Currently only a few RGB formats are supported by the DE2 driver. Add
support for all formats supported by the HW.
Signed-off-by: Jernej Skrabec <jernej.skra...@siol.net>
---
drivers/gpu/drm/sun4i/sun8i_layer.c | 19 -
drivers/gpu/drm/sun4i/sun8i_mixer.c
No all SoCs support scaling on all channels. For example, V3s support
scaling only on VI channels. Because of that, add additional
configuration bitmask which tells which channel support scaler.
Signed-off-by: Jernej Skrabec <jernej.skra...@siol.net>
---
drivers/gpu/drm/sun4i/sun8i_mixer
This commit expands translation of DRM YUV format to HW specific
information.
It doesn't do any functional changes.
Signed-off-by: Jernej Skrabec <jernej.skra...@siol.net>
---
drivers/gpu/drm/sun4i/sun8i_mixer.c | 147 +++-
drivers/gpu/drm/sun4i/sun8i_m
Now that we have properly clipped coordinates in plane state structure,
use them.
This also fixes bug where source x and y were adjusted for negative
value, but width and height weren't. It wasn't discovered because
primary plane usually doesn't have negative coordinates.
Signed-off-by: Jernej
While DE2 driver works, parts of the code are not in optimal place. Reorder
it so it will be easier to support multiple planes.
This commit doesn't do any functional change besides removing two not
very useful debug messages.
Signed-off-by: Jernej Skrabec <jernej.skra...@siol.net>
---
d
Since current DE2 driver doesn't know how to scale yet, add atomic check
function which checks that.
Nice side effect of that function is that populates clipped coordinates
and checks visibility of the plane. That data will be used in the
future.
Signed-off-by: Jernej Skrabec <jernej.s
Basic principle of operation when using YUV framebuffer is that chroma
planes have to be upscaled to same size as luma.
Because of that, expand DE2 scaler library to support that.
BSP driver uses another set of FIR filter coefficients for YUV planes.
Signed-off-by: Jernej Skrabec <jernej.s
DE2 have many CSC units - channel input CSC, channel output CSC and
mixer output CSC and maybe more.
Fortunately, they have all same register layout, only base offsets
differs.
Add support only for channel output CSC for now.
Signed-off-by: Jernej Skrabec <jernej.skra...@siol.net>
---
d
channel. This
simplifies things, since layer parameter can be then used as channel
selection.
Signed-off-by: Jernej Skrabec <jernej.skra...@siol.net>
---
drivers/gpu/drm/sun4i/sun8i_layer.c | 2 +-
drivers/gpu/drm/sun4i/sun8i_mixer.c | 31 +++
2 files chang
Signed-off-by: Jernej Skrabec <jernej.skra...@siol.net>
---
drivers/gpu/drm/sun4i/sun8i_mixer.c | 1 +
drivers/gpu/drm/sun4i/sun8i_mixer.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c
b/drivers/gpu/drm/sun4i/sun8i_mixer.c
index 7c9c87a0535b..2276ef
Calculate scaling parameters and call appropriate scaler set up
function.
Signed-off-by: Jernej Skrabec <jernej.skra...@siol.net>
---
drivers/gpu/drm/sun4i/sun8i_layer.c | 12 +++-
drivers/gpu/drm/sun4i/sun8i_mixer.c | 115 +---
drivers/gpu/drm
and removes settings which are not really needed.
Signed-off-by: Jernej Skrabec <jernej.skra...@siol.net>
---
drivers/gpu/drm/sun4i/sun8i_mixer.c | 65 +++--
drivers/gpu/drm/sun4i/sun8i_mixer.h | 31 --
2 files changed, 47 insertions(+), 49 del
it and so on.
Signed-off-by: Jernej Skrabec <jernej.skra...@siol.net>
---
drivers/gpu/drm/sun4i/sun8i_mixer.c | 28 +---
1 file changed, 17 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c
b/drivers/gpu/drm/sun4i/sun8i_mixer.c
sun8i_layer.c to sun8i_mixer.c
- renames function and structure names so it is apparent where they
belong to
No functional change is made.
Signed-off-by: Jernej Skrabec <jernej.skra...@siol.net>
---
drivers/gpu/drm/sun4i/Makefile | 2 +-
drivers/gpu/drm/sun4i/sun8i_layer.c
they can't be blended together or scaled independetly when they are set
to same channel. Because of that, always use only first overlay in each
channel.
Signed-off-by: Jernej Skrabec <jernej.skra...@siol.net>
---
drivers/gpu/drm/sun4i/sun8i_layer.c | 18 -
drivers/gpu/drm
Now that we have all required bits, add support for YUV formats.
DRM subsystem doesn't know YUV411 semi-planar format, so leave that out
for now.
Signed-off-by: Jernej Skrabec <jernej.skra...@siol.net>
---
drivers/gpu/drm/sun4i/sun8i_vi_layer.c | 127 ++---
Color attribute have same format troughout the whole driver.
Rename macro, add comment with simple explanation and remove redundant
definitions.
Signed-off-by: Jernej Skrabec <jernej.skra...@siol.net>
---
drivers/gpu/drm/sun4i/sun8i_mixer.c | 8 +---
drivers/gpu/drm/sun4i/sun8i_mixer
This commit adds basic support for VI planes. They are meant for video
overlay and because of that they support YUV formats too. However, using
YUV format is not straightforward, so only RGB formats are supported for
now.
Signed-off-by: Jernej Skrabec <jernej.skra...@siol.net>
---
drive
Format mask is one bit too short. Fix it.
Fixes: 9d75b8c0b999 (drm/sun4i: add support for Allwinner DE2 mixers)
Signed-off-by: Jernej Skrabec <jernej.skra...@siol.net>
---
drivers/gpu/drm/sun4i/sun8i_mixer.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/g
Premultiply and color key control registers are already set to zero by
initialization code few lines above. Furthermore, it seems that
colorkeying doesn't really work. It's not used in BSP driver and
experiments with it all failed.
Just remove the code.
Signed-off-by: Jernej Skrabec <jernej.s
max supported scaler factor for each type
of scaler
Jernej Skrabec (27):
drm/sun4i: Fix format mask in DE2 driver
drm/sun4i: Rename DE2 RGB format macros
drm/sun4i: Remove setting alpha mode in DE2 driver
drm/sun4i: Fix debug message in DE2
drm/sun4i: Remove setting default values in DE2 dri
Now that we have properly clipped coordinates in plane state structure,
use them.
This also fixes bug where source x and y were adjusted for negative
value, but width and height weren't. It wasn't discovered because
primary plane usually doesn't have negative coordinates.
Signed-off-by: Jernej
is supported
Default mode (0) considers pixel alpha value or 0xff if pixel has
no alpha information. Global alpha value is ignored in this case.
Because of that, just remove the code.
Signed-off-by: Jernej Skrabec <jernej.skra...@siol.net>
---
drivers/gpu/drm/sun4i/sun8i_mixer.
Basic principle of operation when using YUV framebuffer is that chroma
planes have to be upscaled to same size as luma.
Because of that, expand DE2 scaler library to support that.
BSP driver uses another set of FIR filter coefficients for YUV planes.
Signed-off-by: Jernej Skrabec <jernej.s
This commit expands translation of DRM YUV format to HW specific
information.
It doesn't do any functional changes.
Signed-off-by: Jernej Skrabec <jernej.skra...@siol.net>
---
drivers/gpu/drm/sun4i/sun8i_mixer.c| 136 +
drivers/gpu/drm/sun4i/sun8i_m
Current RGB formats macros are actually not specific to UI planes.
Rename it to something more universal and introduce shift macro.
Signed-off-by: Jernej Skrabec <jernej.skra...@siol.net>
---
drivers/gpu/drm/sun4i/sun8i_mixer.c | 7 ---
drivers/gpu/drm/sun4i/sun8i_mixer.h | 8 +
Debug message would print "Enabling" even when disabling plane.
Fix it.
Fixes: 9d75b8c0b999 (drm/sun4i: add support for Allwinner DE2 mixers)
Signed-off-by: Jernej Skrabec <jernej.skra...@siol.net>
---
drivers/gpu/drm/sun4i/sun8i_mixer.c | 3 ++-
1 file changed, 2 insertion
BSP driver always sets blend mode for all channels, no matter if they
are really used or not. Do the same here.
The exact meaning of the value is not exactly known, but BSP driver
mentions "SRC OVER" and by digging through code some more info can be
found.
Signed-off-by: Jern
Change zpos of VI plane so it is above primary.
Clearly this works only if mixer supports only one VI plane, but it is
good enough for testing and developing.
Proper solution with zpos property should be developed instead.
Signed-off-by: Jernej Skrabec <jernej.skra...@siol.net>
---
drive
Line width is a property of a framebuffer and it belongs to
sun8i_mixer_update_layer_buffer(). This will became even more obvious
when support for multi-plane formats will be added.
Signed-off-by: Jernej Skrabec <jernej.skra...@siol.net>
---
drivers/gpu/drm/sun4i/sun8i_mixer.
Scaling is currently supported only for RGB framebuffers
Coefficients and algorithm which coefficients to select are taken
from BSP driver.
Signed-off-by: Jernej Skrabec <jernej.skra...@siol.net>
---
drivers/gpu/drm/sun4i/Makefile | 3 +-
drivers/gpu/drm/sun4i/sun8i_mixer.h
There is no point having code which sets interlace mode of mixer in
channel related function. Interlace mode will only change when CRTC
state will change, so let's move it to the block which is executed only
when primary plane state is changed.
Signed-off-by: Jernej Skrabec <jernej.s
Since current DE2 driver doesn't know how to scale yet, add atomic check
function which checks that.
Nice side effect of that function is that populates clipped coordinates
and checks visibility of the plane. That data will be used in the
future.
Signed-off-by: Jernej Skrabec <jernej.s
with such configuration.
Signed-off-by: Jernej Skrabec <jernej.skra...@siol.net>
---
drivers/gpu/drm/sun4i/sun8i_mixer.c | 5 +++--
drivers/gpu/drm/sun4i/sun8i_mixer.h | 13 ++---
2 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c
b/drivers/gpu/drm
Currently only a few RGB formats are supported by the DE2 driver. Add
support for all formats supported by the HW.
Signed-off-by: Jernej Skrabec <jernej.skra...@siol.net>
---
drivers/gpu/drm/sun4i/sun8i_layer.c | 19 -
drivers/gpu/drm/sun4i/sun8i_mixer.c
Support for multiple UI planes can now be easily enabled just by adding
more planes with different index.
For now, add immutable zpos property.
Signed-off-by: Jernej Skrabec <jernej.skra...@siol.net>
---
drivers/gpu/drm/sun4i/sun8i_layer.c | 38 +
Base addresses of channel output CSC (CCSC) depends whether mixer in
question is first or second and if it is second, if supports VEP or not.
This new property will tell which set of base addresses to take.
Signed-off-by: Jernej Skrabec <jernej.skra...@siol.net>
---
drivers/gpu/drm
No all SoCs support scaling on all channels. For example, V3s support
scaling only on VI channels. Because of that, add additional
configuration bitmask which tells which channel support scaler.
Signed-off-by: Jernej Skrabec <jernej.skra...@siol.net>
---
drivers/gpu/drm/sun4i/sun8i_mixer.
Channel size should be set every time plane is changed, not only when
primary plane changes. Current code works only because only one
(primary) plane is supported at the moment.
Signed-off-by: Jernej Skrabec <jernej.skra...@siol.net>
---
drivers/gpu/drm/sun4i/sun8i_mixer.c | 14 ++-
DE2 have many CSC units - channel input CSC, channel output CSC and
mixer output CSC and maybe more.
Fortunately, they have all same register layout, only base offsets
differs.
Add support only for channel output CSC for now.
Signed-off-by: Jernej Skrabec <jernej.skra...@siol.net>
---
d
min_scale and max_scale in sun8i_vi_layer_atomic_check() can be used
without initialization.
Fix that.
Fixes: b862a648de3b (drm/sun4i: Add support for HW scaling to DE2)
Signed-off-by: Jernej Skrabec <jernej.skra...@siol.net>
---
drivers/gpu/drm/sun4i/sun8i_vi_layer.c | 3 +++
1 file c
Both mixers have similar capabilities as others SoCs with DE2.
First mixer has 1 VI and 3 UI planes and supports HW scaling on all
planes.
Second mixer has 1 VI and 1 UI planes and also supports HW scaling on
all planes.
Signed-off-by: Jernej Skrabec <jernej.skra...@siol.net>
---
drive
pipeline.
For now, only TCON TV is supported.
Signed-off-by: Jernej Skrabec <jernej.skra...@siol.net>
---
drivers/gpu/drm/sun4i/sun4i_tcon.c | 39 ++
1 file changed, 39 insertions(+)
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c
b/drivers/gpu/drm/sun4i/sun4i_
Some DW HDMI PHYs like those found in A64 and R40 SoCs, can select
between two clock parents.
Add code which reads second PLL from DT.
Signed-off-by: Jernej Skrabec <jernej.skra...@siol.net>
---
drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h | 2 ++
drivers/gpu/drm/sun4i/sun8i_hdmi_phy.
According to documentation and experience with other similar SoCs, video
PLLs don't work stable if their output frequency is set below 192 MHz.
Because of that, set minimal rate to both R40 video PLLs to 192 MHz.
Signed-off-by: Jernej Skrabec <jernej.skra...@siol.net>
---
drivers/clk/su
and TCONS
Something similar also existed in previous SoCs, except that it was part
of first TCON.
Signed-off-by: Jernej Skrabec <jernej.skra...@siol.net>
---
drivers/gpu/drm/sun4i/Makefile | 3 +-
drivers/gpu/drm/sun4i/sun8i_tcon_top.c | 256 +
drivers/g
Video PLLs need to be referenced in R40 DT as possible HDMI PHY parent.
Export them.
Signed-off-by: Jernej Skrabec <jernej.skra...@siol.net>
---
drivers/clk/sunxi-ng/ccu-sun8i-r40.h | 8 ++--
include/dt-bindings/clock/sun8i-r40-ccu.h | 4
2 files changed, 10 insertions
Display related peripherals need precise clocks to operate correctly.
Allow DE2, TCONs and HDMI to set parent clock.
Signed-off-by: Jernej Skrabec <jernej.skra...@siol.net>
---
drivers/clk/sunxi-ng/ccu-sun8i-r40.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff
DMI
- mixer1 <> TCON-TV0 <> HDMI
- mixer1 <> TCON-TV1 <> HDMI
Please review.
Best regards,
Jernej
Jernej Skrabec (15):
clk: sunxi-ng: r40: Add minimal rate for video PLLs
clk: sunxi-ng: r40: Allow setting parent rate to display related
clocks
clk: sunxi-ng: r40: Exp
PHY is the same as in H3, except it can switch between two clock
parents.
Signed-off-by: Jernej Skrabec <jernej.skra...@siol.net>
---
drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
b/drivers/g
Expand HDMI PHY clock driver to support second clock parent.
Signed-off-by: Jernej Skrabec <jernej.skra...@siol.net>
---
drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h | 6 +-
drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 29 ++-
drivers/gpu/drm/sun4i/sun8i_hdmi_phy_clk.
When TCON sets up TCON TOP, it needs to know mixer index. Here we do that
by setting engine ID to number provided in mixer index quirk.
Signed-off-by: Jernej Skrabec <jernej.skra...@siol.net>
---
drivers/gpu/drm/sun4i/sun8i_mixer.c | 4 ++--
drivers/gpu/drm/sun4i/sun8i_mixer.h | 2 ++
2
if SoC has TCON TOP and TCON is TV TCON.
New compatible is added for DWC HDMI PHY, which has additional clock
specified.
Signed-off-by: Jernej Skrabec <jernej.skra...@siol.net>
---
.../bindings/display/sunxi/sun4i-drm.txt | 16 ++--
1 file changed, 14 insertions(+), 2 del
Since HDMI can be considered as main output, most capable mixer is
connected to it (mixer0).
Signed-off-by: Jernej Skrabec <jernej.skra...@siol.net>
---
.../boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 50 +++
1 file changed, 50 insertions(+)
diff --git a/arch/arm/boot/dts
Add all entries needed for HDMI to function properly.
Since R40 has highly configurable pipeline, both mixers and both TCON
TVs are added. Board specific DT should then connect them together to
best fit the purpose of the board.
Signed-off-by: Jernej Skrabec <jernej.skra...@siol.net>
---
TCON TOP main purpose is to configure whole display pipeline. It
determines relationships between mixers and TCONs, selects source TCON
for HDMI, muxes LCD and TV encoder GPIO output, selects TV encoder
clock source and contains additional TV TCON and DSI gates.
Signed-off-by: Jernej Skrabec
If SoC has TCON TOP unit, it has to be configured from TCON, since it
has all information needed. Additionally, if it is TCON TV, it must also
enable bus gate inside TCON TOP unit.
Add support for such TCONs.
Signed-off-by: Jernej Skrabec <jernej.skra...@siol.net>
---
drivers/gpu/drm
DW HDMI PHY driver and PHY clock driver share same registers. Make sure
that DW HDMI PHY setup code doesn't change any clock related bits and
set them to 0 during initialization.
Signed-off-by: Jernej Skrabec
---
drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h | 2 +-
drivers/gpu/drm/sun4i
Both mixers have similar capabilities as others SoCs with DE2.
First mixer has 1 VI and 3 UI planes and supports HW scaling on all
planes.
Second mixer has 1 VI and 1 UI planes and also supports HW scaling on
all planes.
Signed-off-by: Jernej Skrabec
---
drivers/gpu/drm/sun4i/sun8i_mixer.c
Function is useful when drm_of_find_possible_crtcs() can't be used and
custom parsing is needed. This can happen for example when there is a
node with multiple muxes between crtc and encoder.
Signed-off-by: Jernej Skrabec
---
drivers/gpu/drm/drm_of.c | 4 ++--
include/drm/drm_of.h | 8
TV TCONs connected to TCON TOP have to enable additional gate in order
to work.
Add support for such TCONs.
Signed-off-by: Jernej Skrabec
---
drivers/gpu/drm/sun4i/sun4i_tcon.c | 11 +++
drivers/gpu/drm/sun4i/sun4i_tcon.h | 4
2 files changed, 15 insertions(+)
diff --git
drm_of_find_possible_crtcs() doesn't work when DW HDMI encoder is
connected to TCON (crtc) through mux in TCON TOP.
In that case TCON TOP HDMI mux input port has to be manually traversed
and checked if it matches any known crtc.
Signed-off-by: Jernej Skrabec
---
drivers/gpu/drm/sun4i
LVDS and RGB interfaces are always connected to TCONs which have channel
0. It doesn't make sense to try to init them on TV TCONs.
Add a check if TCON has channel 0 before trying to init LVDS or RGB
interface.
Signed-off-by: Jernej Skrabec
---
drivers/gpu/drm/sun4i/sun4i_tcon.c | 32
PHY is the same as in H3, except it can switch between two clock
parents.
Signed-off-by: Jernej Skrabec
---
drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
sun4i_drv_add_endpoints() has a memory leak since it uses of_node_put()
when remote is equal to NULL and does nothing when remote has a valid
pointer.
Invert the logic to fix memory leak.
Signed-off-by: Jernej Skrabec
---
drivers/gpu/drm/sun4i/sun4i_drv.c | 3 ++-
1 file changed, 2 insertions
Display related peripherals need precise clocks to operate correctly.
Allow DE2, TCONs and HDMI to set parent clock.
Signed-off-by: Jernej Skrabec
---
drivers/clk/sunxi-ng/ccu-sun8i-r40.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu
Some DW HDMI PHYs, like those found in A64 and R40 SoCs, can select
between two clock parents.
Add code which reads second PLL from DT.
Signed-off-by: Jernej Skrabec
---
drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h | 2 ++
drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 20 +++-
2 files
selecting
matching input by subtracting 1 for the next round. This work even if
there is only one input and output.
Signed-off-by: Jernej Skrabec
---
drivers/gpu/drm/sun4i/sun4i_tcon.c | 22 ++
1 file changed, 18 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu
doesn't do any functional change.
Signed-off-by: Jernej Skrabec
---
drivers/gpu/drm/sun4i/sun4i_drv.c | 84 +--
1 file changed, 46 insertions(+), 38 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c
b/drivers/gpu/drm/sun4i/sun4i_drv.c
index e15fa2389e3f
TCON description is expanded with R40 TV TCON compatibles. TV TCONs,
which are connected to TCON TOP muxes, such as those on R40 SoC, also
needs additional clock gate to be specified.
Signed-off-by: Jernej Skrabec
---
.../devicetree/bindings/display/sunxi/sun4i-drm.txt | 5 -
1
Expand HDMI PHY clock driver to support second clock parent.
Signed-off-by: Jernej Skrabec
---
drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h | 4 +-
drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 3 +-
drivers/gpu/drm/sun4i/sun8i_hdmi_phy_clk.c | 90 --
3 files changed, 73
Video PLLs need to be referenced in R40 DT as possible HDMI PHY parent.
Export them.
Reviewed-by: Rob Herring
Signed-off-by: Jernej Skrabec
---
drivers/clk/sunxi-ng/ccu-sun8i-r40.h | 8 ++--
include/dt-bindings/clock/sun8i-r40-ccu.h | 4
2 files changed, 10 insertions(+), 2
and TCONS
Something similar also existed in previous SoCs, except that it was part
of first TCON.
Signed-off-by: Jernej Skrabec
---
drivers/gpu/drm/sun4i/Makefile | 3 +-
drivers/gpu/drm/sun4i/sun8i_tcon_top.c | 248 +
drivers/gpu/drm/sun4i/sun8i_tcon_top.h | 38
According to documentation and experience with other similar SoCs, video
PLLs don't work stable if their output frequency is set below 192 MHz.
Because of that, set minimal rate to both R40 video PLLs to 192 MHz.
Signed-off-by: Jernej Skrabec
---
drivers/clk/sunxi-ng/ccu-sun8i-r40.c | 46
ed clk_hw_register_gate() instead of custom gate registration code
- Reworked TCON TOP to be part of of-graph. Because of that, a lot of
new patches were added.
- Droped mixer index quirk patch
- Reworked TCON support for TCON TOP
- Updated commit messages
Jernej Skrabec (27):
clk: sunxi-ng: r
TCON TOP is different from other nodes in graph by having 3 input and 3
output ports. Additionally, connection to TV TCON might lead back to
HDMI mux input port, creating loops.
Add support for traversing such graph.
Signed-off-by: Jernej Skrabec
---
drivers/gpu/drm/sun4i/sun4i_drv.c | 24
R40 DE2 mixers are similar to those found in A83T, except it needs
different clock settings.
Add a compatibles for them.
Signed-off-by: Jernej Skrabec
---
Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation
R40 TV TCON is similar to the A83T TV TCON, except that it needs
additional gate to be enabled.
Add support for it.
Signed-off-by: Jernej Skrabec
---
drivers/gpu/drm/sun4i/sun4i_tcon.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c
b/drivers/gpu
TCON TOP main purpose is to configure whole display pipeline. It
determines relationships between mixers and TCONs, selects source TCON
for HDMI, muxes LCD and TV encoder GPIO output, selects TV encoder
clock source and contains additional TV TCON and DSI gates.
Signed-off-by: Jernej Skrabec
Since HDMI can be considered as main output, most capable mixer is
connected to it (mixer0).
Signed-off-by: Jernej Skrabec
---
.../boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 45 +++
1 file changed, 45 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
riant")
Signed-off-by: Jernej Skrabec
---
drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
index 5a52fc489a9d..966688f04741 100644
--- a/drivers/gpu
A64 HDMI PHY is similar to H3 HDMI PHY except it has two possible PLL
clock parents. It is compatible to other HDMI PHYs, like that found in
R40.
Signed-off-by: Jernej Skrabec
---
Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt | 4 +++-
1 file changed, 3 insertions(+), 1 deletion
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