[PATCH 3/4] drm: Add __arm defines to DRM

Add __arm defines to specify behavior specific for an ARM processor. Signed-off-by: Jordan Crouse jcro...@codeaurora.org --- drivers/gpu/drm/drm_bufs.c |2 +- drivers/gpu/drm/drm_vm.c | 14 +- 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm

[PATCH 4/4] drm: Make sure the DRM offset matches the CPU

The pgoff option in mmap() is defined as an unsigned long so the offset generated by DRM needs to fit into BITS_PER_LONG for the CPU in question. Signed-off-by: Jordan Crouse jcro...@codeaurora.org --- drivers/gpu/drm/drm_gem.c | 10 ++ 1 files changed, 10 insertions(+), 0 deletions

Re: [PATCH 1/2] drm: rework PCI/platform driver interface.

On 02/06/2011 08:09 PM, Dave Airlie wrote: This abstracts the pci/platform interface out a step further, we can go further but this is far enough for now to allow USB to be plugged in. The drivers now just call the init code directly for their device type. Signed-off-by: Dave

Re: GPU lockup dumping

On 05/23/2012 08:51 AM, Jerome Glisse wrote: On Wed, May 23, 2012 at 5:27 AM, Dave Airlieairl...@gmail.com wrote: On Thu, May 17, 2012 at 7:28 PM,j.gli...@gmail.com wrote: So here is improved patchset, where i splited ground work necessary for the dumping into their own patch. The debugfs

Re: [RFCv1 2/2] drm/msm: basic KMS driver for snapdragon

On 07/05/2013 01:53 PM, Rob Clark wrote: The snapdragon chips have multiple different display controllers, depending on which chip variant/version. (As far as I can tell, current devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And then external to the display controller are

Re: [Freedreno] [PATCH 1/4] drm/msm: remove qcom, gpu-pwrlevels bindings

On Mon, Jan 30, 2017 at 01:35:47PM -0500, Rob Clark wrote: > On Mon, Jan 30, 2017 at 1:21 PM, Eric Anholt wrote: > > Rob Clark writes: > > > >> The plan is to use the OPP bindings. For now, remove the documentation > >> for qcom,gpu-pwrlevels, and make the

Re: [Freedreno] [RFC] drm/msm/adreno: clean up gpu bindings

On Thu, Jan 26, 2017 at 05:03:54PM -0500, Rob Clark wrote: > On Thu, Jan 26, 2017 at 4:09 PM, Rob Herring wrote: > > On Thu, Jan 26, 2017 at 1:51 PM, Rob Clark wrote: > >> On Thu, Jan 26, 2017 at 2:11 PM, Rob Herring wrote: > >>> On Tue,

Re: [PATCH 11/11] drm/msm: Implement preemption for A5XX targets

On Wed, Feb 08, 2017 at 12:30:08PM -0800, Stephen Boyd wrote: > On 02/06/2017 09:39 AM, Jordan Crouse wrote: > > diff --git a/drivers/gpu/drm/msm/adreno/a5xx_preempt.c > > b/drivers/gpu/drm/msm/adreno/a5xx_preempt.c > > new file mode 100644 > > index 000..348ead7

[PATCH 02/11] drm/msm: Improve the zap shader

Simply the code, use snprintf correctly and make sure that we memset the rest of the segment if the memory size in the ELF file is larger than the file size. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- drivers/gpu/drm/msm/adreno/a5xx_gpu.

[PATCH 05/11] drm/msm: get an iova from the address space instead of an id

index into a list of domains, we need to maintain a list of them. Luckily the list will be pretty small; even with dynamic address spaces we wouldn't ever see more than two or three. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 8 +- d

[PATCH 07/11] drm/msm: Remove memptrs->wptr

memptrs->wptr seems to be unused. Remove it to avoid confusing the upcoming preemption code. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 3 --- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 - 2 files changed, 4 deletions(-) d

[PATCH 11/11] drm/msm: Implement preemption for A5XX targets

Implement preemption for A5XX targets - this allows multiple ringbuffers for different priorities with automatic preemption of a lower priority ringbuffer if a higher one is ready. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- drivers/gpu/drm/msm/Makefile

[PATCH 10/11] drm/msm: Make the value of RB_CNTL (almost) generic

but that only needs to be done once and doesn't affect A5XX so we can or in the value at init time. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 12 +++- drivers/gpu/drm/msm/msm_gpu.h | 5 + 2 files chang

[PATCH 03/11] drm/msm: Add hint to DRM_IOCTL_MSM_GEM_INFO to return an object IOVA

Modify the 'pad' member of struct drm_msm_gem_info to 'hint'. If the user sets 'hint' to non-zero it means that they want a IOVA for the GEM object instead of a mmap() offset. Return the iova in the 'offset' member. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- drivers/gpu/d

[PATCH 09/11] drm/msm: Shadow current pointer in the ring until command is complete

load for non-preemption targets should be minimal. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 9 +++-- drivers/gpu/drm/msm/msm_ringbuffer.c| 1 + drivers/gpu/drm/msm/msm_ringbuffer.h| 12 3 files chang

[PATCH 01/11] drm/msm: Make sure to detach the MMU during GPU cleanup

We should be detaching the MMU before destroying the address space. To do this cleanly, the detach has to happen in adreno_gpu_cleanup() because it needs access to structs in adreno_gpu.c. Plus it is better symmetry to have the attach and detach at the same code level. Signed-off-by: Jordan

[PATCH 06/11] drm/msm: Add a struct to pass configuration to msm_gpu_init()

The amount of information that we need to pass into msm_gpu_init() is steadily increasing, so add a new struct to stabilize the function call and make it easier to add new configuration down the line. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- drivers/gpu/drm/msm/

[PATCH 04/11] drm/msm: Remove idle function hook

There isn't any generic code that uses ->idle so remove it. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 4 ++-- drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 4 ++-- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 9 - drivers/gp

[PATCH 00/11] drm/msm: A5XX preemption

). Jordan Jordan Crouse (11): drm/msm: Make sure to detach the MMU during GPU cleanup drm/msm: Improve the zap shader drm/msm: Add hint to DRM_IOCTL_MSM_GEM_INFO to return an object IOVA drm/msm: Remove idle function hook drm/msm: get an iova from the address space instead of an id drm/msm

[PATCH 08/11] drm/msm: Support multiple ringbuffers

specific so this code just allows for the possibility but still only defines one ringbuffer for each target family. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 9 +- drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 9 +- drivers/gpu/drm/msm/

Re: [RFC] drm/msm/adreno: clean up gpu bindings

On Tue, Jan 24, 2017 at 12:11:32PM -0500, Rob Clark wrote: > So, cleaning up the GPU bindings is something that has been on my TODO > list for a while, but always $bigger_fires. Existing bindings are a bit > ugly, but served a purpose when too many of the other drivers the GPU > depends on where

Re: [Freedreno] [PATCH 10/12] firmware: qcom_scm: Add qcom_scm_gpu_zap_resume()

On Sat, Jan 14, 2017 at 11:20:58PM -0600, Andy Gross wrote: > + Stanimir > > On Sat, Jan 14, 2017 at 09:49:01PM -0600, Andy Gross wrote: > > On Fri, Jan 13, 2017 at 04:24:38PM -0700, Jordan Crouse wrote: > > > On Fri, Jan 13, 2017 at 11:12:41AM -0600, Andy Gross wrote

Re: [Freedreno] [PATCH] firmware: qcom_scm: Add set remote state API

On Mon, Jan 16, 2017 at 11:56:18PM -0600, Andy Gross wrote: > This patch adds a set remote state SCM API. This will be used by the > Venus and GPU subsystems to set state on the remote processors. > > This work was based on two patch sets by Jordan Crouse and Stanimir > Varbanov.

Re: [PATCH 10/12] firmware: qcom_scm: Add qcom_scm_gpu_zap_resume()

On Fri, Jan 13, 2017 at 11:12:41AM -0600, Andy Gross wrote: > On Mon, Nov 28, 2016 at 12:28:35PM -0700, Jordan Crouse wrote: > > Add an interface to trigger the remote processor to reinitialize the GPU > > zap shader on power-up. > > > > Signed-off-by: Jordan Cro

Re: [Freedreno] [PATCH 10/12] firmware: qcom_scm: Add qcom_scm_gpu_zap_resume()

On Fri, Jan 13, 2017 at 11:12:41AM -0600, Andy Gross wrote: > On Mon, Nov 28, 2016 at 12:28:35PM -0700, Jordan Crouse wrote: > > Add an interface to trigger the remote processor to reinitialize the GPU > > zap shader on power-up. > > > > Signed-off-by: Jordan Cro

[PATCH 0/3] drm/msm cleanups

Here are a few foundational patches to clean up some of the MSM code and get ready for new and awesome things down the line. Jordan Crouse (3): drm/msm: gpu: Cut down the list of "generic" registers to the ones we use drm/msm: gpu: Return error on hw_init failure dr

[PATCH 1/3] drm/msm: gpu: Cut down the list of "generic" registers to the ones we use

There are very few register accesses in the common code. Cut down the list of common registers to just those that are used. This saves const space and saves us the effort of maintaining registers for A3XX and A4XX that don't exist or are unused. Signed-off-by: Jordan Crouse --- drivers/gpu/drm

[PATCH 2/3] drm/msm: gpu: Return error on hw_init failure

When the GPU hardware init function fails (like say, ME_INIT timed out) return error instead of blindly continuing on. This gives us a small chance of saving the system before it goes boom. Signed-off-by: Jordan Crouse --- drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 21

[PATCH 3/3] drm/msm: gpu Add new gpu register read/write functions

and write are needed. gpu_rmw() does a read/modify/write on a 32 bit register given a mask and bits to OR in. Signed-off-by: Jordan Crouse --- drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 12 ++- drivers/gpu/drm/msm/msm_gpu.h | 39 +++ 2 files changed, 41

[PATCH 00/12] Adreno A5XX support

All, here is initial kernel support for the Adreno A5XX family of GPUs found on the QTI Snapdragon 820 and 821 among others. This stack turns on the A5XX hardware and initializes the GPMU (Graphics Power Management Unit) which is a microcontroller to assist with more independent power management.

[PATCH 02/12] drm/msm: gpu: Return error on hw_init failure

When the GPU hardware init function fails (like say, ME_INIT timed out) return error instead of blindly continuing on. This gives us a small chance of saving the system before it goes boom. Signed-off-by: Jordan Crouse --- drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 21

[PATCH 09/12] drm/msm: gpu: Add support for the GPMU

initalized through a shared register interface and then we mostly get out of its way and let it do its thing. Signed-off-by: Jordan Crouse --- drivers/gpu/drm/msm/Makefile | 1 + drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 64 +- drivers/gpu/drm/msm/adreno/a5xx_gpu.h

[PATCH 06/12] drm/msm: Remove 'src_clk' from adreno configuration

request 'core_clk' and get the right thing back so zap the anachronism and directly use grp_clk[0] to control the clock rate. Signed-off-by: Jordan Crouse --- drivers/gpu/drm/msm/msm_gpu.c | 36 +--- drivers/gpu/drm/msm/msm_gpu.h | 2 +- 2 files changed, 14 insertions

[PATCH 05/12] drm/msm: gpu: Add OUT_TYPE4 and OUT_TYPE7

Add helper functions for TYPE4 and TYPE7 ME opcodes that replace TYPE0 and TYPE3 starting with the A5XX targets. Signed-off-by: Jordan Crouse --- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 30 ++ 1 file changed, 30 insertions(+) diff --git a/drivers/gpu/drm/msm

[PATCH 07/12] drm/msm: Disable interrupts during init

Disable the interrupt during the init sequence to avoid having interrupts fired for errors and other things that we are not ready to handle while initializing. Signed-off-by: Jordan Crouse --- drivers/gpu/drm/msm/adreno/adreno_device.c | 4 drivers/gpu/drm/msm/adreno/adreno_gpu.c| 3

[PATCH 03/12] drm/msm: gpu Add new gpu register read/write functions

and write are needed. gpu_rmw() does a read/modify/write on a 32 bit register given a mask and bits to OR in. Signed-off-by: Jordan Crouse --- drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 12 ++- drivers/gpu/drm/msm/msm_gpu.h | 39 +++ 2 files changed, 41

[PATCH 12/12] drm/msm: gpu: Use the zap shader on 5XX if we can

stem crash but thats a problem that shows up immediately. Signed-off-by: Jordan Crouse --- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 72 ++- 1 file changed, 70 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/

[PATCH 01/12] drm/msm: gpu: Cut down the list of "generic" registers to the ones we use

There are very few register accesses in the common code. Cut down the list of common registers to just those that are used. This saves const space and saves us the effort of maintaining registers for A3XX and A4XX that don't exist or are unused. Signed-off-by: Jordan Crouse --- drivers/gpu/drm

[PATCH 08/12] drm/msm: gpu: Add A5XX target support

Add support for the A5XX family of Adreno GPUs. Signed-off-by: Jordan Crouse --- drivers/gpu/drm/msm/Makefile | 1 + drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 823 + drivers/gpu/drm/msm/adreno/a5xx_gpu.h | 37 ++ drivers/gpu/drm/msm/adreno

[PATCH 10/12] firmware: qcom_scm: Add qcom_scm_gpu_zap_resume()

Add an interface to trigger the remote processor to reinitialize the GPU zap shader on power-up. Signed-off-by: Jordan Crouse --- drivers/firmware/qcom_scm-32.c | 5 + drivers/firmware/qcom_scm-64.c | 15 +++ drivers/firmware/qcom_scm.c| 6 ++ drivers/firmware

[PATCH 11/12] drm/msm: Add a quick and dirty PIL loader

loader that will read a MDT file and get it loaded and authenticated through SCM. Signed-off-by: Jordan Crouse --- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 166 ++ 1 file changed, 166 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm

[PATCH 04/12] drm/msm: Add adreno_gpu_write64()

oth 32 bit targets (a3xx and a4xx). When a5xx comes it will define valid target registers for the 'hi' option and everything else will just work. Signed-off-by: Jordan Crouse --- drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 2 ++ drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 2 ++ drivers/gpu/drm/

[Freedreno] [PATCH 12/12] drm/msm: gpu: Use the zap shader on 5XX if we can

On Mon, Dec 05, 2016 at 11:57:12AM -0800, Bjorn Andersson wrote: > On Mon 28 Nov 11:28 PST 2016, Jordan Crouse wrote: > > > The A5XX GPU powers on in "secure" mode. In secure mode the GPU can > > only render to buffers that are marked as secure and inaccessible > &

[Freedreno] [PATCH 11/12] drm/msm: Add a quick and dirty PIL loader

On Mon, Dec 05, 2016 at 11:57:43AM -0800, Bjorn Andersson wrote: > > + if (of_property_read_u32(pdev->dev.of_node, "qcom,pas-id", _id)) { > > This is constant, so define it in the driver. Little bit concerned it might not always be constant but I suppose we can cross that bridge when we get to

[PATCH 0/3] drm/msm: 4.10 fixes

Here is a short trio of drm/msm fixes suitable for 4.10. The first fixes a hang that occurs when the ring is completely filled, the other two can be triggered through the API and cause mild distress. Jordan Crouse (3): drm/msm: Ensure that the hardware write pointer is valid drm/msm: Put

[PATCH 1/3] drm/msm: Ensure that the hardware write pointer is valid

rb->size / 4 and thus result in an out of bounds address to CP_RB_WPTR. The easiest way to fix this is to mask WPTR when writing it to the hardware; it makes the hardware happy and the rest of the ringbuffer math appears to work and there isn't any point in upsetting anything. Signed-off-by

[PATCH 3/3] drm/msm: Verify that MSM_SUBMIT_BO_FLAGS are set

For every submission buffer object one of MSM_SUBMIT_BO_WRITE and MSM_SUBMIT_BO_READ must be set (and nothing else). If we allowed zero then the buffer object would never get queued to be unreferenced. Signed-off-by: Jordan Crouse --- drivers/gpu/drm/msm/msm_gem_submit.c | 3 ++- 1 file changed

[PATCH 2/3] drm/msm: Put back the vaddr in submit_reloc()

The error cases in submit_reloc() need to put back the virtual address of the bo before failling. Add a single failure path for the function. Signed-off-by: Jordan Crouse --- drivers/gpu/drm/msm/msm_gem_submit.c | 15 +-- 1 file changed, 9 insertions(+), 6 deletions(-) diff --git

[PATCH 4/7] drm/msm: crank down gpu when inactive

On 03/10/2014 10:47 AM, Rob Clark wrote: > Shut down the clks when the gpu has nothing to do. A short inactivity > timer is used to provide a low pass filter for power transitions. Good luck. Power management will take years off your life. > Signed-off-by: Rob Clark Acked-by: Jord

[PATCH 2/7] drm/msm: add hang_debug module param

On 03/10/2014 10:47 AM, Rob Clark wrote: > msm.hang_debug=y will dump out current register values if the gpu locks > up, for easier debugging. > > Signed-off-by: Rob Clark > --- > drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 34 > - >

[PATCH 5/7] drm/msm: add chip-id param

ed to try to be clever with unique GPU IDs and such with it but we discovered over time that there is just too much drama. > Signed-off-by: Rob Clark Acked-by: Jordan Crouse > --- > drivers/gpu/drm/msm/adreno/adreno_gpu.c | 6 ++ > include/uapi/drm/msm_drm.h | 1 + &

[PATCH 3/7] drm/msm: spin helper

On 03/10/2014 10:47 AM, Rob Clark wrote: > Helper macro to simplify places where we need to poll with timeout > waiting for gpu. > > Signed-off-by: Rob Clark Acked-by: Jordan Crouse > --- > drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 14 +++ > drivers/gpu/drm/ms

[PATCH 7/7] drm/msm: validate flags, etc

lly > only just barely usable for basic stuff (serial console) with an > upstream kernel, I think we should fix this now and revert specific > parts of this patch later in the unlikely event that a regression is > reported. > > [1] https://lwn.net/Articles/588444/ > > Sign

[RFC] drm/msm: DT support for 8960/8064

On 07/01/2014 12:57 PM, Rob Clark wrote: > diff --git a/Documentation/devicetree/bindings/drm/msm/gpu.txt > b/Documentation/devicetree/bindings/drm/msm/gpu.txt > new file mode 100644 > index 000..6e33efe > --- /dev/null > +++ b/Documentation/devicetree/bindings/drm/msm/gpu.txt > @@ -0,0 +1,51

[RFC] drm/msm: DT support for 8960/8064

On 07/02/2014 08:42 AM, Rob Clark wrote: > On Wed, Jul 2, 2014 at 10:26 AM, Jordan Crouse > wrote: >> >> On 07/01/2014 12:57 PM, Rob Clark wrote: >>> >>> diff --git a/Documentation/devicetree/bindings/drm/msm/gpu.txt >>> b/Documentation/devicetr

[RFC] drm/msm: DT support for 8960/8064

On 07/02/2014 03:01 PM, Rob Clark wrote: > As far as I can tell from diving downstream android kgsl code, seems > like some a2xx you might be able to read the value from hw. Beyond > that I'm not entirely sure. (Remember, no docs.) Ohhh! I get to tell a story! The on chip registers have a long

GPU lockup dumping

On 05/23/2012 08:51 AM, Jerome Glisse wrote: > On Wed, May 23, 2012 at 5:27 AM, Dave Airlie wrote: >> On Thu, May 17, 2012 at 7:28 PM, wrote: >>> So here is improved patchset, where i splited ground work necessary >>> for the dumping into their own patch. The debugfs improvement could >>>

[RFCv1 2/2] drm/msm: basic KMS driver for snapdragon

On 07/05/2013 01:53 PM, Rob Clark wrote: > The snapdragon chips have multiple different display controllers, > depending on which chip variant/version. (As far as I can tell, current > devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And > then external to the display

[PATCH 1/2] drm: rework PCI/platform driver interface.

On 02/06/2011 08:09 PM, Dave Airlie wrote: > This abstracts the pci/platform interface out a step further, > we can go further but this is far enough for now to allow USB > to be plugged in. > > The drivers now just call the init code directly for their > device type. > > Signed-off-by: Dave

[PATCH v3] DRM platform device support

DRM platform device support freshly rebased for 2.6.35. Nothing changed in the code over the set I sent on 5/27. Jordan

[PATCH 1/4] drm: Remove drm_resource wrappers

Remove the drm_resource wrappers and directly use the actual PCI and/or platform functions in their place. Signed-off-by: Jordan Crouse --- drivers/gpu/drm/drm_bufs.c| 13 - drivers/gpu/drm/i915/i915_dma.c |6 +++--- drivers/gpu/drm/mga/mga_dma.c

[PATCH 2/4] drm: Add support for platform devices to register as DRM devices

Allow platform devices without PCI resources to be DRM devices. Signed-off-by: Jordan Crouse --- drivers/gpu/drm/Kconfig |4 +- drivers/gpu/drm/Makefile |2 +- drivers/gpu/drm/drm_drv.c | 37 +--- drivers/gpu/drm/drm_edid.c|4

[PATCH 3/4] drm: Add __arm defines to DRM

Add __arm defines to specify behavior specific for an ARM processor. Signed-off-by: Jordan Crouse --- drivers/gpu/drm/drm_bufs.c |2 +- drivers/gpu/drm/drm_vm.c | 14 +- 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/drm_bufs.c b/drivers/gpu

[PATCH 4/4] drm: Make sure the DRM offset matches the CPU

The pgoff option in mmap() is defined as an unsigned long so the offset generated by DRM needs to fit into BITS_PER_LONG for the CPU in question. Signed-off-by: Jordan Crouse --- drivers/gpu/drm/drm_gem.c | 10 ++ 1 files changed, 10 insertions(+), 0 deletions(-) diff --git a/drivers

[RFC] Qualcomm 2D/3D graphics driver

e bit less cryptic. -- Jordan Crouse Qualcomm Innovation Center Qualcomm Innovation Center is a member of Code Aurora Forum

[PATCH 1/6] drm/msm: Add a quick and dirty PIL loader

loader that will read a MDT file and get it loaded and authenticated through SCM. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 166 ++ 1 file changed, 166 insertions(+) diff --git a/drivers/gpu/drm/msm/

[PATCH 3/6] drm/msm: Improve the zap shader

Simply the code use snprintf correctly and make sure that we memset the rest of the segment if the memory size in the ELF file is larger than the file size. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 70 +---

[PATCH 4/6] drm/msm: Create a child device for the zap shader

Currently we abuse the platform device engine to create a platform device for the zap shader subnode so that we can isolate the reserved memory away from the parent GPU device. It is much safer to create and register a simple child device and use that instead. Signed-off-by: Jordan Crouse <j

[PATCH 5/6] drm/msm: Move zap shader firmware name to the device table

The zap shader firmware name is not platform specific. Move it to the device table instead. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 24 drivers/gpu/drm/msm/adreno/adreno_device.c | 1 + drivers/gpu/d

[PATCH 2/6] drm/msm: gpu: Use the zap shader on 5XX if we can

stem crash but thats a problem that shows up immediately. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 72 ++- 1 file changed, 70 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.

[PATCH 0/6] drm: msm: A5XX zap shader

the changes that Bjorn requested and a bit more clean up to rely on the device tree less as is our current plan of action. I am not at all oppposed to squashing these into one big change or two moderate changes if it makes life easier. Jordan Crouse (6): drm/msm: Add a quick and dirty PIL loader drm

[PATCH 6/6] drm/msm: Document the zap-shader subnode for the GPU

The 'zap-shader' subnode is used to define a phandle for the PIL memory region that is required to load GPU secure firwmare images (known as the "zap shader"). Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- Documentation/devicetree/bindings/display/msm/gpu.txt | 13

Re: [Freedreno] [PATCH 3/3] drm/msm: Fix compilation error when CONFIG_DEBUG_FS undefined

warning: (near initialization > for ‘funcs.base’) [enabled by default] > make[5]: *** [drivers/gpu/drm/msm/adreno/a5xx_gpu.o] Error 1 > make[4]: *** [drivers/gpu/drm/msm] Error 2 > make[4]: *** Waiting for unfinished jobs > > Fixes: b5f103ab98c7 ("drm/msm: gpu

[PATCH 1/4] drm/msm: Fix wrong pointer check in a5xx_destroy

Instead of checking for a5xx_gpu->gpmu_iova during destroy we accidently check a5xx_gpu->gpmu_bo. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/dr

[PATCH 0/4] drm/msm: Fixes for 4.11

Hey Rob, here are a handful of things that might be fixable for 4.11 but if not consider them for -next. Jordan Jordan Crouse (4): drm/msm: Fix wrong pointer check in a5xx_destroy drm/msm: Don't increase priv->num_aspaces until we know that it fits drm/msm: Pass interrupt sta

[PATCH 4/4] drm/msm: Support 64 bit iova in RD_CMDSTREAM_ADDR

Output the upper 32 bits of a 64 bit iova in the RD_CMDSTREAM_ADDR section while maintaining backwards compatibility for tools that only understand 32 bit iovas. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- drivers/gpu/drm/msm/msm_rd.c | 4 ++-- 1 file changed, 2 insertions

[PATCH 2/4] drm/msm: Don't increase priv->num_aspaces until we know that it fits

priv->num_aspaces is increased and then checked to see if it still fits in the priv->aspace array. If it doesn't, we warn and exit but priv->num_aspaces remains incremented. Don't incremement the count until we know that it fits in the array. Signed-off-by: Jordan Crouse <jcro...@co

[PATCH 02/11] drm/msm: Improve the zap shader

Simply the code, use snprintf correct and make sure that we memset the rest of the segment if the memory size in the ELF file is larger than the file size. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 4 +- drivers/gpu/drm/msm/

[PATCH 04/11] drm/msm: Add hint to DRM_IOCTL_MSM_GEM_INFO to return an object IOVA

Modify the 'pad' member of struct drm_msm_gem_info to 'hint'. If the user sets 'hint' to non-zero it means that they want a IOVA for the GEM object instead of a mmap() offset. Return the iova in the 'offset' member. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- drivers/gpu/d

[v2] [PATCH 00/11] drm/msm: A5XX preemption

Here is v2 of the preemption series - Changes: * Refactored API in DRM_IOCTL_MSM_GEM_INFO (Thanks Emil Velikov) * Removed preemption worker and fixed atomics (Thanks Stephen Boyd) * Various fixes and improvements based on testing Thanks! Jordan Jordan Crouse (11): drm/msm: Make sure

[PATCH 08/11] drm/msm: Support multiple ringbuffers

specific so this code just allows for the possibility but still only defines one ringbuffer for each target family. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 9 +- drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 9 +- drivers/gpu/drm/msm/

[PATCH 01/11] drm/msm: Make sure to detach the MMU during GPU cleanup

We should be detaching the MMU before destroying the address space. To do this cleanly, the detach has to happen in adreno_gpu_cleanup() because it needs access to structs in adreno_gpu.c. Plus it is better symmetry to have the attach and detach at the same code level. Signed-off-by: Jordan

[PATCH 10/11] drm/msm: Make the value of RB_CNTL (almost) generic

but that only needs to be done once and doesn't affect A5XX so we can or in the value at init time. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 12 +++- drivers/gpu/drm/msm/msm_gpu.h | 5 + 2 files chang

[PATCH 11/11] drm/msm: Implement preemption for A5XX targets

Implement preemption for A5XX targets - this allows multiple ringbuffers for different priorities with automatic preemption of a lower priority ringbuffer if a higher one is ready. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- drivers/gpu/drm/msm/Makefile

[PATCH 09/11] drm/msm: Shadow current pointer in the ring until command is complete

load for non-preemption targets should be minimal. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 9 +++-- drivers/gpu/drm/msm/msm_ringbuffer.c| 1 + drivers/gpu/drm/msm/msm_ringbuffer.h| 12 3 files chang

[PATCH 03/11] drm/msm: Remove idle function hook

There isn't any generic code that uses ->idle so remove it. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 4 ++-- drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 4 ++-- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 9 - drivers/gp

[PATCH 06/11] drm/msm: Add a struct to pass configuration to msm_gpu_init()

The amount of information that we need to pass into msm_gpu_init() is steadily increasing, so add a new struct to stabilize the function call and make it easier to add new configuration down the line. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- drivers/gpu/drm/msm/

[PATCH 07/11] drm/msm: Remove memptrs->wptr

memptrs->wptr seems to be unused. Remove it to avoid confusing the upcoming preemption code. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 3 --- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 - 2 files changed, 4 deletions(-) d

[PATCH 5/6] drm/msm: gpu: Use OPP tables if we can

If a OPP table is defined for the GPU device in the device tree use that in lieu of the downstream style GPU frequency table. If we do use the downstream table convert it to a OPP table so that we can take advantage of the OPP lookup facilities later. Signed-off-by: Jordan Crouse <j

[PATCH 6/6] msm/drm: gpu: Dynamically locate the clocks from the device tree

Instead of using a fixed list of clock names use the clock-names list in the device tree to discover and get the list of clocks that we need. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- drivers/gpu/drm/msm/msm_gpu.c | 76 ++- drivers/g

[PATCH 2/6] drm/msm: Reference count address spaces

their addresses. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 2 +- drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c | 2 +- drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c | 2 +- drivers/gpu/drm/msm/msm_drv.h | 3 ++- drivers/gpu/drm/msm/msm

[PATCH 4/6] drm/msm: Hard code the GPU "slow frequency"

the "slow" clock speed in the code as 27MHz and save ourselves a bit of infrastructure. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- drivers/gpu/drm/msm/adreno/adreno_device.c | 5 + drivers/gpu/drm/msm/adreno/adreno_gpu.c| 5 ++--- drivers/gpu/drm/msm/

[PATCH 3/6] drm/msm: Add MSM_PARAM_GMEM_BASE

User space needs to know where the GMEM whole starts so that they can set up the addressing correctly. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 3 +++ include/uapi/drm/msm_drm.h | 1 + 2 files changed, 4 insertions(+)

[PATCH 0/6] drm/msm: New features for 4.12

shenanigans. Thanks! Jordan Jordan Crouse (6): drm/msm: Don't allow zero sized buffer objects drm/msm: Reference count address spaces drm/msm: Add MSM_PARAM_GMEM_BASE drm/msm: Hard code the GPU "slow frequency" drm/msm: gpu: Use OPP tables if we can msm/drm: gpu: Dynamica

[PATCH 1/6] drm/msm: Don't allow zero sized buffer objects

-by: Jordan Crouse <jcro...@codeaurora.org> --- drivers/gpu/drm/msm/msm_gem.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/msm/msm_gem.c b/drivers/gpu/drm/msm/msm_gem.c index 4c3e6ef..e819b83 100644 --- a/drivers/gpu/drm/msm/msm_gem.c +++ b/drivers/gpu/drm/msm/msm

[PATCH 2/6] drm/msm: Pass the MMU domain index in struct msm_file_private

Pass the index of the MMU domain in struct msm_file_private instead of assuming gpu->id throughout the submit path. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- drivers/gpu/drm/msm/msm_drv.c| 2 ++ drivers/gpu/drm/msm/msm_drv.h| 6 +- drivers/gp

[PATCH 1/6] drm/msm: Enable 64 bit mode by default

addresses so switch over now to prepare for using addresses above 4G for targets that support them. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 14 ++ drivers/gpu/drm/msm/msm_iommu.c | 7 +++ 2 files chang

[PATCH 4/6] drm/msm: Use TTBR1 for kernel side GPU buffer objects

Use a TTBR1 pagetable for the GPU IOMMU domain and map all the GPU kernel side buffer objects into that range. This will make it easier to switch out TTBR0 for per-process pagetables. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- drivers/gpu/drm/msm/adreno/adreno_gpu.

[PATCH 3/6] drm/msm: Make separate iommu function tables for v1 and v2 MMUs

Since we have the infrastructure for IOMMU function tables it makes sense to use it to differentiate between v1 and v2 targets. It adds a bit more infrastructure but it also gives us the freedom to expand on each flavor (especially v2) for things like dynamic domains. Signed-off-by: Jordan Crouse

[PATCH 0/6] drm/msm: Add per-instance pagetables

s, and I'm sure that what we have won't be what is finally decided upon in the arm-smmu driver (in particular there are some nice parts of the arm-v3 SVM solution that we can borrow) but I think it is important to get eyeballs on this for posterity. Thanks! Jordan Jordan Crouse (6): drm/msm: Ena

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