On Gen3 platforms compositing planes are allocated by VSP on behalf of
DRM/KMS.
If VSP support is not compiled in, vsp initialization stub routine is
called. Return an error from that stub to fail explicitly, otherwise
accessing planes leads to invalid memory errors.
Signed-off-by: Jacopo Mondi
HI Laurent,
On 03/03/2017 12:26, Laurent Pinchart wrote:
Hi Jacopo,
Thank you for the patch.
On Friday 03 Mar 2017 09:09:38 Jacopo Mondi wrote:
On Gen3 platforms compositing planes are allocated by VSP on behalf of
DRM/KMS.
If VSP support is not compiled in, vsp1 initialization stub routine
created.
Signed-off-by: Jacopo Mondi <jacopo+rene...@jmondi.org>
---
drivers/gpu/drm/rcar-du/rcar_du_kms.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_kms.c
b/drivers/gpu/drm/rcar-du/rcar_du_kms.c
index b5d3f16..7f56c09 100644
--- a/drivers/gpu/dr
Hi Laurent,
just one minor comment below
On Mon, Apr 23, 2018 at 01:34:27AM +0300, Laurent Pinchart wrote:
> Add a parameter (in the form of a structure to ease future API
> extensions) to the VSP atomic flush handler to pass CRC source
> configuration, and pass the CRC value to the completion
Hi Laurent,
very minor comments below
On Mon, Apr 23, 2018 at 01:34:24AM +0300, Laurent Pinchart wrote:
> The implementation of the set_fmt pad operation is identical in the
> three modules. Move it to a generic helper function.
>
> Signed-off-by: Laurent Pinchart
; Signed-off-by: Laurent Pinchart <laurent.pinchart+rene...@ideasonboard.com>
Reviewed-by: Jacopo Mondi <jac...@jmondi.org>
> ---
> drivers/media/platform/vsp1/vsp1_entity.c | 16 +
> drivers/media/platform/vsp1/vsp1_histo.c | 59
> +++
> 2 fil
HI Laurent,
On Mon, Apr 23, 2018 at 01:34:29AM +0300, Laurent Pinchart wrote:
> The DISCOM is used to compute CRCs on display frames. Integrate it in
> the display pipeline at the output of the blending unit to process
> output frames.
>
> Computing CRCs on input frames is possible by positioning
DOCMPMR_SEL(9));
> +
> + crop = vsp1_entity_get_pad_selection(entity, entity->config,
> + UIF_PAD_SINK, V4L2_SEL_TGT_CROP);
> +
> + /* On M3-W the horizontal coordinates are twice the register value. */
> + if (uif->m3w_quirk
Hi Peter,
On Wed, May 16, 2018 at 12:15:01PM +0200, Peter Rosin wrote:
> The .of_node member is going away.
>
> Signed-off-by: Peter Rosin <p...@axentia.se>
For this specific driver
Acked-by: Jacopo Mondi <jac...@jmondi.org>
Thanks
j
> ---
> drivers/gpu/dr
ompletion callback.
>
> Signed-off-by: Laurent Pinchart <laurent.pinchart+rene...@ideasonboard.com>
> Reviewed-by: Kieran Bingham <kieran.bingham+rene...@ideasonboard.com>
Reviewed-by: Jacopo Mondi <jacopo+rene...@jmondi.org>
Thanks
j
> ---
> Changes since v2:
&g
inchart <laurent.pinchart+rene...@ideasonboard.com>
> Reviewed-by: Kieran Bingham <kieran.bingham+rene...@ideasonboard.com>
Reviewed-by: Jacopo Mondi <jacopo+rene...@jmondi.org>
Thanks
j
> ---
> Changes since v2:
>
> - Reduce indentation in vsp1_du_insert_uif()
> - Use
Hi Laurent,
On Mon, Apr 23, 2018 at 12:27:39PM +0300, Laurent Pinchart wrote:
> Hi Jacopo,
>
> Thank you for the patch.
>
> On Thursday, 19 April 2018 12:31:02 EEST Jacopo Mondi wrote:
> > Add support for storing image format information in DRM bridges with
> >
Hi Peter,
On Sun, Apr 22, 2018 at 10:02:23PM +0200, Peter Rosin wrote:
> On 2018-04-19 11:31, Jacopo Mondi wrote:
> > Add support for storing image format information in DRM bridges with
> > associated helper function.
> >
> > This patch
pinctrl-0 = <_lcd_base _lcd_rgb565>;
> +
> + port@0 {
The node has a unit address specified, you're missing a reg = <0>
property (no big deal, it's an
= of_graph_get_endpoint_by_regs(dev->dev->of_node, 0, endpoint);
> + if (!ep)
> + return -ENODEV;
> +
> ret = drm_of_find_panel_or_bridge(dev->dev->of_node, 0, endpoint,
>
On Fri, Aug 03, 2018 at 10:40:02AM +0200, Peter Rosin wrote:
> On 2018-08-03 10:11, jacopo mondi wrote:
> > Hi Peter!
> >
> > On Fri, Aug 03, 2018 at 09:23:07AM +0200, Peter Rosin wrote:
> >> With bus-type/bus-width properties in the endpoint nodes, the video-
> &
://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas-bsp.git/commit/
?id=32e9be612773ce0ed75295a10764151633938528
that un-conditionally uses the externally generated clock source as output
pixel clock.
Tested on M3-W Salvator-X board and VGA output: fixes 1920x1080 display.
Jacopo Mondi (2):
drm
: 1b30dbde8 "drm: rcar-du: Add support for external pixel clock"
Signed-off-by: Jacopo Mondi
---
drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 96 ++
1 file changed, 73 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
b/drivers/gp
Rename the 'value' variable, only used to for writing to DMSR register to a
more precise 'dmsr' name.
Signed-off-by: Laurent Pinchart
Signed-off-by: Jacopo Mondi
---
drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers
From: Laurent Pinchart
The DU channels that have a display PLL (DPLL) can only use external
clock sources, and don't have an internal clock divider (with the
exception of H3 ES1.x where the post-divider is present and needs to be
used as a workaround for a DPLL silicon issue).
Rework the clock
Hi Ulrich,
I know this series needs to be re-spin when the D3/E3 LVDS PLL
support will be added, but since I need it for testing on D3 the LVDS
interface reset support, I noticed a small issue which I thought it is
worth reporting.
On Tue, May 15, 2018 at 02:20:38PM +0200, Ulrich Hecht wrote:
Hi Laurent,
On Mon, Jul 30, 2018 at 05:12:15PM +0300, Laurent Pinchart wrote:
> Hi Tomi,
>
> (CC'ing Jacopo Mondi for a comment about bus_formats in bridge drivers)
thanks for CC'ing me
>
> Thank you for the patch.
>
> On Monday, 18 June 2018 16:22:37 EEST Tomi Valkeinen
Hi Peter,
On Thu, Aug 16, 2018 at 02:52:41PM +0200, Peter Rosin wrote:
> On 2018-08-03 10:51, jacopo mondi wrote:
> > On Fri, Aug 03, 2018 at 10:40:02AM +0200, Peter Rosin wrote:
> >> On 2018-08-03 10:11, jacopo mondi wrote:
> >>> Hi Peter!
> >>>
>
endpoint->port, endpoint->id,
You are refusing endpoint->port != 0 in the caller, so that could be
0.
Apart from that small nit:
Reviewed-by: Jacopo Mondi
Thanks
j
> , );
> if (ret)
>
From: Laurent Pinchart
The DU channels that have a display PLL (DPLL) can only use external
clock sources, and don't have an internal clock divider (with the
exception of H3 ES1.x where the post-divider is present and needs to be
used as a workaround for a DPLL silicon issue).
Rework the clock
source.
Without this patch:
rcar-du feb0.display: mode clock 14850 extrate 10800 rate
13328 ESCR 0x0012
The requested pixel clock is approximated by the CPG generated clock to 133,3
MHz, which for some monitor is not enough to correctly display any output.
Thanks
j
Jacopo
HI Laurent,
thanks for the patch rework
On Tue, Aug 21, 2018 at 01:12:40AM +0300, Laurent Pinchart wrote:
> Hi Jacopo,
>
> On Tuesday, 21 August 2018 00:49:41 EEST Laurent Pinchart wrote:
> > From: Jacopo Mondi
> >
> > DU channels not equipped with a DPLL us
From: Jacopo Mondi
DU channels not equipped with a DPLL use an internal (aka SoC provided) or
external clock source combined with an internal divider to generate the
desired output dot clock frequency.
The current clock selection procedure does not fully exploit the ability
of external clock
Hi Laurent,
I run some tests, and here below there's a summary of what I see
On Tue, Aug 21, 2018 at 01:12:40AM +0300, Laurent Pinchart wrote:
> Hi Jacopo,
>
> On Tuesday, 21 August 2018 00:49:41 EEST Laurent Pinchart wrote:
> > From: Jacopo Mondi
> >
> > DU channe
processors
and the output pin controller. The updated version of the SoC manual
prescribes thus to hardcode DPRCR2 bits that controls output pin routing for
those channels.
Signed-off-by: Jacopo Mondi
---
drivers/gpu/drm/rcar-du/rcar_du_group.c | 19 ---
1 file changed, 16 insertions
exception.
Signed-off-by: Jacopo Mondi
---
drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 13 +++--
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
index 1541152..7b1c05b 100644
--- a/drivers/gpu/drm
According to revision 1.00 of R-Car Gen3 SoC manual, writing to OTAR
register is valid only if the channel is equipped with a digital output
pad (DPAD).
Signed-off-by: Jacopo Mondi
---
drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git
invalid writing PnMR[13:12] on:
R-Car V3M/V3H: only group 0 is present, but with a single channel
Signed-off-by: Jacopo Mondi
---
drivers/gpu/drm/rcar-du/rcar_du_plane.c | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_plane.c
b
-N with VGA and HDMI output.
No visible regression, but if you have ideas on how to better verify this
please let me know.
Thanks
j
Jacopo Mondi (4):
drm: rcar-du: Do not write ESCR for DPLL channels
drm: rcar-du: Write OTAR for DPAD channels only
drm: rcar-du: Fix handling of DORCR
based on your drm/du/next branch, with the following patch applied on
top:
'01449a9779b8 (" drm: rcar-du: Rework clock configuration based on hardware
limits")'
Tested on Salvator-X M3-W with kms-modes-tests.py: no functional changes
Thanks
j
Jacopo Mondi (3):
drm: rcar-du: Rename an
with 'rcar_du_crtc_write()'.
Cosmetic patch, no functional changes intended.
Signed-off-by: Jacopo Mondi
---
drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 2 +-
drivers/gpu/drm/rcar-du/rcar_du_regs.h | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
b
Document and re-name the 'dpll_ch' field to a more precise 'dpll_mask' for
consistency with the 'channels_mask' field defined in 'struct
rcar_du_device_info'.
Signed-off-by: Jacopo Mondi
---
drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 2 +-
drivers/gpu/drm/rcar-du/rcar_du_drv.c | 6
with 'rcar_du_crtc_write()'.
Cosmetic patch, no functional changes intended.
Signed-off-by: Jacopo Mondi
---
drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 3 +--
drivers/gpu/drm/rcar-du/rcar_du_regs.h | 4 ++--
2 files changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
b
And for the records, I forgot to add
On Tue, Aug 21, 2018 at 12:35:48PM +0200, jacopo mondi wrote:
> Hi Laurent,
>I run some tests, and here below there's a summary of what I see
>
> On Tue, Aug 21, 2018 at 01:12:40AM +0300, Laurent Pinchart wrote:
> > Hi Jacopo,
> >
&
successfully tested the series with the HDMI output of the Ebisu board.
> Ulrich, Jacopo, could you test it on D3 if you have time ? You only need to
> run kmstest or modetest to display an image on the HDMI output.
HDMI output works fine with several modes I have tested:
1920x1080, 1280x720, 1024x768
Hi Laurent,
On Tue, Sep 04, 2018 at 03:10:17PM +0300, Laurent Pinchart wrote:
> The rcar_du_crtc_get() function is always immediately followed by a call
> to rcar_du_crtc_setup(). Call the later from the former to simplify the
> code, and add a comment to explain how the get and put calls are
>
> >
> > Signed-off-by: Takeshi Kihara
> > Signed-off-by: Jacopo Mondi
>
> My
>
> Reviewed-by: Geert Uytterhoeven
> Tested-by: Geert Uytterhoeven
>
> are still valid.
I was about to send a v2 with these and the slight change Geert
suggested on the c
Hi Laurent,
sorry, I might be confused but,
On Tue, Sep 04, 2018 at 03:10:15PM +0300, Laurent Pinchart wrote:
> The THC63LVD1024 is restricted to a pixel clock frequency in the range
> of 8 to 135 MHz. Implement the bridge .mode_valid() operation
> accordingly.
>
> Signed-off-by: Laurent
Hi Laurent,
On Tue, Sep 04, 2018 at 03:10:16PM +0300, Laurent Pinchart wrote:
> The LVDS encoders in the D3 and E3 SoCs differ significantly from those
> in the other R-Car Gen3 family members:
>
> - The LVDS PLL architecture is more complex and requires computing PLL
> parameters manually.
> -
Hi Andrzej,
thanks for the detailed reply, much appreciated :)
On Mon, Mar 12, 2018 at 02:47:20PM +0100, Andrzej Hajda wrote:
> On 12.03.2018 13:30, jacopo mondi wrote:
> > Hi Andrzej,
> >
> > On Mon, Mar 12, 2018 at 10:07:27AM +0100, Andrzej Hajda wrote:
> >
Hi Andrzej,
On Mon, Mar 12, 2018 at 10:07:27AM +0100, Andrzej Hajda wrote:
> On 09.03.2018 14:51, Jacopo Mondi wrote:
> > Hello,
> >after some discussion on the proposed bindings for generic lvds decoder
> > and
> > Thine THC63LVD1024, I decided to drop the THC63
Document Thine THC63LVD1024 LVDS decoder device tree bindings.
Signed-off-by: Jacopo Mondi <jacopo+rene...@jmondi.org>
---
.../bindings/display/bridge/thine,thc63lvd1024.txt | 63 ++
1 file changed, 63 insertions(+)
create mode 100644
Documentation/devicetree/bi
, describe it in DT
as well.
Signed-off-by: Jacopo Mondi <jacopo+rene...@jmondi.org>
---
arch/arm64/boot/dts/renesas/r8a77970-eagle.dts | 33 +++---
1 file changed, 30 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts
b/arch/arm64/bo
> v3:
- Drop support for "lvds-decoder" and make the driver THC63LVD1024 specific
-- Rework bindings to describe multiple input/output ports
-- Rename driver and remove "lvds-decoder" references
-- Rework Eagle DTS to use new bindings
v1 -> v2:
- Drop support for THC63LVD1024
Ja
Add DRM bridge driver for Thine THC63LVD1024 LVDS to digital parallel
output decoder.
Signed-off-by: Jacopo Mondi <jacopo+rene...@jmondi.org>
---
drivers/gpu/drm/bridge/Kconfig| 7 +
drivers/gpu/drm/bridge/Makefile | 1 +
drivers/gpu/drm/bridge/thc63lvd1024.c
, describe it in DT
as well.
Signed-off-by: Jacopo Mondi <jacopo+rene...@jmondi.org>
Reviewed-by: Andrzej Hajda <a.ha...@samsung.com>
---
arch/arm64/boot/dts/renesas/r8a77970-eagle.dts | 33 +++---
1 file changed, 30 insertions(+), 3 deletions(-)
diff --git a/arch/ar
Add DRM bridge driver for Thine THC63LVD1024 LVDS to digital parallel
output converter.
Signed-off-by: Jacopo Mondi <jacopo+rene...@jmondi.org>
---
drivers/gpu/drm/bridge/Kconfig| 6 +
drivers/gpu/drm/bridge/Makefile | 1 +
drivers/gpu/drm/bridge/thc63lvd1024.c
ot;lvds-decoder" references
-- Rework Eagle DTS to use new bindings
v1 -> v2:
- Drop support for THC63LVD1024
Jacopo Mondi (3):
dt-bindings: display: bridge: Document THC63LVD1024 LVDS decoder
drm: bridge: Add thc63lvd1024 LVDS decoder driver
arm64: dts: renesas: Add LVDS
Document Thine THC63LVD1024 LVDS decoder device tree bindings.
Signed-off-by: Jacopo Mondi <jacopo+rene...@jmondi.org>
---
.../bindings/display/bridge/thine,thc63lvd1024.txt | 63 ++
1 file changed, 63 insertions(+)
create mode 100644
Documentation/devicetree/bi
Document Thine THC63LVD1024 LVDS decoder device tree bindings.
Signed-off-by: Jacopo Mondi <jacopo+rene...@jmondi.org>
Reviewed-by: Andrzej Hajda <a.ha...@samsung.com>
---
.../bindings/display/bridge/thine,thc63lvd1024.txt | 66 ++
1 file changed, 66 insertion
Add DRM bridge driver for Thine THC63LVD1024 LVDS to digital parallel
output converter.
Signed-off-by: Jacopo Mondi <jacopo+rene...@jmondi.org>
Reviewed-by: Andrzej Hajda <a.ha...@samsung.com>
---
drivers/gpu/drm/bridge/Kconfig| 6 +
drivers/gpu/drm/bridge/Makefile
uot; and make the driver THC63LVD1024 specific
-- Rework bindings to describe multiple input/output ports
-- Rename driver and remove "lvds-decoder" references
-- Rework Eagle DTS to use new bindings
v1 -> v2:
- Drop support for THC63LVD1024
Jacopo Mondi (3):
dt-bindings: display: br
, describe it in DT
as well.
Signed-off-by: Jacopo Mondi <jacopo+rene...@jmondi.org>
---
arch/arm64/boot/dts/renesas/r8a77970-eagle.dts | 33 +++---
1 file changed, 30 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts
b/arch/arm64/bo
Hi Andrzej,
sorry for the mess :(
On Wed, Mar 14, 2018 at 09:15:42AM +0100, Andrzej Hajda wrote:
> On 13.03.2018 15:30, Jacopo Mondi wrote:
> > Document Thine THC63LVD1024 LVDS decoder device tree bindings.
> >
> > Signed-off-by: Jacopo Mondi <j
Hi Andrzej,
thanks for review
On Wed, Mar 14, 2018 at 09:42:36AM +0100, Andrzej Hajda wrote:
> On 13.03.2018 15:30, Jacopo Mondi wrote:
> > Add DRM bridge driver for Thine THC63LVD1024 LVDS to digital parallel
> > output decoder.
>
> IMO converter suits here better, but
u plan to update the Gen2 boards DTS files which
> also have a decoder which are not yet described in DT?
Actually I'm not aware of Gen2 boards with this chip and similar
display pipelines. Can you point me to which one needs to have its
DTS brushed?
Thanks
j
>
> On 2018-03-15 17:11
Hi Andrzej,
thanks for your patience in reviewing this series
On Thu, Mar 15, 2018 at 02:37:00PM +0100, Andrzej Hajda wrote:
> On 15.03.2018 11:56, Jacopo Mondi wrote:
> > Add DRM bridge driver for Thine THC63LVD1024 LVDS to digital parallel
> > output converter.
> >
>
is
available, describe it in DT as well.
Signed-off-by: Jacopo Mondi <jacopo+rene...@jmondi.org>
---
arch/arm64/boot/dts/renesas/r8a77970-eagle.dts | 31 --
1 file changed, 29 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r8a77970-eagle.
input endpoints, except for HDMI audio endpoint, which I haven't found
in use in any DTS. I guess the problem has been already debated and maybe solved
in the past, so feel free to point me to other sources.
Jacopo Mondi (3):
dt-bindings: display: bridge: Document LVDS to parallel decoder
drm
Add transparent LVDS decoder driver.
A transparent LVDS decoder is a DRM bridge device that does not require
any configuration and converts LVDS input to digital CMOS/TTL parallel
data output.
Signed-off-by: Jacopo Mondi <jacopo+rene...@jmondi.org>
---
drivers/gpu/drm/bridge/K
Hi Sergei,
On Fri, Mar 09, 2018 at 08:30:36PM +0300, Sergei Shtylyov wrote:
> On 03/09/2018 04:51 PM, Jacopo Mondi wrote:
>
> > The R-Car V3M Eagle board includes a transparent LVDS decoder, connected
> > to the on-chip LVDS encoder output on one side and to HDMI encoder
> &g
Document transparent LVDS to CMOS/TTL decoder that do not require any
configuration.
Signed-off-by: Jacopo Mondi <jacopo+rene...@jmondi.org>
---
.../bindings/display/bridge/lvds-decoder.txt | 42 ++
1 file changed, 42 insertions(+)
create mode 100644
Documen
Hello Archit,
On Sat, Mar 10, 2018 at 11:23:19AM +0530, Archit Taneja wrote:
> Hi,
>
> On Friday 09 March 2018 07:21 PM, Jacopo Mondi wrote:
> >Hello,
> >after some discussion on the proposed bindings for generic lvds decoder
> > and
> >Thine THC63LVD
HI Andrezej,
On Thu, Mar 15, 2018 at 10:44:42AM +0100, Andrzej Hajda wrote:
> On 14.03.2018 11:09, jacopo mondi wrote:
> > Hi Andrzej,
> > thanks for review
> >
> > On Wed, Mar 14, 2018 at 09:42:36AM +0100, Andrzej Hajda wrote:
> >> On 13.03.2018 15:3
is
available, describe it in DT as well.
Signed-off-by: Jacopo Mondi <jacopo+rene...@jmondi.org>
---
arch/arm64/boot/dts/renesas/r8a77970-eagle.dts | 31 --
1 file changed, 29 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r8a77970-eagle.
probes and testing all available output
modes (of which only a few are actually working, I suspect due to faulty mode
propagation through DRM bridges).
Thanks
j
Jacopo Mondi (3):
dt-bindings: display: bridge: Document THC63LVD1024 LVDS decoder
drm: bridge: Add LVDS decoder driver
arm64: dts
Document Thine THC63LVD1024 LVDS decoder.
Signed-off-by: Jacopo Mondi <jacopo+rene...@jmondi.org>
---
.../bindings/display/bridge/thine,thc63lvd1024.txt | 59 ++
1 file changed, 59 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/bridge
enable GPIOs.
Signed-off-by: Jacopo Mondi <jacopo+rene...@jmondi.org>
---
drivers/gpu/drm/bridge/Kconfig| 8 ++
drivers/gpu/drm/bridge/Makefile | 1 +
drivers/gpu/drm/bridge/lvds-decoder.c | 239 ++
3 files changed, 248 insertions(+)
creat
Hi Geert,
On Fri, Mar 09, 2018 at 10:22:39AM +0100, Geert Uytterhoeven wrote:
> Hi Jacopo,
>
> On Fri, Mar 9, 2018 at 10:04 AM, jacopo mondi <jac...@jmondi.org> wrote:
> > On Fri, Mar 09, 2018 at 09:10:55AM +0100, Geert Uytterhoeven wrote:
> >> On Thu, Mar 8, 2018 at
Hi Andrzej,
On Fri, Mar 09, 2018 at 09:01:24AM +0100, Andrzej Hajda wrote:
> On 08.03.2018 16:24, Jacopo Mondi wrote:
> > Document Thine THC63LVD1024 LVDS decoder.
> >
> > Signed-off-by: Jacopo Mondi <jacopo+rene...@jmondi.org>
> > ---
> > .../bindings/dis
Hi Geert,
thanks for review
On Fri, Mar 09, 2018 at 09:10:55AM +0100, Geert Uytterhoeven wrote:
> Hi Jacopo,
>
> On Thu, Mar 8, 2018 at 4:24 PM, Jacopo Mondi <jacopo+rene...@jmondi.org>
> wrote:
> > Document Thine THC63LVD1024 LVDS decoder.
> >
> > Sign
Hi Sergei,
thanks for review
On Wed, Mar 14, 2018 at 08:09:52PM +0300, Sergei Shtylyov wrote:
> On 03/13/2018 05:30 PM, Jacopo Mondi wrote:
>
> > Add DRM bridge driver for Thine THC63LVD1024 LVDS to digital parallel
> > output decoder.
> >
> > Signed-off
Hi Rob,
sorry for pointing to you directly :)
On Mon, Apr 02, 2018 at 04:36:55PM +0300, Laurent Pinchart wrote:
> Hi Vladimir,
>
> On Tuesday, 27 March 2018 14:03:25 EEST Vladimir Zapolskiy wrote:
> > On 03/27/2018 01:10 PM, jacopo mondi wrote:
> > > On Tue, Mar 27,
Enable DU for Renesas R-Car V3M Eagle board.
Signed-off-by: Jacopo Mondi <jacopo+rene...@jmondi.org>
---
arch/arm64/boot/dts/renesas/r8a77970-eagle.dts | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts
b/arch/arm64/boot/dts/r
Document Thine THC63LVD1024 LVDS decoder device tree bindings.
Signed-off-by: Jacopo Mondi <jacopo+rene...@jmondi.org>
Reviewed-by: Andrzej Hajda <a.ha...@samsung.com>
Reviewed-by: Niklas Söderlund <niklas.soderlund+rene...@ragnatech.se>
Reviewed-by: Laurent Pinch
From: Niklas Söderlund
Add the LVDS device to r8a77970.dtsi in a disabled state. Also connect
the it to the LVDS output of the DU. While at it align the endpoint name
of the du to du_out_lvds0 which is used in other Renesas DTS files to
describe this link.
oder" references
-- Rework Eagle DTS to use new bindings
v1 -> v2:
- Drop support for THC63LVD1024
Jacopo Mondi (2):
dt-bindings: display: bridge: Document THC63LVD1024 LVDS decoder
drm: bridge: Add thc63lvd1024 LVDS decoder driver
.../bindings/display/bridge/thine,thc63lvd1024.txt |
From: Niklas Söderlund <niklas.soderlund+rene...@ragnatech.se>
Enable HDMI output adding the HDMI connector and the ADV7511W, connected
to THC63LVD1024 LVDS decoder output.
Signed-off-by: Niklas Söderlund <niklas.soderlund+rene...@ragnatech.se>
Signed-off-by: Jacopo Mondi
Add DRM bridge driver for Thine THC63LVD1024 LVDS to digital parallel
output converter.
Signed-off-by: Jacopo Mondi <jacopo+rene...@jmondi.org>
Reviewed-by: Andrzej Hajda <a.ha...@samsung.com>
Reviewed-by: Niklas Söderlund <niklas.soderlund+rene...@ragnatech.se>
---
driv
From: Sergei Shtylyov
Describe VSPD0 in the R8A77970 device tree; it will be used by DU in
the next patch...
Based on the original (and large) patch by Daisuke Matsushita
.
Signed-off-by: Vladimir Barinov
From: Sergei Shtylyov
Define the generic R8A77970 part of the DU device node.
Based on the original (and large) patch by Daisuke Matsushita
.
Signed-off-by: Vladimir Barinov
From: Sergei Shtylyov
Describe FCPVD0 in the R8A77970 device tree; it will be used by VSPD0 in
the next patch...
Based on the original (and large) patch by Daisuke Matsushita
.
Signed-off-by: Vladimir Barinov
that a driver is available, describe it in DT
as well.
Signed-off-by: Jacopo Mondi <jacopo+rene...@jmondi.org>
Reviewed-by: Andrzej Hajda <a.ha...@samsung.com>
---
arch/arm64/boot/dts/renesas/r8a77970-eagle.dts | 29 ++
1 file changed, 29 insertions(+)
diff --git
v7-eagle-dts
Thanks
j
Jacopo Mondi (2):
arm64: dts: renesas: eagle: Enable DU
arm64: dts: renesas: eagle: Add LVDS decoder
Niklas Söderlund (2):
arm64: dts: renesas: r8a77970: add the LVDS instance
arm64: dts: renesas: eagle: Add ADV7511W and HDMI output
Sergei Shtylyov (3):
Hi Laurent
On Fri, Apr 06, 2018 at 06:40:14PM +0300, Laurent Pinchart wrote:
> Hi Jacopo,
>
> (CC'ing Mark Brown)
Hi Mark
[snip]
> >
> > Anyway, we spent enough time on naming issues, starting from my first
> > stupid 'pdwn' permutations then on this semi-standard names.
> >
> > I'll send next
Sorry for the mess
subject should have been
Subject: [PATCH 0/7] V3M-Eagle display enablement
I copied the wrong one from another cover letter...
On Fri, Apr 06, 2018 at 03:08:05PM +0200, Jacopo Mondi wrote:
> Hello,
>this series enables HDMI display on V3M Eagle board.
>
>
Add DRM bridge driver for Thine THC63LVD1024 LVDS to digital parallel
output converter.
Signed-off-by: Jacopo Mondi <jacopo+rene...@jmondi.org>
Reviewed-by: Andrzej Hajda <a.ha...@samsung.com>
Reviewed-by: Niklas Söderlund <niklas.soderlund+rene...@ragnatech.se>
---
driv
ve "lvds-decoder" references
-- Rework Eagle DTS to use new bindings
v1 -> v2:
- Drop support for THC63LVD1024
Jacopo Mondi (2):
dt-bindings: display: bridge: Document THC63LVD1024 LVDS decoder
drm: bridge: Add thc63lvd1024 LVDS decoder driver
.../bindings/display/bridge/th
Document Thine THC63LVD1024 LVDS decoder device tree bindings.
Signed-off-by: Jacopo Mondi <jacopo+rene...@jmondi.org>
Reviewed-by: Andrzej Hajda <a.ha...@samsung.com>
Reviewed-by: Niklas Söderlund <niklas.soderlund+rene...@ragnatech.se>
Reviewed-by: Laurent Pinch
Hello,
small self review, as I've just noticed a trivial error.
On Tue, Apr 10, 2018 at 12:53:10PM +0200, Jacopo Mondi wrote:
> Add DRM bridge driver for Thine THC63LVD1024 LVDS to digital parallel
> output converter.
>
> Signed-off-by: Jacopo Mondi <jacopo+rene...@jmondi.
Hi Laurent,
On Fri, Apr 06, 2018 at 04:51:11PM +0300, Laurent Pinchart wrote:
> Hi Jacopo,
>
> Thank you for the patch.
>
> On Friday, 6 April 2018 16:08:12 EEST Jacopo Mondi wrote:
> > From: Niklas Söderlund <niklas.soderlund+rene...@ragnatech.se>
> >
>
Hi Laurent,
On Fri, Apr 06, 2018 at 04:53:43PM +0300, Laurent Pinchart wrote:
> Hi Jacopo,
>
> On Friday, 6 April 2018 16:08:05 EEST Jacopo Mondi wrote:
> > Hello,
> >this series enables HDMI display on V3M Eagle board.
> >
> > The series is based on Geert's
Hi Laurent,
On Fri, Apr 06, 2018 at 04:15:35PM +0300, Laurent Pinchart wrote:
> Hi Jacopo,
>
> Thank you for the patch.
>
> On Friday, 6 April 2018 15:41:56 EEST Jacopo Mondi wrote:
> > Document Thine THC63LVD1024 LVDS decoder device tree bindings.
> >
> > Signed-
Document Thine THC63LVD1024 LVDS decoder device tree bindings.
Signed-off-by: Jacopo Mondi <jacopo+rene...@jmondi.org>
Reviewed-by: Andrzej Hajda <a.ha...@samsung.com>
Reviewed-by: Niklas Söderlund <niklas.soderlund+rene...@ragnatech.se>
Reviewed-by: Laurent Pinch
Hi Vladimir,
On Thu, Apr 19, 2018 at 02:18:30PM +0300, Vladimir Zapolskiy wrote:
> Hi Jacopo,
>
> On 04/10/2018 01:53 PM, Jacopo Mondi wrote:
> > Add DRM bridge driver for Thine THC63LVD1024 LVDS to digital parallel
> > output converter.
> >
> > Signed-
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