[PATCH v2] dt-bindings: lcdif: Document the dmas/dma-names properties
From: Fabio Estevam i.MX28 has an RX DMA channel associated with the LCDIF controller. Document the 'dmas' and 'dma-names' properties to fix the following dt-schema warnings: lcdif@8003: 'dma-names', 'dmas' do not match any of the regexes: 'pinctrl-[0-9]+' Signed-off-by: Fabio Estevam Reviewed-by: Krzysztof Kozlowski --- Changes since v1: - Add a blank line before the examples. (Krzysztof) .../bindings/display/fsl,lcdif.yaml | 20 +++ 1 file changed, 20 insertions(+) diff --git a/Documentation/devicetree/bindings/display/fsl,lcdif.yaml b/Documentation/devicetree/bindings/display/fsl,lcdif.yaml index 0681fc49aa1b..8e3a98aeec32 100644 --- a/Documentation/devicetree/bindings/display/fsl,lcdif.yaml +++ b/Documentation/devicetree/bindings/display/fsl,lcdif.yaml @@ -50,6 +50,14 @@ properties: - const: disp_axi minItems: 1 + dmas: +items: + - description: DMA specifier for the RX DMA channel. + + dma-names: +items: + - const: rx + interrupts: items: - description: LCDIF DMA interrupt @@ -156,6 +164,18 @@ allOf: interrupts: maxItems: 1 + - if: + not: +properties: + compatible: +contains: + enum: +- fsl,imx28-lcdif +then: + properties: +dmas: false +dma-names: false + examples: - | #include -- 2.34.1
Re: [PATCH] dt-bindings: lcdif: Document the dmas/dma-names properties
Hi Marek, On Tue, Sep 3, 2024 at 1:51 PM Marek Vasut wrote: > This also applies to MX23 , that one also has the support for > command-mode LCDs which are then driven by pumping commands via DMA. I > don't think Linux actually supports this mode of operation, but I do > recall using it some long time ago on MX23. I checked the i.MX23 Reference Manual and no LCDIF DMA entry is listed in either Table 10-1. APBH DMA Channel Assignments or Table 11-1. APBX DMA Channel Assignments.
[PATCH] dt-bindings: lcdif: Document the dmas/dma-names properties
From: Fabio Estevam i.MX28 has an RX DMA channel associated with the LCDIF controller. Document the 'dmas' and 'dma-names' properties to fix the following dt-schema warnings: lcdif@8003: 'dma-names', 'dmas' do not match any of the regexes: 'pinctrl-[0-9]+' Signed-off-by: Fabio Estevam --- .../bindings/display/fsl,lcdif.yaml | 19 +++ 1 file changed, 19 insertions(+) diff --git a/Documentation/devicetree/bindings/display/fsl,lcdif.yaml b/Documentation/devicetree/bindings/display/fsl,lcdif.yaml index 0681fc49aa1b..dd462abd61f8 100644 --- a/Documentation/devicetree/bindings/display/fsl,lcdif.yaml +++ b/Documentation/devicetree/bindings/display/fsl,lcdif.yaml @@ -50,6 +50,14 @@ properties: - const: disp_axi minItems: 1 + dmas: +items: + - description: DMA specifier for the RX DMA channel. + + dma-names: +items: + - const: rx + interrupts: items: - description: LCDIF DMA interrupt @@ -156,6 +164,17 @@ allOf: interrupts: maxItems: 1 + - if: + not: +properties: + compatible: +contains: + enum: +- fsl,imx28-lcdif +then: + properties: +dmas: false +dma-names: false examples: - | #include -- 2.34.1
Re: [PATCH 1/6] drm/bridge: imx8mp-hdmi-tx: Switch to SYSTEM_SLEEP_PM_OPS()
A gentle ping on this series.
Thanks
On Wed, Jun 26, 2024 at 8:07 PM Fabio Estevam wrote:
>
> From: Fabio Estevam
>
> Replace SET_SYSTEM_SLEEP_PM_OPS with its modern SYSTEM_SLEEP_PM_OPS()
> alternative.
>
> The combined usage of pm_ptr() and SYSTEM_SLEEP_PM_OPS()
> allows the compiler to evaluate if the runtime suspend/resume() functions
> are used at build time or are simply dead code.
>
> This allows removing the __maybe_unused notation from the runtime
> suspend/resume() functions.
>
> Signed-off-by: Fabio Estevam
> ---
> drivers/gpu/drm/bridge/imx/imx8mp-hdmi-tx.c | 9 -
> 1 file changed, 4 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/bridge/imx/imx8mp-hdmi-tx.c
> b/drivers/gpu/drm/bridge/imx/imx8mp-hdmi-tx.c
> index 13bc570c5473..4a3a8a3ce250 100644
> --- a/drivers/gpu/drm/bridge/imx/imx8mp-hdmi-tx.c
> +++ b/drivers/gpu/drm/bridge/imx/imx8mp-hdmi-tx.c
> @@ -111,12 +111,12 @@ static void imx8mp_dw_hdmi_remove(struct
> platform_device *pdev)
> dw_hdmi_remove(hdmi->dw_hdmi);
> }
>
> -static int __maybe_unused imx8mp_dw_hdmi_pm_suspend(struct device *dev)
> +static int imx8mp_dw_hdmi_pm_suspend(struct device *dev)
> {
> return 0;
> }
>
> -static int __maybe_unused imx8mp_dw_hdmi_pm_resume(struct device *dev)
> +static int imx8mp_dw_hdmi_pm_resume(struct device *dev)
> {
> struct imx8mp_hdmi *hdmi = dev_get_drvdata(dev);
>
> @@ -126,8 +126,7 @@ static int __maybe_unused imx8mp_dw_hdmi_pm_resume(struct
> device *dev)
> }
>
> static const struct dev_pm_ops imx8mp_dw_hdmi_pm_ops = {
> - SET_SYSTEM_SLEEP_PM_OPS(imx8mp_dw_hdmi_pm_suspend,
> - imx8mp_dw_hdmi_pm_resume)
> + SYSTEM_SLEEP_PM_OPS(imx8mp_dw_hdmi_pm_suspend,
> imx8mp_dw_hdmi_pm_resume)
> };
>
> static const struct of_device_id imx8mp_dw_hdmi_of_table[] = {
> @@ -142,7 +141,7 @@ static struct platform_driver
> imx8mp_dw_hdmi_platform_driver = {
> .driver = {
> .name = "imx8mp-dw-hdmi-tx",
> .of_match_table = imx8mp_dw_hdmi_of_table,
> - .pm = &imx8mp_dw_hdmi_pm_ops,
> + .pm = pm_ptr(&imx8mp_dw_hdmi_pm_ops),
> },
> };
>
> --
> 2.34.1
>
[PATCH 6/6] drm/bridge: imx8qxp-ldb: Switch to RUNTIME_PM_OPS()
From: Fabio Estevam
Replace SET_RUNTIME_PM_OPS with its modern RUNTIME_PM_OPS() alternative.
The combined usage of pm_ptr() and RUNTIME_PM_OPS()
allows the compiler to evaluate if the runtime suspend/resume() functions
are used at build time or are simply dead code.
This allows removing the __maybe_unused notation from the runtime
suspend/resume() functions.
Signed-off-by: Fabio Estevam
---
drivers/gpu/drm/bridge/imx/imx8qxp-ldb.c | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/bridge/imx/imx8qxp-ldb.c
b/drivers/gpu/drm/bridge/imx/imx8qxp-ldb.c
index 7984da9c0a35..b33011f397f0 100644
--- a/drivers/gpu/drm/bridge/imx/imx8qxp-ldb.c
+++ b/drivers/gpu/drm/bridge/imx/imx8qxp-ldb.c
@@ -678,12 +678,12 @@ static void imx8qxp_ldb_remove(struct platform_device
*pdev)
pm_runtime_disable(&pdev->dev);
}
-static int __maybe_unused imx8qxp_ldb_runtime_suspend(struct device *dev)
+static int imx8qxp_ldb_runtime_suspend(struct device *dev)
{
return 0;
}
-static int __maybe_unused imx8qxp_ldb_runtime_resume(struct device *dev)
+static int imx8qxp_ldb_runtime_resume(struct device *dev)
{
struct imx8qxp_ldb *imx8qxp_ldb = dev_get_drvdata(dev);
struct ldb *ldb = &imx8qxp_ldb->base;
@@ -695,8 +695,7 @@ static int __maybe_unused imx8qxp_ldb_runtime_resume(struct
device *dev)
}
static const struct dev_pm_ops imx8qxp_ldb_pm_ops = {
- SET_RUNTIME_PM_OPS(imx8qxp_ldb_runtime_suspend,
- imx8qxp_ldb_runtime_resume, NULL)
+ RUNTIME_PM_OPS(imx8qxp_ldb_runtime_suspend, imx8qxp_ldb_runtime_resume,
NULL)
};
static const struct of_device_id imx8qxp_ldb_dt_ids[] = {
@@ -709,7 +708,7 @@ static struct platform_driver imx8qxp_ldb_driver = {
.probe = imx8qxp_ldb_probe,
.remove_new = imx8qxp_ldb_remove,
.driver = {
- .pm = &imx8qxp_ldb_pm_ops,
+ .pm = pm_ptr(&imx8qxp_ldb_pm_ops),
.name = DRIVER_NAME,
.of_match_table = imx8qxp_ldb_dt_ids,
},
--
2.34.1
[PATCH 5/6] drm/bridge: dw-hdmi-cec: Switch to SYSTEM_SLEEP_PM_OPS()
From: Fabio Estevam
Replace SET_SYSTEM_SLEEP_PM_OPS with its modern SYSTEM_SLEEP_PM_OPS()
alternative.
The combined usage of pm_ptr() and SYSTEM_SLEEP_PM_OPS()
allows the compiler to evaluate if the runtime suspend/resume() functions
are used at build time or are simply dead code.
This allows removing the __maybe_unused notation from the runtime
suspend/resume() functions.
Signed-off-by: Fabio Estevam
---
drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c
b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c
index 673661160e54..d4614de1ae1e 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c
@@ -312,7 +312,7 @@ static void dw_hdmi_cec_remove(struct platform_device *pdev)
cec_unregister_adapter(cec->adap);
}
-static int __maybe_unused dw_hdmi_cec_resume(struct device *dev)
+static int dw_hdmi_cec_resume(struct device *dev)
{
struct dw_hdmi_cec *cec = dev_get_drvdata(dev);
@@ -328,7 +328,7 @@ static int __maybe_unused dw_hdmi_cec_resume(struct device
*dev)
return 0;
}
-static int __maybe_unused dw_hdmi_cec_suspend(struct device *dev)
+static int dw_hdmi_cec_suspend(struct device *dev)
{
struct dw_hdmi_cec *cec = dev_get_drvdata(dev);
@@ -341,7 +341,7 @@ static int __maybe_unused dw_hdmi_cec_suspend(struct device
*dev)
}
static const struct dev_pm_ops dw_hdmi_cec_pm = {
- SET_SYSTEM_SLEEP_PM_OPS(dw_hdmi_cec_suspend, dw_hdmi_cec_resume)
+ SYSTEM_SLEEP_PM_OPS(dw_hdmi_cec_suspend, dw_hdmi_cec_resume)
};
static struct platform_driver dw_hdmi_cec_driver = {
@@ -349,7 +349,7 @@ static struct platform_driver dw_hdmi_cec_driver = {
.remove_new = dw_hdmi_cec_remove,
.driver = {
.name = "dw-hdmi-cec",
- .pm = &dw_hdmi_cec_pm,
+ .pm = pm_ptr(&dw_hdmi_cec_pm),
},
};
module_platform_driver(dw_hdmi_cec_driver);
--
2.34.1
[PATCH 4/6] drm/bridge: samsung-dsim: Switch to RUNTIME_PM_OPS()
From: Fabio Estevam
Replace SET_RUNTIME_PM_OPS with its modern RUNTIME_PM_OPS() alternative.
The combined usage of pm_ptr() and RUNTIME_PM_OPS()
allows the compiler to evaluate if the runtime suspend/resume() functions
are used at build time or are simply dead code.
This allows removing the __maybe_unused notation from the runtime
suspend/resume() functions.
Signed-off-by: Fabio Estevam
---
drivers/gpu/drm/bridge/samsung-dsim.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c
b/drivers/gpu/drm/bridge/samsung-dsim.c
index e7e53a9e42af..73ccf21ae446 100644
--- a/drivers/gpu/drm/bridge/samsung-dsim.c
+++ b/drivers/gpu/drm/bridge/samsung-dsim.c
@@ -2043,7 +2043,7 @@ void samsung_dsim_remove(struct platform_device *pdev)
}
EXPORT_SYMBOL_GPL(samsung_dsim_remove);
-static int __maybe_unused samsung_dsim_suspend(struct device *dev)
+static int samsung_dsim_suspend(struct device *dev)
{
struct samsung_dsim *dsi = dev_get_drvdata(dev);
const struct samsung_dsim_driver_data *driver_data = dsi->driver_data;
@@ -2073,7 +2073,7 @@ static int __maybe_unused samsung_dsim_suspend(struct
device *dev)
return 0;
}
-static int __maybe_unused samsung_dsim_resume(struct device *dev)
+static int samsung_dsim_resume(struct device *dev)
{
struct samsung_dsim *dsi = dev_get_drvdata(dev);
const struct samsung_dsim_driver_data *driver_data = dsi->driver_data;
@@ -2108,7 +2108,7 @@ static int __maybe_unused samsung_dsim_resume(struct
device *dev)
}
const struct dev_pm_ops samsung_dsim_pm_ops = {
- SET_RUNTIME_PM_OPS(samsung_dsim_suspend, samsung_dsim_resume, NULL)
+ RUNTIME_PM_OPS(samsung_dsim_suspend, samsung_dsim_resume, NULL)
SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
pm_runtime_force_resume)
};
@@ -2142,7 +2142,7 @@ static struct platform_driver samsung_dsim_driver = {
.remove_new = samsung_dsim_remove,
.driver = {
.name = "samsung-dsim",
- .pm = &samsung_dsim_pm_ops,
+ .pm = pm_ptr(&samsung_dsim_pm_ops),
.of_match_table = samsung_dsim_of_match,
},
};
--
2.34.1
[PATCH 3/6] drm/bridge: imx8qxp-pixel-combiner: Switch to RUNTIME_PM_OPS()
From: Fabio Estevam
Replace SET_RUNTIME_PM_OPS with its modern RUNTIME_PM_OPS() alternative.
The combined usage of pm_ptr() and RUNTIME_PM_OPS()
allows the compiler to evaluate if the runtime suspend/resume() functions
are used at build time or are simply dead code.
This allows removing the __maybe_unused notation from the runtime
suspend/resume() functions.
Signed-off-by: Fabio Estevam
---
drivers/gpu/drm/bridge/imx/imx8qxp-pixel-combiner.c | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-combiner.c
b/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-combiner.c
index e6dbbdc87ce2..ce43e4069e21 100644
--- a/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-combiner.c
+++ b/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-combiner.c
@@ -371,7 +371,7 @@ static void imx8qxp_pc_bridge_remove(struct platform_device
*pdev)
pm_runtime_disable(&pdev->dev);
}
-static int __maybe_unused imx8qxp_pc_runtime_suspend(struct device *dev)
+static int imx8qxp_pc_runtime_suspend(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct imx8qxp_pc *pc = platform_get_drvdata(pdev);
@@ -393,7 +393,7 @@ static int __maybe_unused imx8qxp_pc_runtime_suspend(struct
device *dev)
return ret;
}
-static int __maybe_unused imx8qxp_pc_runtime_resume(struct device *dev)
+static int imx8qxp_pc_runtime_resume(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct imx8qxp_pc *pc = platform_get_drvdata(pdev);
@@ -415,8 +415,7 @@ static int __maybe_unused imx8qxp_pc_runtime_resume(struct
device *dev)
}
static const struct dev_pm_ops imx8qxp_pc_pm_ops = {
- SET_RUNTIME_PM_OPS(imx8qxp_pc_runtime_suspend,
- imx8qxp_pc_runtime_resume, NULL)
+ RUNTIME_PM_OPS(imx8qxp_pc_runtime_suspend, imx8qxp_pc_runtime_resume,
NULL)
};
static const struct of_device_id imx8qxp_pc_dt_ids[] = {
@@ -430,7 +429,7 @@ static struct platform_driver imx8qxp_pc_bridge_driver = {
.probe = imx8qxp_pc_bridge_probe,
.remove_new = imx8qxp_pc_bridge_remove,
.driver = {
- .pm = &imx8qxp_pc_pm_ops,
+ .pm = pm_ptr(&imx8qxp_pc_pm_ops),
.name = DRIVER_NAME,
.of_match_table = imx8qxp_pc_dt_ids,
},
--
2.34.1
[PATCH 2/6] drm/bridge: imx8qm-ldb: Switch to RUNTIME_PM_OPS()
From: Fabio Estevam
Replace SET_RUNTIME_PM_OPS with its modern RUNTIME_PM_OPS() alternative.
The combined usage of pm_ptr() and RUNTIME_PM_OPS()
allows the compiler to evaluate if the runtime suspend/resume() functions
are used at build time or are simply dead code.
This allows removing the __maybe_unused notation from the runtime
suspend/resume() functions.
Signed-off-by: Fabio Estevam
---
drivers/gpu/drm/bridge/imx/imx8qm-ldb.c | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/bridge/imx/imx8qm-ldb.c
b/drivers/gpu/drm/bridge/imx/imx8qm-ldb.c
index 21471a9a28b2..c879e37f5811 100644
--- a/drivers/gpu/drm/bridge/imx/imx8qm-ldb.c
+++ b/drivers/gpu/drm/bridge/imx/imx8qm-ldb.c
@@ -542,12 +542,12 @@ static void imx8qm_ldb_remove(struct platform_device
*pdev)
pm_runtime_disable(&pdev->dev);
}
-static int __maybe_unused imx8qm_ldb_runtime_suspend(struct device *dev)
+static int imx8qm_ldb_runtime_suspend(struct device *dev)
{
return 0;
}
-static int __maybe_unused imx8qm_ldb_runtime_resume(struct device *dev)
+static int imx8qm_ldb_runtime_resume(struct device *dev)
{
struct imx8qm_ldb *imx8qm_ldb = dev_get_drvdata(dev);
struct ldb *ldb = &imx8qm_ldb->base;
@@ -559,8 +559,7 @@ static int __maybe_unused imx8qm_ldb_runtime_resume(struct
device *dev)
}
static const struct dev_pm_ops imx8qm_ldb_pm_ops = {
- SET_RUNTIME_PM_OPS(imx8qm_ldb_runtime_suspend,
- imx8qm_ldb_runtime_resume, NULL)
+ RUNTIME_PM_OPS(imx8qm_ldb_runtime_suspend, imx8qm_ldb_runtime_resume,
NULL)
};
static const struct of_device_id imx8qm_ldb_dt_ids[] = {
@@ -573,7 +572,7 @@ static struct platform_driver imx8qm_ldb_driver = {
.probe = imx8qm_ldb_probe,
.remove_new = imx8qm_ldb_remove,
.driver = {
- .pm = &imx8qm_ldb_pm_ops,
+ .pm = pm_ptr(&imx8qm_ldb_pm_ops),
.name = DRIVER_NAME,
.of_match_table = imx8qm_ldb_dt_ids,
},
--
2.34.1
[PATCH 1/6] drm/bridge: imx8mp-hdmi-tx: Switch to SYSTEM_SLEEP_PM_OPS()
From: Fabio Estevam
Replace SET_SYSTEM_SLEEP_PM_OPS with its modern SYSTEM_SLEEP_PM_OPS()
alternative.
The combined usage of pm_ptr() and SYSTEM_SLEEP_PM_OPS()
allows the compiler to evaluate if the runtime suspend/resume() functions
are used at build time or are simply dead code.
This allows removing the __maybe_unused notation from the runtime
suspend/resume() functions.
Signed-off-by: Fabio Estevam
---
drivers/gpu/drm/bridge/imx/imx8mp-hdmi-tx.c | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/bridge/imx/imx8mp-hdmi-tx.c
b/drivers/gpu/drm/bridge/imx/imx8mp-hdmi-tx.c
index 13bc570c5473..4a3a8a3ce250 100644
--- a/drivers/gpu/drm/bridge/imx/imx8mp-hdmi-tx.c
+++ b/drivers/gpu/drm/bridge/imx/imx8mp-hdmi-tx.c
@@ -111,12 +111,12 @@ static void imx8mp_dw_hdmi_remove(struct platform_device
*pdev)
dw_hdmi_remove(hdmi->dw_hdmi);
}
-static int __maybe_unused imx8mp_dw_hdmi_pm_suspend(struct device *dev)
+static int imx8mp_dw_hdmi_pm_suspend(struct device *dev)
{
return 0;
}
-static int __maybe_unused imx8mp_dw_hdmi_pm_resume(struct device *dev)
+static int imx8mp_dw_hdmi_pm_resume(struct device *dev)
{
struct imx8mp_hdmi *hdmi = dev_get_drvdata(dev);
@@ -126,8 +126,7 @@ static int __maybe_unused imx8mp_dw_hdmi_pm_resume(struct
device *dev)
}
static const struct dev_pm_ops imx8mp_dw_hdmi_pm_ops = {
- SET_SYSTEM_SLEEP_PM_OPS(imx8mp_dw_hdmi_pm_suspend,
- imx8mp_dw_hdmi_pm_resume)
+ SYSTEM_SLEEP_PM_OPS(imx8mp_dw_hdmi_pm_suspend, imx8mp_dw_hdmi_pm_resume)
};
static const struct of_device_id imx8mp_dw_hdmi_of_table[] = {
@@ -142,7 +141,7 @@ static struct platform_driver
imx8mp_dw_hdmi_platform_driver = {
.driver = {
.name = "imx8mp-dw-hdmi-tx",
.of_match_table = imx8mp_dw_hdmi_of_table,
- .pm = &imx8mp_dw_hdmi_pm_ops,
+ .pm = pm_ptr(&imx8mp_dw_hdmi_pm_ops),
},
};
--
2.34.1
Re: [PATCH] drm/bridge: imx8mp-hdmi-pvi: Fix build warnings
Hi Adam,
On Tue, Feb 6, 2024 at 9:23 PM Adam Ford wrote:
>
> Two separate build warnings were reported. One from an
> uninitialized variable, and the other from returning 0
> instead of NULL from a pointer.
>
> Fixes: 059c53e877ca ("drm/bridge: imx: add driver for HDMI TX Parallel Video
> Interface")
> Reported-by: nat...@kernel.org
The Reported-by line format can be improved:
Reported-by: Nathan Chancellor
Thanks
Re: [PATCH V5 1/2] dt-bindings: display: imx: add binding for i.MX8MP HDMI PVI
Hi Adam, Thanks for moving this forward. On Fri, Jan 5, 2024 at 10:56 PM Adam Ford wrote: > > From: Lucas Stach > > Add binding for the i.MX8MP HDMI parallel video interface block. > > Signed-off-by: Lucas Stach > Reviewed-by: Laurent Pinchart > Reviewed-by: Conor Dooley You missed your own Signed-off-by tag.
Re: [PATCH 2/6] drm/panel: Add driver for BOE TH101MB31IG002-28A panel
On Fri, Dec 22, 2023 at 2:32 PM Manuel Traut wrote:
>
> From: Segfault
>
> The BOE TH101MB31IG002-28A panel is a WXGA panel.
> It is used in Pine64 Pinetab2 and PinetabV.
>
> Signed-off-by: Segfault
Please use a real name instead...
> +MODULE_AUTHOR("Alexander Warnecke ");
like here.
Re: [PATCH v3 2/2] drm/bridge: imx: add driver for HDMI TX Parallel Video Interface
On Fri, Dec 15, 2023 at 4:01 PM Adam Ford wrote: > Thanks for the list. I was able to successfully build the stable 6.6 > branch with those patches applied and I have the HDMI working. > Unfortunately, I get build errors on the linux-next, so it's going to > take me a little time to sort through all of this. If you need help to figure this problem out, please let me know. I haven't tried it against linux-next. > I am thinking that it would be better to consolidate all these > together into one series instead of piecemealing it. However, there > are some items that can be submitted right away without significantly > reworking them against linux-next. Do people have a preference? I think it makes sense to re-submit the "easy ones" right away.
Re: [PATCH v3 2/2] drm/bridge: imx: add driver for HDMI TX Parallel Video Interface
Hi Adam, On Fri, Dec 15, 2023 at 1:40 PM Adam Ford wrote: > I started looking into this today, but there appears to be some > dependencies missing because the PVI is just one small portion of > this. The PVI needs to interact with the hdmi_blk_ctrl and the hdmi > transmitter itself. > > It looks like there was at least one attempt to push the hdmi driver, > but we're also missing some hdmi power domain information, and the dri > patchwork lists a bunch of proposed patches for the lcdif driver. I > haven't looked through them all, so I don't know if they are > necessary. I found a git repo with Lucas' stuff, but it's based on > the 6.0 kernel, so it's fairly old. Either way it seems like there is > more to the HDMI than just his one series. Here is the whole patchset that I tested against 6.6: https://patchwork.freedesktop.org/patch/485391/ https://patchwork.freedesktop.org/patch/485392/ https://patchwork.freedesktop.org/patch/485395/ https://patchwork.freedesktop.org/patch/515299/ https://patchwork.freedesktop.org/patch/515300/ https://patchwork.kernel.org/project/linux-arm-kernel/patch/20220406153402.1265474-12-l.st...@pengutronix.de/
Re: [PATCH v3 2/2] drm/bridge: imx: add driver for HDMI TX Parallel Video Interface
Hi Adam, On Sun, Dec 10, 2023 at 2:35 PM Adam Ford wrote: > Lucas, > > It's been a few months since there has been any action. If you want, > I can help apply the suggestions that Laurent has and re-submit with > both of our names if you want. It would be nice to get this > integrated. It would be nice if you could re-submit the series. Thanks
Re: [PATCH 1/3] drm/mxsfb: Add an entry for "fsl,imx8mq-lcdif"
Hi Lucas, On Tue, Dec 12, 2023 at 3:19 PM Lucas Stach wrote: > I don't really like this series. While we don't make any strong > guarantees in this way, it breaks booting older kernels with a new DT. I thought we needed only to guarantee that old DTs still run with newer kernels, not the other way around. > As this driver patch shows, there are no actual differences in the IP > block between i.MX6SX and i.MX8MQ, it's just the SoC integration that's > different, where in one SoC the controller is located in a power > domain, while it isn't in another. > > To me this smells like making changes to parts that don't really care > about those differences. The thing that cares about the difference is > the DT schema validation and I feel like there must be a better way to > describe this in the schema than to patch both driver and DT just to > accommodate a SoC integration difference. Is there a way to make the > power-domain property not dependent on the IP block, but the machine > compatible? Yes, this series is all about making dt-schema validation happy. If there is a better alternative, I am all ears. Rob, Krzysztof, Conor Any suggestions? Thanks
[PATCH 3/3] arm64: dts: imx8mq: Exclude "fsl,imx6sx-lcdif"
From: Fabio Estevam
On i.MX6SX, the LCDIF has an associated power domain.
i.MX8MQ does not have an LCDIF power domain, so pass only
"fsl,imx8mq-lcdif" as compatible string to fix the following
dt-schema warning:
imx8mq-evk.dtb: lcd-controller@3032: 'power-domains' is a required property
from schema $id: http://devicetree.org/schemas/display/fsl,lcdif.yaml#
Signed-off-by: Fabio Estevam
---
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index c6dc3ba0d43b..5d8365e4eb26 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -739,7 +739,7 @@ sdma2: dma-controller@302c {
};
lcdif: lcd-controller@3032 {
- compatible = "fsl,imx8mq-lcdif",
"fsl,imx6sx-lcdif";
+ compatible = "fsl,imx8mq-lcdif";
reg = <0x3032 0x1>;
interrupts = ;
clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>,
--
2.34.1
[PATCH 2/3] dt-bindings: lcdif: Decouple imx8mq from imx6sx
From: Fabio Estevam On i.MX6SX, the LCDIF has an associated power domain. i.MX8MQ does not have an LCDIF power domain, so allow passing only "fsl,imx8mq-lcdif" as compatible string to fix the following dt-schema warning: imx8mq-evk.dtb: lcd-controller@3032: 'power-domains' is a required property from schema $id: http://devicetree.org/schemas/display/fsl,lcdif.yaml# Signed-off-by: Fabio Estevam --- Documentation/devicetree/bindings/display/fsl,lcdif.yaml | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/fsl,lcdif.yaml b/Documentation/devicetree/bindings/display/fsl,lcdif.yaml index 1c2be8d6f633..8969e56d4c98 100644 --- a/Documentation/devicetree/bindings/display/fsl,lcdif.yaml +++ b/Documentation/devicetree/bindings/display/fsl,lcdif.yaml @@ -20,6 +20,7 @@ properties: - fsl,imx23-lcdif - fsl,imx28-lcdif - fsl,imx6sx-lcdif + - fsl,imx8mq-lcdif - fsl,imx8mp-lcdif - fsl,imx93-lcdif - items: @@ -77,7 +78,9 @@ allOf: properties: compatible: contains: -const: fsl,imx6sx-lcdif +enum: + - fsl,imx6sx-lcdif + - fsl,imx8mq-lcdif then: properties: clocks: @@ -113,6 +116,7 @@ allOf: enum: - fsl,imx6sx-lcdif - fsl,imx8mp-lcdif +- fsl,imx8mq-lcdif - fsl,imx93-lcdif then: properties: -- 2.34.1
[PATCH 1/3] drm/mxsfb: Add an entry for "fsl,imx8mq-lcdif"
From: Fabio Estevam
On i.MX6SX, the LCDIF has an associated power domain.
However, i.MX8MQ does not have an LCDIF power domain.
imx8mq.dtsi has the following compatible string:
compatible = "fsl,imx8mq-lcdif", "fsl,imx6sx-lcdif";
which causes the following dt-schema warning:
imx8mq-evk.dtb: lcd-controller@3032: 'power-domains' is a required property
from schema $id: http://devicetree.org/schemas/display/fsl,lcdif.yaml#
To prevent this problem, add a specific fsl,imx8mq-lcdif entry in
the driver to properly handle such a power-domain requirement difference.
Signed-off-by: Fabio Estevam
---
drivers/gpu/drm/mxsfb/mxsfb_drv.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/mxsfb/mxsfb_drv.c
b/drivers/gpu/drm/mxsfb/mxsfb_drv.c
index b483ef48216a..ac9ce3b45b38 100644
--- a/drivers/gpu/drm/mxsfb/mxsfb_drv.c
+++ b/drivers/gpu/drm/mxsfb/mxsfb_drv.c
@@ -340,6 +340,7 @@ static const struct of_device_id mxsfb_dt_ids[] = {
{ .compatible = "fsl,imx23-lcdif", .data = &mxsfb_devdata[MXSFB_V3], },
{ .compatible = "fsl,imx28-lcdif", .data = &mxsfb_devdata[MXSFB_V4], },
{ .compatible = "fsl,imx6sx-lcdif", .data = &mxsfb_devdata[MXSFB_V6], },
+ { .compatible = "fsl,imx8mq-lcdif", .data = &mxsfb_devdata[MXSFB_V6], },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, mxsfb_dt_ids);
--
2.34.1
Re: Question about device links between supplier and consumer
Hi Richard, On Thu, Dec 7, 2023 at 10:43 AM Rafael J. Wysocki wrote: > > Otherwise, the mmc driver will be defer probed after the init > > executed, as you can imagine, the init will complain it can not find > > the dev node specified by the 'root=/dev/xxx' in the kernel. command > > line. Have you tried passing 'rootwait' into your kernel command line? That should fix the problem.
[PATCH v2] dt-bindings: lcdif: Properly describe the i.MX23 interrupts
From: Fabio Estevam i.MX23 has two LCDIF interrupts instead of a single one like other i.MX devices. Take this into account for properly describing the i.MX23 LCDIF interrupts. This fixes the following dt-schema warning: imx23-olinuxino.dtb: lcdif@8003: interrupts: [[46], [45]] is too long from schema $id: http://devicetree.org/schemas/display/fsl,lcdif.yaml# Signed-off-by: Fabio Estevam Reviewed-by: Marek Vasut --- Changes since v1: - Add missing else to limit the number of irqs for the other variants. (Krzysztof) .../bindings/display/fsl,lcdif.yaml | 20 ++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/fsl,lcdif.yaml b/Documentation/devicetree/bindings/display/fsl,lcdif.yaml index fc11ab5fc465..1c2be8d6f633 100644 --- a/Documentation/devicetree/bindings/display/fsl,lcdif.yaml +++ b/Documentation/devicetree/bindings/display/fsl,lcdif.yaml @@ -51,7 +51,10 @@ properties: minItems: 1 interrupts: -maxItems: 1 +items: + - description: LCDIF DMA interrupt + - description: LCDIF Error interrupt +minItems: 1 power-domains: maxItems: 1 @@ -131,6 +134,21 @@ allOf: then: required: - power-domains + - if: + properties: +compatible: + contains: +enum: + - fsl,imx23-lcdif +then: + properties: +interrupts: + minItems: 2 + maxItems: 2 +else: + properties: +interrupts: + maxItems: 1 examples: - | -- 2.34.1
[PATCH v2] dt-bindings: display: adi, adv75xx: Document #sound-dai-cells
From: Fabio Estevam When using audio from ADV7533 or ADV7535 and describing the audio card via simple-audio-card, the '#sound-dai-cells' needs to be passed. Document the '#sound-dai-cells' property to fix the following dt-schema warning: imx8mn-beacon-kit.dtb: hdmi@3d: '#sound-dai-cells' does not match any of the regexes: 'pinctrl-[0-9]+' from schema $id: http://devicetree.org/schemas/display/bridge/adi,adv7533.yaml# Signed-off-by: Fabio Estevam Acked-by: Adam Ford --- Changes since v1: - Also pass '$ref: /schemas/sound/dai-common.yaml#' (Krzysztof). .../devicetree/bindings/display/bridge/adi,adv7533.yaml | 6 ++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/display/bridge/adi,adv7533.yaml b/Documentation/devicetree/bindings/display/bridge/adi,adv7533.yaml index 987aa83c2649..df20a3c9c744 100644 --- a/Documentation/devicetree/bindings/display/bridge/adi,adv7533.yaml +++ b/Documentation/devicetree/bindings/display/bridge/adi,adv7533.yaml @@ -9,6 +9,9 @@ title: Analog Devices ADV7533/35 HDMI Encoders maintainers: - Laurent Pinchart +allOf: + - $ref: /schemas/sound/dai-common.yaml# + description: | The ADV7533 and ADV7535 are HDMI audio and video transmitters compatible with HDMI 1.4 and DVI 1.0. They support color space @@ -89,6 +92,9 @@ properties: $ref: /schemas/types.yaml#/definitions/uint32 enum: [ 1, 2, 3, 4 ] + "#sound-dai-cells": +const: 0 + ports: description: The ADV7533/35 has two video ports and one audio port. -- 2.34.1
[PATCH] dt-bindings: display: adi,adv75xx: Document #sound-dai-cells
From: Fabio Estevam When using audio from ADV7533 or ADV7535 and describing the audio card via simple-audio-card, the '#sound-dai-cells' needs to be passed. Document the '#sound-dai-cells' property to fix the following dt-schema warning: imx8mn-beacon-kit.dtb: hdmi@3d: '#sound-dai-cells' does not match any of the regexes: 'pinctrl-[0-9]+' from schema $id: http://devicetree.org/schemas/display/bridge/adi,adv7533.yaml# Signed-off-by: Fabio Estevam --- .../devicetree/bindings/display/bridge/adi,adv7533.yaml| 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/display/bridge/adi,adv7533.yaml b/Documentation/devicetree/bindings/display/bridge/adi,adv7533.yaml index 987aa83c2649..e15ae072922e 100644 --- a/Documentation/devicetree/bindings/display/bridge/adi,adv7533.yaml +++ b/Documentation/devicetree/bindings/display/bridge/adi,adv7533.yaml @@ -89,6 +89,9 @@ properties: $ref: /schemas/types.yaml#/definitions/uint32 enum: [ 1, 2, 3, 4 ] + '#sound-dai-cells': +const: 0 + ports: description: The ADV7533/35 has two video ports and one audio port. -- 2.34.1
[PATCH v2] dt-bindings: lcdif: Properly describe the i.MX23 interrupts
From: Fabio Estevam i.MX23 has two LCDIF interrupts instead of a single one like other i.MX devices. Take this into account for properly describing the i.MX23 LCDIF interrupts. This fixes the following dt-schema warning: imx23-olinuxino.dtb: lcdif@8003: interrupts: [[46], [45]] is too long from schema $id: http://devicetree.org/schemas/display/fsl,lcdif.yaml# Signed-off-by: Fabio Estevam --- Changes since v1: - Fix typo in commit log (i.MX23 has two LCDIF interrupts). .../devicetree/bindings/display/fsl,lcdif.yaml | 16 +++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/fsl,lcdif.yaml b/Documentation/devicetree/bindings/display/fsl,lcdif.yaml index fc11ab5fc465..c4228b893766 100644 --- a/Documentation/devicetree/bindings/display/fsl,lcdif.yaml +++ b/Documentation/devicetree/bindings/display/fsl,lcdif.yaml @@ -51,7 +51,10 @@ properties: minItems: 1 interrupts: -maxItems: 1 +items: + - description: LCDIF DMA interrupt + - description: LCDIF Error interrupt +minItems: 1 power-domains: maxItems: 1 @@ -131,6 +134,17 @@ allOf: then: required: - power-domains + - if: + properties: +compatible: + contains: +enum: + - fsl,imx23-lcdif +then: + properties: +interrupts: + minItems: 2 + maxItems: 2 examples: - | -- 2.34.1
[PATCH] dt-bindings: lcdif: Properly describe the i.MX23 interrupts
From: Fabio Estevam i.MX23 has two i.MX23 interrupts instead of a single one like other i.MX devices. Take this into account for properly describing the i.MX23 LCDIF interrupts. This fixes the following dt-schema warning: imx23-olinuxino.dtb: lcdif@8003: interrupts: [[46], [45]] is too long from schema $id: http://devicetree.org/schemas/display/fsl,lcdif.yaml# Signed-off-by: Fabio Estevam --- .../devicetree/bindings/display/fsl,lcdif.yaml | 16 +++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/fsl,lcdif.yaml b/Documentation/devicetree/bindings/display/fsl,lcdif.yaml index fc11ab5fc465..c4228b893766 100644 --- a/Documentation/devicetree/bindings/display/fsl,lcdif.yaml +++ b/Documentation/devicetree/bindings/display/fsl,lcdif.yaml @@ -51,7 +51,10 @@ properties: minItems: 1 interrupts: -maxItems: 1 +items: + - description: LCDIF DMA interrupt + - description: LCDIF Error interrupt +minItems: 1 power-domains: maxItems: 1 @@ -131,6 +134,17 @@ allOf: then: required: - power-domains + - if: + properties: +compatible: + contains: +enum: + - fsl,imx23-lcdif +then: + properties: +interrupts: + minItems: 2 + maxItems: 2 examples: - | -- 2.34.1
Re: [PATCH v4 2/2] drm/bridge: imx: add driver for HDMI TX Parallel Video Interface
Hi Lucas, On Thu, Sep 28, 2023 at 9:56 AM Lucas Stach wrote: > > This IP block is found in the HDMI subsystem of the i.MX8MP SoC. It has a > full timing generator and can switch between different video sources. On > the i.MX8MP however the only supported source is the LCDIF. The block > just needs to be powered up and told about the polarity of the video > sync signals to act in bypass mode. > > Signed-off-by: Lucas Stach > Reviewed-by: Luca Ceresoli (v2) > Tested-by: Marek Vasut (v1) > Tested-by: Luca Ceresoli (v2) > Tested-by: Richard Leitner (v2) > Tested-by: Frieder Schrempf (v2) > Reviewed-by: Laurent Pinchart (v3) Tested-by: Fabio Estevam Could someone apply this series, please?
Re: [PATCH] drm/rockchip: lvds: do not print error message when deferring probe
Hi Quentin,
On Fri, Nov 17, 2023 at 3:31 PM Quentin Schulz wrote:
>
> From: Quentin Schulz
>
> This scary message may happen if the panel or bridge is not probed
> before the LVDS controller is, resulting in some head scratching because
> the LVDS panel is actually working, since a later try will eventually
> find the panel or bridge.
>
> Therefore let's demote this error message into a debug message to not
> scare users unnecessarily.
...
> diff --git a/drivers/gpu/drm/rockchip/rockchip_lvds.c
> b/drivers/gpu/drm/rockchip/rockchip_lvds.c
> index f0f47e9abf5a..52e2ce2a61a8 100644
> --- a/drivers/gpu/drm/rockchip/rockchip_lvds.c
> +++ b/drivers/gpu/drm/rockchip/rockchip_lvds.c
> @@ -577,7 +577,7 @@ static int rockchip_lvds_bind(struct device *dev, struct
> device *master,
> ret = -EINVAL;
> goto err_put_port;
> } else if (ret) {
> - DRM_DEV_ERROR(dev, "failed to find panel and bridge node\n");
> + DRM_DEV_DEBUG(dev, "failed to find panel and bridge node\n");
> ret = -EPROBE_DEFER;
What about using dev_err_probe() instead?
Re: [PATCH] drm: bridge: adv7511: fix reading edid segments
Hi Emil, On Thu, Oct 26, 2023 at 11:47 AM Emil Abildgaard Svendsen wrote: > > Currently reading EDID only works because usually only two EDID blocks > of 128 bytes is used. Where an EDID segment holds 256 bytes or two EDID > blocks. And the first EDID segment read works fine but E-EDID specifies > up to 128 segments. > > The logic is broken so change EDID segment index to multiple of 256 > bytes and not 128 (block size). > > Also change check of DDC status. Instead of silently not reading EDID > when in "IDLE" state [1]. Check if the DDC controller is in reset > instead (no HPD). > > [1] > ADV7511 Programming Guide: Table 11: DDCController Status: > > 0xC8 [3:0] DDC Controller State > > In Reset (No Hot Plug Detected) > 0001Reading EDID > 0010IDLE (Waiting for HDCP Requested) > 0011Initializing HDCP > 0100HDCP Enabled > 0101Initializing HDCP Repeater > > Signed-off-by: Emil Svendsen What about passing a Fixes tag?
[PATCH] dt-bindings: display: fsl, imx6-hdmi: Change to 'unevaluatedProperties: false'
From: Fabio Estevam fsl,imx6-hdmi.yaml makes a reference to synopsys,dw-hdmi.yaml. The 'interrupts'and 'reg' properties are described in synopsys,dw-hdmi.yaml, so use 'unevaluatedProperties: false' so that these two properties can be accepted. This fixes the following schema warnings: hdmi@12: 'interrupts', 'reg' do not match any of the regexes: 'pinctrl-[0-9]+' from schema $id: http://devicetree.org/schemas/display/imx/fsl,imx6-hdmi.yaml# Signed-off-by: Fabio Estevam --- .../devicetree/bindings/display/imx/fsl,imx6-hdmi.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx6-hdmi.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx6-hdmi.yaml index af7fe9c4d196..7979cf07f119 100644 --- a/Documentation/devicetree/bindings/display/imx/fsl,imx6-hdmi.yaml +++ b/Documentation/devicetree/bindings/display/imx/fsl,imx6-hdmi.yaml @@ -87,7 +87,7 @@ required: - interrupts - ports -additionalProperties: false +unevaluatedProperties: false examples: - | -- 2.34.1
Re: [PATCH] drm/imx: Add error handling in dw_hdmi_imx_probe()
On Sun, Sep 24, 2023 at 11:36 AM liuhaoran wrote: > > This patch adds error-handling for the of_match_node() > inside the dw_hdmi_imx_probe(). > > Signed-off-by: liuhaoran > --- > drivers/gpu/drm/imx/ipuv3/dw_hdmi-imx.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/gpu/drm/imx/ipuv3/dw_hdmi-imx.c > b/drivers/gpu/drm/imx/ipuv3/dw_hdmi-imx.c > index a2277a0d6d06..3b25f018b2a6 100644 > --- a/drivers/gpu/drm/imx/ipuv3/dw_hdmi-imx.c > +++ b/drivers/gpu/drm/imx/ipuv3/dw_hdmi-imx.c > @@ -224,6 +224,9 @@ static int dw_hdmi_imx_probe(struct platform_device *pdev) > struct imx_hdmi *hdmi; > int ret; > > + if (!match) > + return -ENODEV; > + This check is not needed. The only way this driver can probe is via devicetree and this can only happen when match is non-NULL.
Re: [PATCH 4/5] drm/bridge: samsung-dsim: adjust porches by rounding up
Hi Michael, On Mon, Aug 28, 2023 at 12:59 PM Michael Tretter wrote: > > The porches must be rounded up to make the samsung-dsim work. The commit log could be improved here. The way it is written gives the impression that samsung-dsim does not work currently.
Re: [PATCH 0/7] ADV7511 driver enhancements
Hi Biju, On Sun, Aug 13, 2023 at 3:05 PM Biju Das wrote: > > This patch series aims to improve ADV7511 driver by adding > feature bits and data instead of comparing enum adv7511_type for > various hardware differences between ADV7511, ADV7533 and ADV7535. > > This patch series tested with[1] on RZ/G2L SMARC EVK which embeds > ADV7535. I have successfully tested this series on a imx8mm-evk, which has an ADV7535: Tested-by: Fabio Estevam
Re: [PATCH v2] drm: bridge: samsung-dsim: Fix init during host transfer
Hi Tim, On Thu, Aug 17, 2023 at 5:53 PM Tim Harvey wrote: > Frieder, > > Sorry for the delay. Yes this resolves the regression I ran into. I > tested it on top of v6.5-rc6 on a gw72xx-0x with a DFROBOT DRF0678 7in > 800x480 (Raspberry Pi) display which has the Toshiba TC358762 > compatible DSI to DBI bridge. > > Let's please get this into v6.5 as soon as possible. Care to provide your Tested-by tag?
Re: [PATCH v3] drm/msm/a2xx: Call adreno_gpu_init() earlier
Hi Rob,
Any comments, please?
On Mon, Jul 24, 2023 at 5:28 PM Fabio Estevam wrote:
>
> Hi Rob,
>
> A gentle ping.
>
> On Thu, Jun 22, 2023 at 3:37 PM Dmitry Baryshkov
> wrote:
> >
> > On 21/06/2023 02:23, Fabio Estevam wrote:
> > > From: Fabio Estevam
> > >
> > > The adreno_is_a20x() and adreno_is_a225() functions rely on the
> > > GPU revision, but such information is retrieved inside adreno_gpu_init(),
> > > which is called afterwards.
> > >
> > > Fix this problem by caling adreno_gpu_init() earlier, so that
> > > the GPU information revision is available when adreno_is_a20x()
> > > and adreno_is_a225() run.
> > >
> > > Tested on a imx53-qsb board.
> > >
> > > Fixes: 21af872cd8c6 ("drm/msm/adreno: add a2xx")
> > > Signed-off-by: Fabio Estevam
> > > ---
> > > Hi,
> > >
> > > This error has been exposed by a recent commit in linux-next:
> > >
> > > cc943f43ece7 ("drm/msm/adreno: warn if chip revn is verified before being
> > > set")
> > >
> > > , but the error has been present since the very first a2xx commit.
> > >
> > > Changes since v2:
> > > - Call adreno_gpu_init() earlier.
> >
> > Reviewed-by: Dmitry Baryshkov
> >
> >
> > >
> > > drivers/gpu/drm/msm/adreno/a2xx_gpu.c | 8
> > > 1 file changed, 4 insertions(+), 4 deletions(-)
> >
> >
> > --
> > With best wishes
> > Dmitry
> >
Re: [PATCH v3] drm/msm/a2xx: Call adreno_gpu_init() earlier
Hi Rob,
A gentle ping.
On Thu, Jun 22, 2023 at 3:37 PM Dmitry Baryshkov
wrote:
>
> On 21/06/2023 02:23, Fabio Estevam wrote:
> > From: Fabio Estevam
> >
> > The adreno_is_a20x() and adreno_is_a225() functions rely on the
> > GPU revision, but such information is retrieved inside adreno_gpu_init(),
> > which is called afterwards.
> >
> > Fix this problem by caling adreno_gpu_init() earlier, so that
> > the GPU information revision is available when adreno_is_a20x()
> > and adreno_is_a225() run.
> >
> > Tested on a imx53-qsb board.
> >
> > Fixes: 21af872cd8c6 ("drm/msm/adreno: add a2xx")
> > Signed-off-by: Fabio Estevam
> > ---
> > Hi,
> >
> > This error has been exposed by a recent commit in linux-next:
> >
> > cc943f43ece7 ("drm/msm/adreno: warn if chip revn is verified before being
> > set")
> >
> > , but the error has been present since the very first a2xx commit.
> >
> > Changes since v2:
> > - Call adreno_gpu_init() earlier.
>
> Reviewed-by: Dmitry Baryshkov
>
>
> >
> > drivers/gpu/drm/msm/adreno/a2xx_gpu.c | 8
> > 1 file changed, 4 insertions(+), 4 deletions(-)
>
>
> --
> With best wishes
> Dmitry
>
Re: [PATCH v2] drm: bridge: samsung-dsim: Fix waiting for empty cmd transfer FIFO on older Exynos
On Fri, Jul 21, 2023 at 8:28 AM Marek Szyprowski
wrote:
>
> Samsung DSIM used in older Exynos SoCs (like Exynos 4210, 4x12, 3250)
> doesn't report empty level of packer header FIFO. In case of those SoCs,
> use the old way of waiting for empty command tranfsfer FIFO, removed
> recently by commit 14806c641582 ("Drain command transfer FIFO before
> transfer").
>
> Fixes: 14806c641582 ("Drain command transfer FIFO before transfer")
Nitpick: the Subject of the commit log is not complete.
Fixes: 14806c641582 ("drm: bridge: samsung-dsim: Drain command
transfer FIFO before transfer")
> Signed-off-by: Marek Szyprowski
> ---
> v2:
> - added additional delay when workaround is used as suggested by Marek Vasut
>
> v1:
> https://lore.kernel.org/all/20230718131859.3114135-1-m.szyprow...@samsung.com/
> ---
> drivers/gpu/drm/bridge/samsung-dsim.c | 18 --
> include/drm/bridge/samsung-dsim.h | 1 +
> 2 files changed, 17 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c
> b/drivers/gpu/drm/bridge/samsung-dsim.c
> index 9b7a00bafeaa..d06401de637c 100644
> --- a/drivers/gpu/drm/bridge/samsung-dsim.c
> +++ b/drivers/gpu/drm/bridge/samsung-dsim.c
> @@ -412,6 +412,7 @@ static const struct samsung_dsim_driver_data
> exynos3_dsi_driver_data = {
> .m_min = 41,
> .m_max = 125,
> .min_freq = 500,
> + .has_broken_fifoctrl_emptyhdr = 1,
> };
>
> static const struct samsung_dsim_driver_data exynos4_dsi_driver_data = {
> @@ -428,6 +429,7 @@ static const struct samsung_dsim_driver_data
> exynos4_dsi_driver_data = {
> .m_min = 41,
> .m_max = 125,
> .min_freq = 500,
> + .has_broken_fifoctrl_emptyhdr = 1,
> };
>
> static const struct samsung_dsim_driver_data exynos5_dsi_driver_data = {
> @@ -1009,8 +1011,20 @@ static int samsung_dsim_wait_for_hdr_fifo(struct
> samsung_dsim *dsi)
> do {
> u32 reg = samsung_dsim_read(dsi, DSIM_FIFOCTRL_REG);
>
> - if (reg & DSIM_SFR_HEADER_EMPTY)
> - return 0;
> + if (!dsi->driver_data->has_broken_fifoctrl_emptyhdr) {
> + if (reg & DSIM_SFR_HEADER_EMPTY)
> + return 0;
> + } else {
> + if (!(reg & DSIM_SFR_HEADER_FULL)) {
> + /*
> +* Wait a little bit, so the pending data can
> +* actually leave the FIFO to avoid overflow.
> +*/
> + if (!cond_resched())
> + usleep_range(950, 1050);
> + return 0;
> + }
> + }
>
> if (!cond_resched())
> usleep_range(950, 1050);
> diff --git a/include/drm/bridge/samsung-dsim.h
> b/include/drm/bridge/samsung-dsim.h
> index 05100e91ecb9..18017b3e5d9e 100644
> --- a/include/drm/bridge/samsung-dsim.h
> +++ b/include/drm/bridge/samsung-dsim.h
> @@ -62,6 +62,7 @@ struct samsung_dsim_driver_data {
> const unsigned int *reg_values;
> u16 m_min;
> u16 m_max;
> + unsigned int has_broken_fifoctrl_emptyhdr;
> };
>
> struct samsung_dsim_host_ops {
> --
> 2.34.1
>
Re: [PATCH] drm: adv7511: Fix low refresh rate register for ADV7533/5
On Wed, May 17, 2023 at 4:08 AM Alexandru Ardelean wrote: > > From: Bogdan Togorean > > For ADV7533 and ADV7535 low refresh rate is selected using > bits [3:2] of 0x4a main register. > So depending on ADV model write 0xfb or 0x4a register. > > Signed-off-by: Bogdan Togorean > Signed-off-by: Alexandru Ardelean Should this contain a Fixes tag so that it could be backported to stable kernels?
[PATCH v3] drm/msm/a2xx: Call adreno_gpu_init() earlier
From: Fabio Estevam
The adreno_is_a20x() and adreno_is_a225() functions rely on the
GPU revision, but such information is retrieved inside adreno_gpu_init(),
which is called afterwards.
Fix this problem by caling adreno_gpu_init() earlier, so that
the GPU information revision is available when adreno_is_a20x()
and adreno_is_a225() run.
Tested on a imx53-qsb board.
Fixes: 21af872cd8c6 ("drm/msm/adreno: add a2xx")
Signed-off-by: Fabio Estevam
---
Hi,
This error has been exposed by a recent commit in linux-next:
cc943f43ece7 ("drm/msm/adreno: warn if chip revn is verified before being set")
, but the error has been present since the very first a2xx commit.
Changes since v2:
- Call adreno_gpu_init() earlier.
drivers/gpu/drm/msm/adreno/a2xx_gpu.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a2xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a2xx_gpu.c
index c67089a7ebc1..ad4570d60abf 100644
--- a/drivers/gpu/drm/msm/adreno/a2xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a2xx_gpu.c
@@ -540,6 +540,10 @@ struct msm_gpu *a2xx_gpu_init(struct drm_device *dev)
gpu->perfcntrs = perfcntrs;
gpu->num_perfcntrs = ARRAY_SIZE(perfcntrs);
+ ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 1);
+ if (ret)
+ goto fail;
+
if (adreno_is_a20x(adreno_gpu))
adreno_gpu->registers = a200_registers;
else if (adreno_is_a225(adreno_gpu))
@@ -547,10 +551,6 @@ struct msm_gpu *a2xx_gpu_init(struct drm_device *dev)
else
adreno_gpu->registers = a220_registers;
- ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 1);
- if (ret)
- goto fail;
-
if (!gpu->aspace) {
dev_err(dev->dev, "No memory protection without MMU\n");
if (!allow_vram_carveout) {
--
2.34.1
Re: [PATCH 1/3] drm/msm/a3xx: Pass the revision information
On 20/06/2023 14:40, Dmitry Baryshkov wrote:
This looks like a boilerplate being added to all aYxx drivers (and
then these fields are also set in adreno_gpu_init()). Can we remove
duplication somehow?
Sorry, I missed this comment prior to sending v2.
Maybe a simpler fix for a2xx_gpu would be:
--- a/drivers/gpu/drm/msm/adreno/a2xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a2xx_gpu.c
@@ -540,6 +540,10 @@ struct msm_gpu *a2xx_gpu_init(struct drm_device
*dev)
gpu->perfcntrs = perfcntrs;
gpu->num_perfcntrs = ARRAY_SIZE(perfcntrs);
+ ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 1);
+ if (ret)
+ goto fail;
+
if (adreno_is_a20x(adreno_gpu))
adreno_gpu->registers = a200_registers;
else if (adreno_is_a225(adreno_gpu))
@@ -547,10 +551,6 @@ struct msm_gpu *a2xx_gpu_init(struct drm_device
*dev)
else
adreno_gpu->registers = a220_registers;
- ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 1);
- if (ret)
- goto fail;
-
if (!gpu->aspace) {
dev_err(dev->dev, "No memory protection without MMU\n");
if (!allow_vram_carveout) {
What do you think?
a3xx and a4xx call adreno_gpu_init() prior to adreno_is_xxx() so they
don't have issues.
[PATCH v2 4/4] drm/msm/a5xx: Pass the revision information
From: Fabio Estevam
Commit cc943f43ece7 ("drm/msm/adreno: warn if chip revn is verified
before being set") exposes the need of setting the GPU revision fields
prior to using the adreno_is_xxx() functions.
Pass the GPU revision information to avoid run-time warning.
Signed-off-by: Fabio Estevam
---
Build-tested only.
Changes since v1:
- None
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
index a99310b68793..b4c1720ba89c 100644
--- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
@@ -1744,6 +1744,7 @@ struct msm_gpu *a5xx_gpu_init(struct drm_device *dev)
struct msm_drm_private *priv = dev->dev_private;
struct platform_device *pdev = priv->gpu_pdev;
struct adreno_platform_config *config = pdev->dev.platform_data;
+ const struct adreno_info *info;
struct a5xx_gpu *a5xx_gpu = NULL;
struct adreno_gpu *adreno_gpu;
struct msm_gpu *gpu;
@@ -1770,6 +1771,23 @@ struct msm_gpu *a5xx_gpu_init(struct drm_device *dev)
nr_rings = 4;
+ /*
+* We need to know the platform type before calling into adreno_gpu_init
+* so that the hw_apriv flag can be correctly set. Snoop into the info
+* and grab the revision number
+*/
+ info = adreno_info(config->rev);
+ if (!info)
+ return ERR_PTR(-EINVAL);
+
+ /* Assign these early so that we can use the is_aXYZ helpers */
+ /* Numeric revision IDs (e.g. 630) */
+ adreno_gpu->revn = info->revn;
+ /* New-style ADRENO_REV()-only */
+ adreno_gpu->rev = info->rev;
+ /* Quirk data */
+ adreno_gpu->info = info;
+
if (adreno_cmp_rev(ADRENO_REV(5, 1, 0, ANY_ID), config->rev))
nr_rings = 1;
--
2.34.1
[PATCH v2 2/4] drm/msm/a3xx: Pass the revision information
From: Fabio Estevam
Commit cc943f43ece7 ("drm/msm/adreno: warn if chip revn is verified
before being set") exposes the need of setting the GPU revision fields
prior to using the adreno_is_xxx() functions.
Pass the GPU revision information to avoid run-time warning.
Signed-off-by: Fabio Estevam
---
Build-tested only.
Changes since v1:
- None
drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
index c86b377f6f0d..fc23810d7684 100644
--- a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
@@ -530,6 +530,8 @@ struct msm_gpu *a3xx_gpu_init(struct drm_device *dev)
struct msm_gpu *gpu;
struct msm_drm_private *priv = dev->dev_private;
struct platform_device *pdev = priv->gpu_pdev;
+ struct adreno_platform_config *config = pdev->dev.platform_data;
+ const struct adreno_info *info;
struct icc_path *ocmem_icc_path;
struct icc_path *icc_path;
int ret;
@@ -558,6 +560,25 @@ struct msm_gpu *a3xx_gpu_init(struct drm_device *dev)
if (ret)
goto fail;
+ /*
+* We need to know the platform type before calling into adreno_gpu_init
+* so that the hw_apriv flag can be correctly set. Snoop into the info
+* and grab the revision number
+*/
+ info = adreno_info(config->rev);
+ if (!info) {
+ ret = -EINVAL;
+ goto fail;
+ }
+
+ /* Assign these early so that we can use the is_aXYZ helpers */
+ /* Numeric revision IDs (e.g. 630) */
+ adreno_gpu->revn = info->revn;
+ /* New-style ADRENO_REV()-only */
+ adreno_gpu->rev = info->rev;
+ /* Quirk data */
+ adreno_gpu->info = info;
+
/* if needed, allocate gmem: */
if (adreno_is_a330(adreno_gpu)) {
ret = adreno_gpu_ocmem_init(&adreno_gpu->base.pdev->dev,
--
2.34.1
[PATCH v2 3/4] drm/msm/a4xx: Pass the revision information
From: Fabio Estevam
Commit cc943f43ece7 ("drm/msm/adreno: warn if chip revn is verified
before being set") exposes the need of setting the GPU revision fields
prior to using the adreno_is_xxx() functions.
Pass the GPU revision information to avoid run-time warning.
Signed-off-by: Fabio Estevam
---
Build-tested only.
Changes since v1:
- None
drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
index 715436cb3996..2ae072b4e79d 100644
--- a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
@@ -658,6 +658,8 @@ struct msm_gpu *a4xx_gpu_init(struct drm_device *dev)
struct msm_gpu *gpu;
struct msm_drm_private *priv = dev->dev_private;
struct platform_device *pdev = priv->gpu_pdev;
+ struct adreno_platform_config *config = pdev->dev.platform_data;
+ const struct adreno_info *info;
struct icc_path *ocmem_icc_path;
struct icc_path *icc_path;
int ret;
@@ -684,6 +686,25 @@ struct msm_gpu *a4xx_gpu_init(struct drm_device *dev)
if (ret)
goto fail;
+ /*
+* We need to know the platform type before calling into adreno_gpu_init
+* so that the hw_apriv flag can be correctly set. Snoop into the info
+* and grab the revision number
+*/
+ info = adreno_info(config->rev);
+ if (!info) {
+ ret = -EINVAL;
+ goto fail;
+ }
+
+ /* Assign these early so that we can use the is_aXYZ helpers */
+ /* Numeric revision IDs (e.g. 630) */
+ adreno_gpu->revn = info->revn;
+ /* New-style ADRENO_REV()-only */
+ adreno_gpu->rev = info->rev;
+ /* Quirk data */
+ adreno_gpu->info = info;
+
adreno_gpu->registers = adreno_is_a405(adreno_gpu) ? a405_registers :
a4xx_registers;
--
2.34.1
[PATCH v2 1/4] drm/msm/a2xx: Pass the revision information
From: Fabio Estevam
Commit cc943f43ece7 ("drm/msm/adreno: warn if chip revn is verified
before being set") exposes the need of setting the GPU revision fields
prior to using the adreno_is_xxx() functions:
[ cut here ]
WARNING: CPU: 0 PID: 1 at drivers/gpu/drm/msm/adreno/adreno_gpu.h:171
a2xx_gpu_init+0x138/0x184
Modules linked in:
CPU: 0 PID: 1 Comm: swapper/0 Not tainted 6.4.0-rc7-next-20230620 #993
Pass the GPU revision information to avoid run-time warning.
Tested on a imx53-qsb board.
Signed-off-by: Fabio Estevam
---
Changes since v1:
- Make it part of a single patch series.
drivers/gpu/drm/msm/adreno/a2xx_gpu.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/drivers/gpu/drm/msm/adreno/a2xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a2xx_gpu.c
index c67089a7ebc1..4e1218462a23 100644
--- a/drivers/gpu/drm/msm/adreno/a2xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a2xx_gpu.c
@@ -520,6 +520,8 @@ struct msm_gpu *a2xx_gpu_init(struct drm_device *dev)
struct msm_gpu *gpu;
struct msm_drm_private *priv = dev->dev_private;
struct platform_device *pdev = priv->gpu_pdev;
+ struct adreno_platform_config *config = pdev->dev.platform_data;
+ const struct adreno_info *info;
int ret;
if (!pdev) {
@@ -540,6 +542,23 @@ struct msm_gpu *a2xx_gpu_init(struct drm_device *dev)
gpu->perfcntrs = perfcntrs;
gpu->num_perfcntrs = ARRAY_SIZE(perfcntrs);
+ /*
+* We need to know the platform type before calling into adreno_gpu_init
+* so that the hw_apriv flag can be correctly set. Snoop into the info
+* and grab the revision number
+*/
+ info = adreno_info(config->rev);
+ if (!info)
+ return ERR_PTR(-EINVAL);
+
+ /* Assign these early so that we can use the is_aXYZ helpers */
+ /* Numeric revision IDs (e.g. 630) */
+ adreno_gpu->revn = info->revn;
+ /* New-style ADRENO_REV()-only */
+ adreno_gpu->rev = info->rev;
+ /* Quirk data */
+ adreno_gpu->info = info;
+
if (adreno_is_a20x(adreno_gpu))
adreno_gpu->registers = a200_registers;
else if (adreno_is_a225(adreno_gpu))
--
2.34.1
[PATCH 3/3] drm/msm/a5xx: Pass the revision information
From: Fabio Estevam
Commit cc943f43ece7 ("drm/msm/adreno: warn if chip revn is verified
before being set") exposes the need of setting the GPU revision fields
prior to using the adreno_is_xxx() functions.
Pass the GPU revision information to avoid run-time warning.
Signed-off-by: Fabio Estevam
---
Build-tested only.
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
index a99310b68793..b4c1720ba89c 100644
--- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
@@ -1744,6 +1744,7 @@ struct msm_gpu *a5xx_gpu_init(struct drm_device *dev)
struct msm_drm_private *priv = dev->dev_private;
struct platform_device *pdev = priv->gpu_pdev;
struct adreno_platform_config *config = pdev->dev.platform_data;
+ const struct adreno_info *info;
struct a5xx_gpu *a5xx_gpu = NULL;
struct adreno_gpu *adreno_gpu;
struct msm_gpu *gpu;
@@ -1770,6 +1771,23 @@ struct msm_gpu *a5xx_gpu_init(struct drm_device *dev)
nr_rings = 4;
+ /*
+* We need to know the platform type before calling into adreno_gpu_init
+* so that the hw_apriv flag can be correctly set. Snoop into the info
+* and grab the revision number
+*/
+ info = adreno_info(config->rev);
+ if (!info)
+ return ERR_PTR(-EINVAL);
+
+ /* Assign these early so that we can use the is_aXYZ helpers */
+ /* Numeric revision IDs (e.g. 630) */
+ adreno_gpu->revn = info->revn;
+ /* New-style ADRENO_REV()-only */
+ adreno_gpu->rev = info->rev;
+ /* Quirk data */
+ adreno_gpu->info = info;
+
if (adreno_cmp_rev(ADRENO_REV(5, 1, 0, ANY_ID), config->rev))
nr_rings = 1;
--
2.34.1
[PATCH 2/3] drm/msm/43xx: Pass the revision information
From: Fabio Estevam
Commit cc943f43ece7 ("drm/msm/adreno: warn if chip revn is verified
before being set") exposes the need of setting the GPU revision fields
prior to using the adreno_is_xxx() functions.
Pass the GPU revision information to avoid run-time warning.
Signed-off-by: Fabio Estevam
---
Build-tested only.
drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
index 715436cb3996..2ae072b4e79d 100644
--- a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
@@ -658,6 +658,8 @@ struct msm_gpu *a4xx_gpu_init(struct drm_device *dev)
struct msm_gpu *gpu;
struct msm_drm_private *priv = dev->dev_private;
struct platform_device *pdev = priv->gpu_pdev;
+ struct adreno_platform_config *config = pdev->dev.platform_data;
+ const struct adreno_info *info;
struct icc_path *ocmem_icc_path;
struct icc_path *icc_path;
int ret;
@@ -684,6 +686,25 @@ struct msm_gpu *a4xx_gpu_init(struct drm_device *dev)
if (ret)
goto fail;
+ /*
+* We need to know the platform type before calling into adreno_gpu_init
+* so that the hw_apriv flag can be correctly set. Snoop into the info
+* and grab the revision number
+*/
+ info = adreno_info(config->rev);
+ if (!info) {
+ ret = -EINVAL;
+ goto fail;
+ }
+
+ /* Assign these early so that we can use the is_aXYZ helpers */
+ /* Numeric revision IDs (e.g. 630) */
+ adreno_gpu->revn = info->revn;
+ /* New-style ADRENO_REV()-only */
+ adreno_gpu->rev = info->rev;
+ /* Quirk data */
+ adreno_gpu->info = info;
+
adreno_gpu->registers = adreno_is_a405(adreno_gpu) ? a405_registers :
a4xx_registers;
--
2.34.1
[PATCH 1/3] drm/msm/a3xx: Pass the revision information
From: Fabio Estevam
Commit cc943f43ece7 ("drm/msm/adreno: warn if chip revn is verified
before being set") exposes the need of setting the GPU revision fields
prior to using the adreno_is_xxx() functions.
Pass the GPU revision information to avoid run-time warning.
Signed-off-by: Fabio Estevam
---
Build-tested only.
drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
index c86b377f6f0d..fc23810d7684 100644
--- a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
@@ -530,6 +530,8 @@ struct msm_gpu *a3xx_gpu_init(struct drm_device *dev)
struct msm_gpu *gpu;
struct msm_drm_private *priv = dev->dev_private;
struct platform_device *pdev = priv->gpu_pdev;
+ struct adreno_platform_config *config = pdev->dev.platform_data;
+ const struct adreno_info *info;
struct icc_path *ocmem_icc_path;
struct icc_path *icc_path;
int ret;
@@ -558,6 +560,25 @@ struct msm_gpu *a3xx_gpu_init(struct drm_device *dev)
if (ret)
goto fail;
+ /*
+* We need to know the platform type before calling into adreno_gpu_init
+* so that the hw_apriv flag can be correctly set. Snoop into the info
+* and grab the revision number
+*/
+ info = adreno_info(config->rev);
+ if (!info) {
+ ret = -EINVAL;
+ goto fail;
+ }
+
+ /* Assign these early so that we can use the is_aXYZ helpers */
+ /* Numeric revision IDs (e.g. 630) */
+ adreno_gpu->revn = info->revn;
+ /* New-style ADRENO_REV()-only */
+ adreno_gpu->rev = info->rev;
+ /* Quirk data */
+ adreno_gpu->info = info;
+
/* if needed, allocate gmem: */
if (adreno_is_a330(adreno_gpu)) {
ret = adreno_gpu_ocmem_init(&adreno_gpu->base.pdev->dev,
--
2.34.1
[PATCH] drm/msm/a2xx: Pass the revision information
From: Fabio Estevam
Since commit cc943f43ece7 ("drm/msm/adreno: warn if chip revn is verified
before being set") the following run-time warning is observed:
[ cut here ]
WARNING: CPU: 0 PID: 1 at drivers/gpu/drm/msm/adreno/adreno_gpu.h:171
a2xx_gpu_init+0x138/0x184
Modules linked in:
CPU: 0 PID: 1 Comm: swapper/0 Not tainted 6.4.0-rc7-next-20230620 #993
Fix the problem by assigning the GPU revision fields like it is
done in a6xx_gpu.
Fixes: cc943f43ece7 ("drm/msm/adreno: warn if chip revn is verified before
being set")
Signed-off-by: Fabio Estevam
---
drivers/gpu/drm/msm/adreno/a2xx_gpu.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/drivers/gpu/drm/msm/adreno/a2xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a2xx_gpu.c
index c67089a7ebc1..4e1218462a23 100644
--- a/drivers/gpu/drm/msm/adreno/a2xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a2xx_gpu.c
@@ -520,6 +520,8 @@ struct msm_gpu *a2xx_gpu_init(struct drm_device *dev)
struct msm_gpu *gpu;
struct msm_drm_private *priv = dev->dev_private;
struct platform_device *pdev = priv->gpu_pdev;
+ struct adreno_platform_config *config = pdev->dev.platform_data;
+ const struct adreno_info *info;
int ret;
if (!pdev) {
@@ -540,6 +542,23 @@ struct msm_gpu *a2xx_gpu_init(struct drm_device *dev)
gpu->perfcntrs = perfcntrs;
gpu->num_perfcntrs = ARRAY_SIZE(perfcntrs);
+ /*
+* We need to know the platform type before calling into adreno_gpu_init
+* so that the hw_apriv flag can be correctly set. Snoop into the info
+* and grab the revision number
+*/
+ info = adreno_info(config->rev);
+ if (!info)
+ return ERR_PTR(-EINVAL);
+
+ /* Assign these early so that we can use the is_aXYZ helpers */
+ /* Numeric revision IDs (e.g. 630) */
+ adreno_gpu->revn = info->revn;
+ /* New-style ADRENO_REV()-only */
+ adreno_gpu->rev = info->rev;
+ /* Quirk data */
+ adreno_gpu->info = info;
+
if (adreno_is_a20x(adreno_gpu))
adreno_gpu->registers = a200_registers;
else if (adreno_is_a225(adreno_gpu))
--
2.34.1
[PATCH v2] drm/panel: simple: Add connector_type for innolux_at043tn24
From: Fabio Estevam
The innolux at043tn24 display is a parallel LCD. Pass the 'connector_type'
information to avoid the following warning:
panel-simple panel: Specify missing connector_type
Signed-off-by: Fabio Estevam
Fixes: 41bcceb4de9c ("drm/panel: simple: Add support for Innolux AT043TN24")
---
Changes since v1:
- Pass Fixes tag (Neil).
drivers/gpu/drm/panel/panel-simple.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/panel/panel-simple.c
b/drivers/gpu/drm/panel/panel-simple.c
index a247a0e7c799..7c80528d571e 100644
--- a/drivers/gpu/drm/panel/panel-simple.c
+++ b/drivers/gpu/drm/panel/panel-simple.c
@@ -2178,6 +2178,7 @@ static const struct panel_desc innolux_at043tn24 = {
.height = 54,
},
.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
+ .connector_type = DRM_MODE_CONNECTOR_DPI,
.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
};
--
2.34.1
[PATCH] drm/panel: simple: Add connector_type for innolux_at043tn24
From: Fabio Estevam
The innolux at043tn24 display is a parallel LCD. Pass the 'connector_type'
information to avoid the following warning:
panel-simple panel: Specify missing connector_type
Signed-off-by: Fabio Estevam
---
drivers/gpu/drm/panel/panel-simple.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/panel/panel-simple.c
b/drivers/gpu/drm/panel/panel-simple.c
index a247a0e7c799..7c80528d571e 100644
--- a/drivers/gpu/drm/panel/panel-simple.c
+++ b/drivers/gpu/drm/panel/panel-simple.c
@@ -2178,6 +2178,7 @@ static const struct panel_desc innolux_at043tn24 = {
.height = 54,
},
.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
+ .connector_type = DRM_MODE_CONNECTOR_DPI,
.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
};
--
2.34.1
[PATCH v2] dt-bindings: samsung,mipi-dsim: Use port-base reference
From: Fabio Estevam
Use port-base reference for port@1.
This fixes the following schema warning:
imx8mp-dhcom-pdk3.dtb: dsi@32e6: ports:port@1:endpoint: Unevaluated
properties are not allowed ('data-lanes' was unexpected)
>From schema:
>Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml
Fixes: 1f0d40d88f7a ("dt-bindings: bridge: Convert Samsung MIPI DSIM bridge to
yaml")
Signed-off-by: Fabio Estevam
---
Changes since v1:
- Only changed port@1.
- Used Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml as
reference. (Thanks Marek for the suggestion!)
To reproduce the original problem against linux-next 20230531:
- Enable the mipi_dsi node on imx8mp-dhcom-som.dtsi
&mipi_dsi {
samsung,burst-clock-frequency = <16000>;
samsung,esc-clock-frequency = <1000>;
+ status = "okay";
ports {
port@1 {
$ make CHECK_DTBS=y DT_SCHEMA_FILES=samsung,mipi-dsim.yaml
freescale/imx8mp-dhcom-pdk3.dtb
UPD include/config/kernel.release
LINTDocumentation/devicetree/bindings
CHKDT Documentation/devicetree/bindings/processed-schema.json
SCHEMA Documentation/devicetree/bindings/processed-schema.json
DTC_CHK arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3.dtb
arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3.dtb: dsi@32e6:
ports:port@1:endpoint: Unevaluated properties are not allowed ('data-lanes' was
unexpected)
>From schema:
>Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml
.../devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
a/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml
b/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml
index 06b6c44d4641..4ed7a799ba26 100644
--- a/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml
+++ b/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml
@@ -103,7 +103,8 @@ properties:
specified.
port@1:
-$ref: /schemas/graph.yaml#/properties/port
+$ref: /schemas/graph.yaml#/$defs/port-base
+unevaluatedProperties: false
description:
DSI output port node to the panel or the next bridge
in the chain.
--
2.34.1
Re: [PATCH] dt-bindings: samsung,mipi-dsim: Use port-base reference
On 31/05/2023 15:56, Krzysztof Kozlowski wrote: This would have sense if you kept original intention, so additionalProperties: false Without it - you just break bindings to hide warning. I am not sure I understood your suggestion. Is this what you mean? diff --git a/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml b/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml index 06b6c44d4641..033404669b11 100644 --- a/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml +++ b/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml @@ -96,14 +96,14 @@ properties: properties: port@0: -$ref: /schemas/graph.yaml#/properties/port +$ref: /schemas/graph.yaml#/$defs/port-base description: Input port node to receive pixel data from the display controller. Exactly one endpoint must be specified. port@1: -$ref: /schemas/graph.yaml#/properties/port +$ref: /schemas/graph.yaml#/$defs/port-base description: DSI output port node to the panel or the next bridge in the chain. @@ -230,8 +230,7 @@ allOf: - vddio-supply - samsung,phy-type -additionalProperties: - type: object +additionalProperties: false examples: - | --
[PATCH] dt-bindings: samsung,mipi-dsim: Use port-base reference
From: Fabio Estevam
Use port-base reference for port@0 and port@1.
This fixes the following schema warning:
imx8mm-evk.dtb: dsi@32e1: ports:port@1:endpoint: Unevaluated properties are
not allowed ('data-lanes' was unexpected)
>From schema:
>Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml
Fixes: 1f0d40d88f7a ("dt-bindings: bridge: Convert Samsung MIPI DSIM bridge to
yaml")
Signed-off-by: Fabio Estevam
---
.../devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
a/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml
b/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml
index 9f61ebdfefa8..51879030dd6d 100644
--- a/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml
+++ b/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml
@@ -93,14 +93,14 @@ properties:
properties:
port@0:
-$ref: /schemas/graph.yaml#/properties/port
+$ref: /schemas/graph.yaml#/$defs/port-base
description:
Input port node to receive pixel data from the
display controller. Exactly one endpoint must be
specified.
port@1:
-$ref: /schemas/graph.yaml#/properties/port
+$ref: /schemas/graph.yaml#/$defs/port-base
description:
DSI output port node to the panel or the next bridge
in the chain.
--
2.34.1
Re: [PATCH V2] dt-bindings: bridge: samsung-dsim: Make some flags optional
On Sun, May 28, 2023 at 10:27 AM Adam Ford wrote: > > In the event a device is connected to the samsung-dsim > controller that doesn't support the burst-clock, the > driver is able to get the requested pixel clock from the > attached device or bridge. In these instances, the > samsung,burst-clock-frequency isn't needed, so remove > it from the required list. > > The pll-clock frequency can be set by the device tree entry > for samsung,pll-clock-frequency, but in some cases, the > pll-clock may have the same clock rate as sclk_mipi clock. > If they are equal, this flag is not needed since the driver > will use the sclk_mipi rate as a fallback. > > Signed-off-by: Adam Ford > Reviewed-by: Conor Dooley > --- > V2: Split from driver series. Re-word updates for burst > and pll-clock frequency. Reviewed-by: Fabio Estevam
Re: [PATCH V7 0/6] drm: bridge: samsung-dsim: Support variable clocking
Hi Adam, On Tue, May 23, 2023 at 8:49 PM Adam Ford wrote: > Inki, > > I haven't heard back from you on whether or not you want the bindings > patch to be included with me resending the series as V7 or if you're > OK with a single, stand-alone patch. > Will you let me know? I have the patch standing by waiting for > instructions. If you're not the right person to ask, please let me > know who the right person is. Neil has also been collecting samsung-dsim patches. Maybe he can clarify.
Re: [PATCH v4 1/2] dt-bindings: samsung, mipi-dsim: Add 'lane-polarities'
Hi Neil, On Sun, May 14, 2023 at 9:29 AM Krzysztof Kozlowski wrote: > > On 14/05/2023 13:46, Fabio Estevam wrote: > > From: Fabio Estevam > > > > The Samsung DSIM IP block allows the inversion of the clock and > > data lanes. > > > > Add an optional property called 'lane-polarities' that describes the > > polarities of the MIPI DSI clock and data lanes. > > > Reviewed-by: Krzysztof Kozlowski Could you please apply this series? Thanks
Re: [PATCH V7 0/6] drm: bridge: samsung-dsim: Support variable clocking
Hi Adam, On Thu, May 18, 2023 at 8:06 PM Adam Ford wrote: > > This series fixes the blanking pack size and the PMS calculation. It then > adds support to allows the DSIM to dynamically DPHY clocks, and support > non-burst mode while allowing the removal of the hard-coded clock values > for the PLL for imx8m mini/nano/plus, and it allows the removal of the > burst-clock device tree entry when burst-mode isn't supported by connected > devices like an HDMI brige. In that event, the HS clock is set to the > value requested by the bridge chip. > > This has been tested on both an i.MX8M Nano and i.MX8M Plus, and should > work on i.MX8M Mini as well. Marek Szyprowski has tested it on various > Exynos boards. > > Adam Ford (5): > drm: bridge: samsung-dsim: Fix PMS Calculator on imx8m[mnp] > drm: bridge: samsung-dsim: Fetch pll-clock-frequency automatically > drm: bridge: samsung-dsim: Select GENERIC_PHY_MIPI_DPHY > drm: bridge: samsung-dsim: Dynamically configure DPHY timing > drm: bridge: samsung-dsim: Support non-burst mode > > Lucas Stach (1): > drm: bridge: samsung-dsim: fix blanking packet size calculation > > drivers/gpu/drm/bridge/Kconfig| 1 + > drivers/gpu/drm/bridge/samsung-dsim.c | 142 +- > include/drm/bridge/samsung-dsim.h | 4 + > 3 files changed, 124 insertions(+), 23 deletions(-) > > V7: Move messages indicating the optional device tree items are going > to be automatically read elsewhere was move to dev_dbg instead of > dev_info. Cleaned up some of the comments to be a bit more clear. > Eliminated a double variable assignement accidentally introduced > in V6 when some of the items were moved from patch 6 to patch 5. It seems you missed addressing one previous comment from Lucas: "Same as with the earlier patch, this needs to be documented in the DT binding by moving "samsung,burst-clock-frequency" to be a optional property."
Re: [PATCH v2 2/2] drm/bridge: ti-sn65dsi83: Fix enable/disable flow to meet spec
On Thu, May 4, 2023 at 6:12 AM Alexander Stein wrote: > > Am Mittwoch, 3. Mai 2023, 18:33:07 CEST schrieb Frieder Schrempf: > > From: Frieder Schrempf > > > > The datasheet describes the following initialization flow including > > minimum delay times between each step: > > > > 1. DSI data lanes need to be in LP-11 and the clock lane in HS mode > > 2. toggle EN signal > > 3. initialize registers > > 4. enable PLL > > 5. soft reset > > 6. enable DSI stream > > 7. check error status register > > > > To meet this requirement we need to make sure the host bridge's > > pre_enable() is called first by using the pre_enable_prev_first > > flag. > > > > Furthermore we need to split enable() into pre_enable() which covers > > steps 2-5 from above and enable() which covers step 7 and is called > > after the host bridge's enable(). > > > > Signed-off-by: Frieder Schrempf > > Tested-by: Alexander Stein #TQMa8MxML/MBa8Mx Should this have a Fixes tag so that it could be backported to stable kernels?
[PATCH v4 2/2] drm: bridge: samsung-dsim: Implement support for clock/data polarity swap
From: Marek Vasut
Implement support for DSI clock and data lane DN/DP polarity swap by
means of decoding 'lane-polarities' DT property. The controller does
support DN/DP swap of clock lane and all data lanes, the controller
does not support polarity swap of individual data lane bundles, add
a check which verifies all data lanes have the same polarity.
This has been validated on an imx8mm board that actually has the MIPI DSI
clock lanes inverted.
Signed-off-by: Marek Vasut
Signed-off-by: Fabio Estevam
Reviewed-by: Jagan Teki
---
Changes since v3:
- None
drivers/gpu/drm/bridge/samsung-dsim.c | 27 ++-
include/drm/bridge/samsung-dsim.h | 2 ++
2 files changed, 28 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c
b/drivers/gpu/drm/bridge/samsung-dsim.c
index e0a402a85787..5791148e2da2 100644
--- a/drivers/gpu/drm/bridge/samsung-dsim.c
+++ b/drivers/gpu/drm/bridge/samsung-dsim.c
@@ -183,6 +183,8 @@
#define DSIM_AFC_CTL(x)(((x) & 0x7) << 5)
/* DSIM_PLLCTRL */
+#define DSIM_PLL_DPDNSWAP_CLK (1 << 25)
+#define DSIM_PLL_DPDNSWAP_DAT (1 << 24)
#define DSIM_FREQ_BAND(x) ((x) << 24)
#define DSIM_PLL_ENBIT(23)
#define DSIM_PLL_P(x, offset) ((x) << (offset))
@@ -622,6 +624,11 @@ static unsigned long samsung_dsim_set_pll(struct
samsung_dsim *dsi,
reg |= DSIM_FREQ_BAND(band);
}
+ if (dsi->swap_dn_dp_clk)
+ reg |= DSIM_PLL_DPDNSWAP_CLK;
+ if (dsi->swap_dn_dp_data)
+ reg |= DSIM_PLL_DPDNSWAP_DAT;
+
samsung_dsim_write(dsi, DSIM_PLLCTRL_REG, reg);
timeout = 1000;
@@ -1696,7 +1703,9 @@ static int samsung_dsim_parse_dt(struct samsung_dsim *dsi)
{
struct device *dev = dsi->dev;
struct device_node *node = dev->of_node;
- int ret;
+ u32 lane_polarities[5] = { 0 };
+ struct device_node *endpoint;
+ int i, nr_lanes, ret;
ret = samsung_dsim_of_read_u32(node, "samsung,pll-clock-frequency",
&dsi->pll_clk_rate);
@@ -1713,6 +1722,22 @@ static int samsung_dsim_parse_dt(struct samsung_dsim
*dsi)
if (ret < 0)
return ret;
+ endpoint = of_graph_get_endpoint_by_regs(node, 1, -1);
+ nr_lanes = of_property_count_u32_elems(endpoint, "data-lanes");
+ if (nr_lanes > 0 && nr_lanes <= 4) {
+ /* Polarity 0 is clock lane, 1..4 are data lanes. */
+ of_property_read_u32_array(endpoint, "lane-polarities",
+ lane_polarities, nr_lanes + 1);
+ for (i = 1; i <= nr_lanes; i++) {
+ if (lane_polarities[1] != lane_polarities[i])
+ DRM_DEV_ERROR(dsi->dev, "Data lanes polarities
do not match");
+ }
+ if (lane_polarities[0])
+ dsi->swap_dn_dp_clk = true;
+ if (lane_polarities[1])
+ dsi->swap_dn_dp_data = true;
+ }
+
return 0;
}
diff --git a/include/drm/bridge/samsung-dsim.h
b/include/drm/bridge/samsung-dsim.h
index ba5484de2b30..6a37d1e079bf 100644
--- a/include/drm/bridge/samsung-dsim.h
+++ b/include/drm/bridge/samsung-dsim.h
@@ -95,6 +95,8 @@ struct samsung_dsim {
u32 mode_flags;
u32 format;
+ bool swap_dn_dp_clk;
+ bool swap_dn_dp_data;
int state;
struct drm_property *brightness;
struct completion completed;
--
2.34.1
[PATCH v4 1/2] dt-bindings: samsung,mipi-dsim: Add 'lane-polarities'
From: Fabio Estevam The Samsung DSIM IP block allows the inversion of the clock and data lanes. Add an optional property called 'lane-polarities' that describes the polarities of the MIPI DSI clock and data lanes. This property is useful for properly describing the hardware when the board designer decided to switch the polarities of the MIPI DSI clock and/or data lanes. Signed-off-by: Fabio Estevam --- Changes since v3: - Dropped oneOf, no need for it. (Krzysztof) - Dropped description as it is obvious. (Krzysztof) - Dropped items, as it is already in video-interfaces. (Krzysztof) - Dropped "See ../../media/video-interfaces.yaml". (Krzysztof) .../display/bridge/samsung,mipi-dsim.yaml | 23 +++ 1 file changed, 23 insertions(+) diff --git a/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml b/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml index e841659e20cd..9f61ebdfefa8 100644 --- a/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml +++ b/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml @@ -105,6 +105,29 @@ properties: DSI output port node to the panel or the next bridge in the chain. +properties: + endpoint: +$ref: /schemas/media/video-interfaces.yaml# +unevaluatedProperties: false + +properties: + data-lanes: +minItems: 1 +maxItems: 4 +uniqueItems: true +items: + enum: [ 1, 2, 3, 4 ] + + lane-polarities: +minItems: 1 +maxItems: 5 +description: + The Samsung MIPI DSI IP requires that all the data lanes have + the same polarity. + +dependencies: + lane-polarities: [data-lanes] + required: - clock-names - clocks -- 2.34.1
[PATCH v3 2/2] drm: bridge: samsung-dsim: Implement support for clock/data polarity swap
From: Marek Vasut
Implement support for DSI clock and data lane DN/DP polarity swap by
means of decoding 'lane-polarities' DT property. The controller does
support DN/DP swap of clock lane and all data lanes, the controller
does not support polarity swap of individual data lane bundles, add
a check which verifies all data lanes have the same polarity.
This has been validated on an imx8mm board that actually has the MIPI DSI
clock lanes inverted.
Signed-off-by: Marek Vasut
Signed-off-by: Fabio Estevam
Reviewed-by: Jagan Teki
---
Changes since v2:
- None
drivers/gpu/drm/bridge/samsung-dsim.c | 27 ++-
include/drm/bridge/samsung-dsim.h | 2 ++
2 files changed, 28 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c
b/drivers/gpu/drm/bridge/samsung-dsim.c
index e0a402a85787..5791148e2da2 100644
--- a/drivers/gpu/drm/bridge/samsung-dsim.c
+++ b/drivers/gpu/drm/bridge/samsung-dsim.c
@@ -183,6 +183,8 @@
#define DSIM_AFC_CTL(x)(((x) & 0x7) << 5)
/* DSIM_PLLCTRL */
+#define DSIM_PLL_DPDNSWAP_CLK (1 << 25)
+#define DSIM_PLL_DPDNSWAP_DAT (1 << 24)
#define DSIM_FREQ_BAND(x) ((x) << 24)
#define DSIM_PLL_ENBIT(23)
#define DSIM_PLL_P(x, offset) ((x) << (offset))
@@ -622,6 +624,11 @@ static unsigned long samsung_dsim_set_pll(struct
samsung_dsim *dsi,
reg |= DSIM_FREQ_BAND(band);
}
+ if (dsi->swap_dn_dp_clk)
+ reg |= DSIM_PLL_DPDNSWAP_CLK;
+ if (dsi->swap_dn_dp_data)
+ reg |= DSIM_PLL_DPDNSWAP_DAT;
+
samsung_dsim_write(dsi, DSIM_PLLCTRL_REG, reg);
timeout = 1000;
@@ -1696,7 +1703,9 @@ static int samsung_dsim_parse_dt(struct samsung_dsim *dsi)
{
struct device *dev = dsi->dev;
struct device_node *node = dev->of_node;
- int ret;
+ u32 lane_polarities[5] = { 0 };
+ struct device_node *endpoint;
+ int i, nr_lanes, ret;
ret = samsung_dsim_of_read_u32(node, "samsung,pll-clock-frequency",
&dsi->pll_clk_rate);
@@ -1713,6 +1722,22 @@ static int samsung_dsim_parse_dt(struct samsung_dsim
*dsi)
if (ret < 0)
return ret;
+ endpoint = of_graph_get_endpoint_by_regs(node, 1, -1);
+ nr_lanes = of_property_count_u32_elems(endpoint, "data-lanes");
+ if (nr_lanes > 0 && nr_lanes <= 4) {
+ /* Polarity 0 is clock lane, 1..4 are data lanes. */
+ of_property_read_u32_array(endpoint, "lane-polarities",
+ lane_polarities, nr_lanes + 1);
+ for (i = 1; i <= nr_lanes; i++) {
+ if (lane_polarities[1] != lane_polarities[i])
+ DRM_DEV_ERROR(dsi->dev, "Data lanes polarities
do not match");
+ }
+ if (lane_polarities[0])
+ dsi->swap_dn_dp_clk = true;
+ if (lane_polarities[1])
+ dsi->swap_dn_dp_data = true;
+ }
+
return 0;
}
diff --git a/include/drm/bridge/samsung-dsim.h
b/include/drm/bridge/samsung-dsim.h
index ba5484de2b30..6a37d1e079bf 100644
--- a/include/drm/bridge/samsung-dsim.h
+++ b/include/drm/bridge/samsung-dsim.h
@@ -95,6 +95,8 @@ struct samsung_dsim {
u32 mode_flags;
u32 format;
+ bool swap_dn_dp_clk;
+ bool swap_dn_dp_data;
int state;
struct drm_property *brightness;
struct completion completed;
--
2.34.1
[PATCH v3 1/2] dt-bindings: samsung,mipi-dsim: Add 'lane-polarities'
From: Fabio Estevam The Samsung DSIM IP block allows the inversion of the clock and data lanes. Add an optional property called 'lane-polarities' that describes the polarities of the MIPI DSI clock and data lanes. This property is useful for properly describing the hardware when the board designer decided to switch the polarities of the MIPI DSI clock and/or data lanes. Signed-off-by: Fabio Estevam --- Changes since v2: - Use video-interfaces.yaml (Rob). .../display/bridge/samsung,mipi-dsim.yaml | 29 +++ 1 file changed, 29 insertions(+) diff --git a/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml b/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml index e841659e20cd..dad6d06fbdd9 100644 --- a/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml +++ b/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml @@ -105,6 +105,35 @@ properties: DSI output port node to the panel or the next bridge in the chain. +properties: + endpoint: +$ref: /schemas/media/video-interfaces.yaml# +unevaluatedProperties: false + +properties: + data-lanes: +oneOf: + - minItems: 1 +maxItems: 4 +uniqueItems: true +items: + enum: [ 1, 2, 3, 4 ] +description: + See ../../media/video-interfaces.yaml for details. + + lane-polarities: +minItems: 1 +maxItems: 5 +items: + enum: [ 0, 1 ] +description: + See ../../media/video-interfaces.yaml for details. + The Samsung MIPI DSI IP requires that all the data lanes have + the same polarity. + +dependencies: + lane-polarities: [data-lanes] + required: - clock-names - clocks -- 2.34.1
Re: [PATCH v2 1/2] dt-bindings: samsung,mipi-dsim: Add 'lane-polarities'
Hi Rob, On 12/04/2023 11:43, Rob Herring wrote: No, this should be video-interfaces.yaml since you use properties from it. Ok, will change it. +unevaluatedProperties: false + +properties: + data-lanes: +oneOf: + - minItems: 1 +maxItems: 4 +uniqueItems: true +items: + enum: [ 1, 2, 3, 4 ] The h/w really supports any combination of lanes to be used? The MIPI DSIM IP supports the usage of 1, 2, 3, or 4 data lanes. The following cases are possible: data-lanes = <1>; data-lanes = <1 2>; data-lanes = <1 2 3>; data-lanes = <1 2 3 4>; Lane reordering is not supported. +description: + See ../../media/video-interfaces.yaml for details. + + lane-polarities: +minItems: 1 +maxItems: 5 +items: + enum: [ 0, 1 ] +description: + See ../../media/video-interfaces.yaml for details. + The Samsung MIPI DSI IP requires that all the data lanes have + the same polarity. Sounds like a constraint: oneOf: - items: const: 0 - items: const: 1 Imagine a board that has 4 data lanes and only the clock lane is inverted. The representation is (the first entry is the clock lane, followed by the 4 data lanes): lane-polarities = <1 0 0 0 0>; If the board has no inversion on the clock lane, and has the data lanes inverted: lane-polarities = <0 1 1 1 1>; Should I keep the data-lanes and lane-polarities description as in this patch? Please advise. Thanks, Fabio Estevam
[PATCH] dt-bindings: drm/bridge: ti-sn65dsi86: Fix the video-interfaces.yaml references
From: Fabio Estevam video-interface.txt does not exist anymore, as it has been converted to video-interfaces.yaml. Instead of referencing video-interfaces.yaml multiple times, pass it as a $ref to the schema. Signed-off-by: Fabio Estevam --- Changes since v1: - Pass video-interfaces.yaml as a $ref to the schema. (Rob) .../devicetree/bindings/display/bridge/ti,sn65dsi86.yaml| 6 +- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.yaml b/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.yaml index 911564468c5e..6ec6d287bff4 100644 --- a/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.yaml +++ b/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.yaml @@ -90,7 +90,7 @@ properties: properties: endpoint: -$ref: /schemas/graph.yaml#/$defs/endpoint-base +$ref: /schemas/media/video-interfaces.yaml# unevaluatedProperties: false properties: @@ -106,7 +106,6 @@ properties: description: If you have 1 logical lane the bridge supports routing to either port 0 or port 1. Port 0 is suggested. - See ../../media/video-interface.txt for details. - minItems: 2 maxItems: 2 @@ -118,7 +117,6 @@ properties: description: If you have 2 logical lanes the bridge supports reordering but only on physical ports 0 and 1. - See ../../media/video-interface.txt for details. - minItems: 4 maxItems: 4 @@ -132,7 +130,6 @@ properties: description: If you have 4 logical lanes the bridge supports reordering in any way. - See ../../media/video-interface.txt for details. lane-polarities: minItems: 1 @@ -141,7 +138,6 @@ properties: enum: - 0 - 1 -description: See ../../media/video-interface.txt dependencies: lane-polarities: [data-lanes] -- 2.34.1
[PATCH] dt-bindings: drm/bridge: ti-sn65dsi86: Fix the video-interfaces.yaml references
From: Fabio Estevam video-interface.txt does not exist anymore, as it has been converted to video-interfaces.yaml. Update the references to the new file name. Signed-off-by: Fabio Estevam --- .../devicetree/bindings/display/bridge/ti,sn65dsi86.yaml | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.yaml b/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.yaml index 911564468c5e..967b1deb4936 100644 --- a/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.yaml +++ b/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.yaml @@ -106,7 +106,7 @@ properties: description: If you have 1 logical lane the bridge supports routing to either port 0 or port 1. Port 0 is suggested. - See ../../media/video-interface.txt for details. + See ../../media/video-interfaces.yaml for details. - minItems: 2 maxItems: 2 @@ -118,7 +118,7 @@ properties: description: If you have 2 logical lanes the bridge supports reordering but only on physical ports 0 and 1. - See ../../media/video-interface.txt for details. + See ../../media/video-interfaces.yaml for details. - minItems: 4 maxItems: 4 @@ -132,7 +132,7 @@ properties: description: If you have 4 logical lanes the bridge supports reordering in any way. - See ../../media/video-interface.txt for details. + See ../../media/video-interfaces.yaml for details. lane-polarities: minItems: 1 @@ -141,7 +141,7 @@ properties: enum: - 0 - 1 -description: See ../../media/video-interface.txt +description: See ../../media/video-interfaces.yaml dependencies: lane-polarities: [data-lanes] -- 2.34.1
[PATCH v2 2/2] drm: bridge: samsung-dsim: Implement support for clock/data polarity swap
From: Marek Vasut
Implement support for DSI clock and data lane DN/DP polarity swap by
means of decoding 'lane-polarities' DT property. The controller does
support DN/DP swap of clock lane and all data lanes, the controller
does not support polarity swap of individual data lane bundles, add
a check which verifies all data lanes have the same polarity.
This has been validated on an imx8mm board that actually has the MIPI DSI
clock lanes inverted.
Signed-off-by: Marek Vasut
Signed-off-by: Fabio Estevam
Reviewed-by: Jagan Teki
---
Changes since v1:
- Use 'drm: bridge: samsung-dsim:' as prefix (Jagan).
- Collected Jagan's Reviewed-by tag.
drivers/gpu/drm/bridge/samsung-dsim.c | 27 ++-
include/drm/bridge/samsung-dsim.h | 2 ++
2 files changed, 28 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c
b/drivers/gpu/drm/bridge/samsung-dsim.c
index e0a402a85787..5791148e2da2 100644
--- a/drivers/gpu/drm/bridge/samsung-dsim.c
+++ b/drivers/gpu/drm/bridge/samsung-dsim.c
@@ -183,6 +183,8 @@
#define DSIM_AFC_CTL(x)(((x) & 0x7) << 5)
/* DSIM_PLLCTRL */
+#define DSIM_PLL_DPDNSWAP_CLK (1 << 25)
+#define DSIM_PLL_DPDNSWAP_DAT (1 << 24)
#define DSIM_FREQ_BAND(x) ((x) << 24)
#define DSIM_PLL_ENBIT(23)
#define DSIM_PLL_P(x, offset) ((x) << (offset))
@@ -622,6 +624,11 @@ static unsigned long samsung_dsim_set_pll(struct
samsung_dsim *dsi,
reg |= DSIM_FREQ_BAND(band);
}
+ if (dsi->swap_dn_dp_clk)
+ reg |= DSIM_PLL_DPDNSWAP_CLK;
+ if (dsi->swap_dn_dp_data)
+ reg |= DSIM_PLL_DPDNSWAP_DAT;
+
samsung_dsim_write(dsi, DSIM_PLLCTRL_REG, reg);
timeout = 1000;
@@ -1696,7 +1703,9 @@ static int samsung_dsim_parse_dt(struct samsung_dsim *dsi)
{
struct device *dev = dsi->dev;
struct device_node *node = dev->of_node;
- int ret;
+ u32 lane_polarities[5] = { 0 };
+ struct device_node *endpoint;
+ int i, nr_lanes, ret;
ret = samsung_dsim_of_read_u32(node, "samsung,pll-clock-frequency",
&dsi->pll_clk_rate);
@@ -1713,6 +1722,22 @@ static int samsung_dsim_parse_dt(struct samsung_dsim
*dsi)
if (ret < 0)
return ret;
+ endpoint = of_graph_get_endpoint_by_regs(node, 1, -1);
+ nr_lanes = of_property_count_u32_elems(endpoint, "data-lanes");
+ if (nr_lanes > 0 && nr_lanes <= 4) {
+ /* Polarity 0 is clock lane, 1..4 are data lanes. */
+ of_property_read_u32_array(endpoint, "lane-polarities",
+ lane_polarities, nr_lanes + 1);
+ for (i = 1; i <= nr_lanes; i++) {
+ if (lane_polarities[1] != lane_polarities[i])
+ DRM_DEV_ERROR(dsi->dev, "Data lanes polarities
do not match");
+ }
+ if (lane_polarities[0])
+ dsi->swap_dn_dp_clk = true;
+ if (lane_polarities[1])
+ dsi->swap_dn_dp_data = true;
+ }
+
return 0;
}
diff --git a/include/drm/bridge/samsung-dsim.h
b/include/drm/bridge/samsung-dsim.h
index ba5484de2b30..6a37d1e079bf 100644
--- a/include/drm/bridge/samsung-dsim.h
+++ b/include/drm/bridge/samsung-dsim.h
@@ -95,6 +95,8 @@ struct samsung_dsim {
u32 mode_flags;
u32 format;
+ bool swap_dn_dp_clk;
+ bool swap_dn_dp_data;
int state;
struct drm_property *brightness;
struct completion completed;
--
2.34.1
[PATCH v2 1/2] dt-bindings: samsung,mipi-dsim: Add 'lane-polarities'
From: Fabio Estevam The Samsung DSIM IP block allows the inversion of the clock and data lanes. Add an optional property called 'lane-polarities' that describes the polarities of the MIPI DSI clock and data lanes. This property is useful for properly describing the hardware when the board designer decided to switch the polarities of the MIPI DSI clock and/or data lanes. Signed-off-by: Fabio Estevam --- Changes since v1: - Rebased against drm-misc-next that has samsung,mipi-dsim.yaml. .../display/bridge/samsung,mipi-dsim.yaml | 29 +++ 1 file changed, 29 insertions(+) diff --git a/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml b/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml index e841659e20cd..04eb440ade72 100644 --- a/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml +++ b/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml @@ -105,6 +105,35 @@ properties: DSI output port node to the panel or the next bridge in the chain. +properties: + endpoint: +$ref: /schemas/graph.yaml#/$defs/endpoint-base +unevaluatedProperties: false + +properties: + data-lanes: +oneOf: + - minItems: 1 +maxItems: 4 +uniqueItems: true +items: + enum: [ 1, 2, 3, 4 ] +description: + See ../../media/video-interfaces.yaml for details. + + lane-polarities: +minItems: 1 +maxItems: 5 +items: + enum: [ 0, 1 ] +description: + See ../../media/video-interfaces.yaml for details. + The Samsung MIPI DSI IP requires that all the data lanes have + the same polarity. + +dependencies: + lane-polarities: [data-lanes] + required: - clock-names - clocks -- 2.34.1
[PATCH v3] dt-bindings: bridge: Convert Samsung MIPI DSIM bridge to yaml
From: Jagan Teki Samsung MIPI DSIM bridge can be found on Exynos and NXP's i.MX8M Mini/Nano/Plus SoCs. Convert exynos_dsim.txt to yaml. Used the example node from exynos5433.dtsi instead of the one used in the legacy exynos_dsim.txt. Signed-off-by: Jagan Teki Signed-off-by: Fabio Estevam --- Changes since v2: - Took previous Rob Herring's feedback into account: https://lore.kernel.org/all/20210712151322.ga1931...@robh.at.kernel.org/ - Handled imx8mn and imx8mp. - Remove unnecessary #address-cells/size-cells. .../display/bridge/samsung,mipi-dsim.yaml | 255 ++ .../bindings/display/exynos/exynos_dsim.txt | 92 --- MAINTAINERS | 1 + 3 files changed, 256 insertions(+), 92 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml delete mode 100644 Documentation/devicetree/bindings/display/exynos/exynos_dsim.txt diff --git a/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml b/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml new file mode 100644 index ..55dbec178ea8 --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml @@ -0,0 +1,255 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/samsung,mipi-dsim.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung MIPI DSIM bridge controller + +maintainers: + - Inki Dae + - Jagan Teki + - Marek Szyprowski + +description: | + Samsung MIPI DSIM bridge controller can be found it on Exynos + and i.MX8M Mini/Nano/Plus SoC's. + +properties: + compatible: +oneOf: + - enum: + - samsung,exynos3250-mipi-dsi + - samsung,exynos4210-mipi-dsi + - samsung,exynos5410-mipi-dsi + - samsung,exynos5422-mipi-dsi + - samsung,exynos5433-mipi-dsi + - fsl,imx8mm-mipi-dsim + - fsl,imx8mp-mipi-dsim + - items: + - const: fsl,imx8mn-mipi-dsim + - const: fsl,imx8mm-mipi-dsim + + reg: +maxItems: 1 + + interrupts: +maxItems: 1 + + '#address-cells': +const: 1 + + '#size-cells': +const: 0 + + clocks: +minItems: 2 +maxItems: 5 + + clock-names: +minItems: 2 +maxItems: 5 + + samsung,phy-type: +$ref: /schemas/types.yaml#/definitions/uint32 +description: phandle to the samsung phy-type + + power-domains: +maxItems: 1 + + samsung,power-domain: +$ref: /schemas/types.yaml#/definitions/phandle +description: phandle to the associated samsung power domain + + vddcore-supply: +description: MIPI DSIM Core voltage supply (e.g. 1.1V) + + vddio-supply: +description: MIPI DSIM I/O and PLL voltage supply (e.g. 1.8V) + + samsung,burst-clock-frequency: +$ref: /schemas/types.yaml#/definitions/uint32 +description: + DSIM high speed burst mode frequency. + + samsung,esc-clock-frequency: +$ref: /schemas/types.yaml#/definitions/uint32 +description: + DSIM escape mode frequency. + + samsung,pll-clock-frequency: +$ref: /schemas/types.yaml#/definitions/uint32 +description: + DSIM oscillator clock frequency. + + phys: +maxItems: 1 + + phy-names: +const: dsim + + ports: +$ref: /schemas/graph.yaml#/properties/ports + +properties: + port@0: +$ref: /schemas/graph.yaml#/properties/port +description: + Input port node to receive pixel data from the + display controller. Exactly one endpoint must be + specified. + + port@1: +$ref: /schemas/graph.yaml#/properties/port +description: + DSI output port node to the panel or the next bridge + in the chain. + +required: + - clock-names + - clocks + - compatible + - interrupts + - reg + - samsung,burst-clock-frequency + - samsung,esc-clock-frequency + - samsung,pll-clock-frequency + +allOf: + - $ref: ../dsi-controller.yaml# + - if: + properties: +compatible: + contains: +const: samsung,exynos5433-mipi-dsi + +then: + properties: +clocks: + minItems: 5 + +clock-names: + items: +- const: bus_clk +- const: phyclk_mipidphy0_bitclkdiv8 +- const: phyclk_mipidphy0_rxclkesc0 +- const: sclk_rgb_vclk_to_dsim0 +- const: sclk_mipi + +ports: + required: +- port@0 + + required: +- ports +- vddcore-supply +- vddio-supply + + - if: + properties: +compatible: + contains: +const: samsung,exynos5410-mipi-dsi + +then: + properties: +clocks: + minItems: 2 + +clock-names: + items: +- const: bus_clk +- const: pll_clk + + required: +
[PATCH v3 2/2] drm/bridge: fsl-ldb: Add i.MX6SX support
From: Fabio Estevam
i.MX6SX has a single LVDS port and share a similar LDB_CTRL register layout
with i.MX8MP and i.MX93.
There is no LVDS CTRL register on the i.MX6SX, so only write to
this register on the appropriate SoCs.
Add support for the i.MX6SX LDB.
Tested on a imx6sx-sdb board with a Hannstar HSD100PXN1 LVDS panel
and also on a custom i.MX6SX-based board.
Signed-off-by: Fabio Estevam
Reviewed-by: Neil Armstrong
Reviewed-by: Marek Vasut
---
Changes since v2:
- Rename it to 'single_ctrl_reg' to make it clearer that on i.MX6X, there
is a single ctrl register. On the newer SoCs there are two ctrl registers.
Changes since v1:
- None
drivers/gpu/drm/bridge/fsl-ldb.c | 14 +-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/bridge/fsl-ldb.c b/drivers/gpu/drm/bridge/fsl-ldb.c
index 450b352914f4..f8e5d8ab98e3 100644
--- a/drivers/gpu/drm/bridge/fsl-ldb.c
+++ b/drivers/gpu/drm/bridge/fsl-ldb.c
@@ -56,6 +56,7 @@
#define LVDS_CTRL_VBG_ADJ_MASK GENMASK(19, 17)
enum fsl_ldb_devtype {
+ IMX6SX_LDB,
IMX8MP_LDB,
IMX93_LDB,
};
@@ -64,9 +65,14 @@ struct fsl_ldb_devdata {
u32 ldb_ctrl;
u32 lvds_ctrl;
bool lvds_en_bit;
+ bool single_ctrl_reg;
};
static const struct fsl_ldb_devdata fsl_ldb_devdata[] = {
+ [IMX6SX_LDB] = {
+ .ldb_ctrl = 0x18,
+ .single_ctrl_reg = true,
+ },
[IMX8MP_LDB] = {
.ldb_ctrl = 0x5c,
.lvds_ctrl = 0x128,
@@ -202,6 +208,9 @@ static void fsl_ldb_atomic_enable(struct drm_bridge *bridge,
regmap_write(fsl_ldb->regmap, fsl_ldb->devdata->ldb_ctrl, reg);
+ if (fsl_ldb->devdata->single_ctrl_reg)
+ return;
+
/* Program LVDS_CTRL */
reg = LVDS_CTRL_CC_ADJ(2) | LVDS_CTRL_PRE_EMPH_EN |
LVDS_CTRL_PRE_EMPH_ADJ(3) | LVDS_CTRL_VBG_EN;
@@ -228,7 +237,8 @@ static void fsl_ldb_atomic_disable(struct drm_bridge
*bridge,
regmap_write(fsl_ldb->regmap, fsl_ldb->devdata->lvds_ctrl,
LVDS_CTRL_LVDS_EN);
else
- regmap_write(fsl_ldb->regmap, fsl_ldb->devdata->lvds_ctrl, 0);
+ if (!fsl_ldb->devdata->single_ctrl_reg)
+ regmap_write(fsl_ldb->regmap,
fsl_ldb->devdata->lvds_ctrl, 0);
regmap_write(fsl_ldb->regmap, fsl_ldb->devdata->ldb_ctrl, 0);
clk_disable_unprepare(fsl_ldb->clk);
@@ -355,6 +365,8 @@ static void fsl_ldb_remove(struct platform_device *pdev)
}
static const struct of_device_id fsl_ldb_match[] = {
+ { .compatible = "fsl,imx6sx-ldb",
+ .data = &fsl_ldb_devdata[IMX6SX_LDB], },
{ .compatible = "fsl,imx8mp-ldb",
.data = &fsl_ldb_devdata[IMX8MP_LDB], },
{ .compatible = "fsl,imx93-ldb",
--
2.34.1
[PATCH v3 1/2] dt-bindings: display: bridge: ldb: Add an i.MX6SX entry
From: Fabio Estevam i.MX6SX has a single LVDS port and share a similar LDB_CTRL register layout with i.MX8MP and i.MX93. Signed-off-by: Fabio Estevam Reviewed-by: Krzysztof Kozlowski Reviewed-by: Marek Vasut --- Changes since v2: - Collected Reviewed-by tags. - Improved the Subject by not stating support. (Marek). Changes since v1: - Do not duplicate the entire if. (Krzysztof) .../devicetree/bindings/display/bridge/fsl,ldb.yaml | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/bridge/fsl,ldb.yaml b/Documentation/devicetree/bindings/display/bridge/fsl,ldb.yaml index 6e0e3ba9b49e..07388bf2b90d 100644 --- a/Documentation/devicetree/bindings/display/bridge/fsl,ldb.yaml +++ b/Documentation/devicetree/bindings/display/bridge/fsl,ldb.yaml @@ -17,6 +17,7 @@ description: | properties: compatible: enum: + - fsl,imx6sx-ldb - fsl,imx8mp-ldb - fsl,imx93-ldb @@ -64,7 +65,9 @@ allOf: properties: compatible: contains: -const: fsl,imx93-ldb +enum: + - fsl,imx6sx-ldb + - fsl,imx93-ldb then: properties: ports: -- 2.34.1
[PATCH v3] dt-bindings: bridge: Convert Samsung MIPI DSIM bridge to yaml
From: Jagan Teki Samsung MIPI DSIM bridge can be found on Exynos and NXP's i.MX8M Mini/Nano/Plus SoCs. Convert exynos_dsim.txt to yaml. Used the example node from exynos5433.dtsi instead of the one used in the legacy exynos_dsim.txt. Signed-off-by: Jagan Teki Signed-off-by: Fabio Estevam --- Changes since v2: - Took previous Rob Herring's feedback into account: https://lore.kernel.org/all/20210712151322.ga1931...@robh.at.kernel.org/ - Handled imx8mn and imx8mp - Remove unnecessary #address-cells/size-cells. .../display/bridge/samsung,mipi-dsim.yaml | 255 ++ .../bindings/display/exynos/exynos_dsim.txt | 92 --- MAINTAINERS | 1 + 3 files changed, 256 insertions(+), 92 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml delete mode 100644 Documentation/devicetree/bindings/display/exynos/exynos_dsim.txt diff --git a/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml b/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml new file mode 100644 index ..55dbec178ea8 --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml @@ -0,0 +1,255 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/samsung,mipi-dsim.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung MIPI DSIM bridge controller + +maintainers: + - Inki Dae + - Jagan Teki + - Marek Szyprowski + +description: | + Samsung MIPI DSIM bridge controller can be found it on Exynos + and i.MX8M Mini/Nano/Plus SoC's. + +properties: + compatible: +oneOf: + - enum: + - samsung,exynos3250-mipi-dsi + - samsung,exynos4210-mipi-dsi + - samsung,exynos5410-mipi-dsi + - samsung,exynos5422-mipi-dsi + - samsung,exynos5433-mipi-dsi + - fsl,imx8mm-mipi-dsim + - fsl,imx8mp-mipi-dsim + - items: + - const: fsl,imx8mn-mipi-dsim + - const: fsl,imx8mm-mipi-dsim + + reg: +maxItems: 1 + + interrupts: +maxItems: 1 + + '#address-cells': +const: 1 + + '#size-cells': +const: 0 + + clocks: +minItems: 2 +maxItems: 5 + + clock-names: +minItems: 2 +maxItems: 5 + + samsung,phy-type: +$ref: /schemas/types.yaml#/definitions/uint32 +description: phandle to the samsung phy-type + + power-domains: +maxItems: 1 + + samsung,power-domain: +$ref: /schemas/types.yaml#/definitions/phandle +description: phandle to the associated samsung power domain + + vddcore-supply: +description: MIPI DSIM Core voltage supply (e.g. 1.1V) + + vddio-supply: +description: MIPI DSIM I/O and PLL voltage supply (e.g. 1.8V) + + samsung,burst-clock-frequency: +$ref: /schemas/types.yaml#/definitions/uint32 +description: + DSIM high speed burst mode frequency. + + samsung,esc-clock-frequency: +$ref: /schemas/types.yaml#/definitions/uint32 +description: + DSIM escape mode frequency. + + samsung,pll-clock-frequency: +$ref: /schemas/types.yaml#/definitions/uint32 +description: + DSIM oscillator clock frequency. + + phys: +maxItems: 1 + + phy-names: +const: dsim + + ports: +$ref: /schemas/graph.yaml#/properties/ports + +properties: + port@0: +$ref: /schemas/graph.yaml#/properties/port +description: + Input port node to receive pixel data from the + display controller. Exactly one endpoint must be + specified. + + port@1: +$ref: /schemas/graph.yaml#/properties/port +description: + DSI output port node to the panel or the next bridge + in the chain + +required: + - clock-names + - clocks + - compatible + - interrupts + - reg + - samsung,burst-clock-frequency + - samsung,esc-clock-frequency + - samsung,pll-clock-frequency + +allOf: + - $ref: ../dsi-controller.yaml# + - if: + properties: +compatible: + contains: +const: samsung,exynos5433-mipi-dsi + +then: + properties: +clocks: + minItems: 5 + +clock-names: + items: +- const: bus_clk +- const: phyclk_mipidphy0_bitclkdiv8 +- const: phyclk_mipidphy0_rxclkesc0 +- const: sclk_rgb_vclk_to_dsim0 +- const: sclk_mipi + +ports: + required: +- port@0 + + required: +- ports +- vddcore-supply +- vddio-supply + + - if: + properties: +compatible: + contains: +const: samsung,exynos5410-mipi-dsi + +then: + properties: +clocks: + minItems: 2 + +clock-names: + items: +- const: bus_clk +- const: pll_clk + + required: +- vdd
Re: [PATCH v2] dt-bindings: bridge: Convert Samsung MIPI DSIM bridge to yaml
Hi Krzysztof, On 03/04/2023 09:49, Krzysztof Kozlowski wrote: Signed-off-by: Jagan Teki Signed-off-by: Fabio Estevam --- Changes since v1: - Added samsung,mipi-dsim.yaml entry to MAINTAINERS file (Jagan) - Added Marek Szyprowski entry to the samsung,mipi-dsim.yaml maintainers section (Jagan) - Mention that i.MX8M Plus is also supported (Marek) - Remove endpoint@0 description as it only has one endpoint (Marek) Where is the changelog from original submission? How your v1 differs form it? Or did you just ignore all the feedback? I'm sorry, but it was not my intention to ignore any feedback. Which feedback are you referring to specifically? Some more context: last week I sent a patch adding a new property for exynos_dsim.txt and you asked me to convert it to yaml first: https://lore.kernel.org/all/ff66c8b9-c7f7-1eb2-c730-4812b7ff6...@linaro.org/#t Jagan pointed out an earlier submission he did in 2021: https://lore.kernel.org/all/20210704090230.26489-9-ja...@amarulasolutions.com/ That was my starting point. + phys: +maxItems: 1 +description: phandle to the phy module representing the DPHY OK, so you did ignore the feedback. Not intentionally. NAK, go through the feedback and implement it. Just found this feedback from Rob about Jagan's initial submission: https://lore.kernel.org/all/20210712151322.ga1931...@robh.at.kernel.org/ I can send a new version that takes Rob's feedback into account. Were there any further versions/feedback that were submitted? Can't find them on lore. In another reply, you mention that this should be v13. I could not find previous versions of the yaml submission. Please advise. Thanks, Fabio Estevam
[PATCH v2] dt-bindings: bridge: Convert Samsung MIPI DSIM bridge to yaml
From: Jagan Teki Samsung MIPI DSIM bridge can be found on Exynos and NXP's i.MX8M Mini/Nano/Plus SoCs. Convert exynos_dsim.txt to yaml. Used the example node from latest Exynos SoC instead of the one used in legacy exynos_dsim.txt. Signed-off-by: Jagan Teki Signed-off-by: Fabio Estevam --- Changes since v1: - Added samsung,mipi-dsim.yaml entry to MAINTAINERS file (Jagan) - Added Marek Szyprowski entry to the samsung,mipi-dsim.yaml maintainers section (Jagan) - Mention that i.MX8M Plus is also supported (Marek) - Remove endpoint@0 description as it only has one endpoint (Marek) .../display/bridge/samsung,mipi-dsim.yaml | 271 ++ .../bindings/display/exynos/exynos_dsim.txt | 92 -- MAINTAINERS | 1 + 3 files changed, 272 insertions(+), 92 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml delete mode 100644 Documentation/devicetree/bindings/display/exynos/exynos_dsim.txt diff --git a/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml b/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml new file mode 100644 index ..2698752dc6ed --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml @@ -0,0 +1,271 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/samsung,mipi-dsim.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung MIPI DSIM bridge controller + +maintainers: + - Inki Dae + - Jagan Teki + +description: | + Samsung MIPI DSIM bridge controller can be found it on Exynos + and i.MX8M Mini/Nano/Plus SoC's. + +properties: + compatible: +enum: + - samsung,exynos3250-mipi-dsi + - samsung,exynos4210-mipi-dsi + - samsung,exynos5410-mipi-dsi + - samsung,exynos5422-mipi-dsi + - samsung,exynos5433-mipi-dsi + - fsl,imx8mm-mipi-dsim + - fsl,imx8mp-mipi-dsim + + reg: +maxItems: 1 + + interrupts: +maxItems: 1 + + '#address-cells': +const: 1 + + '#size-cells': +const: 0 + + clocks: +minItems: 2 +maxItems: 5 + + clock-names: +minItems: 2 +maxItems: 5 + + phys: +maxItems: 1 +description: phandle to the phy module representing the DPHY + + phy-names: +items: + - const: dsim + + samsung,phy-type: +$ref: /schemas/types.yaml#/definitions/uint32 +description: phandle to the samsung phy-type + + power-domains: +description: phandle to the associated power domain +maxItems: 1 + + samsung,power-domain: +$ref: /schemas/types.yaml#/definitions/phandle +description: phandle to the associated samsung power domain + + vddcore-supply: +description: MIPI DSIM Core voltage supply (e.g. 1.1V) + + vddio-supply: +description: MIPI DSIM I/O and PLL voltage supply (e.g. 1.8V) + + samsung,burst-clock-frequency: +$ref: /schemas/types.yaml#/definitions/uint32 +description: + DSIM high speed burst mode frequency. + + samsung,esc-clock-frequency: +$ref: /schemas/types.yaml#/definitions/uint32 +description: + DSIM escape mode frequency. + + samsung,pll-clock-frequency: +$ref: /schemas/types.yaml#/definitions/uint32 +description: + DSIM oscillator clock frequency. + + ports: +$ref: /schemas/graph.yaml#/properties/ports + +properties: + port@0: +$ref: /schemas/graph.yaml#/$defs/port-base +description: + Input port node to receive pixel data from the + display controller. Exactly one endpoint must be + specified. + +unevaluatedProperties: false + + port@1: +$ref: /schemas/graph.yaml#/properties/port +description: + DSI output port node to the panel or the next bridge + in the chain + +required: + - '#address-cells' + - '#size-cells' + - clock-names + - clocks + - compatible + - interrupts + - phy-names + - phys + - reg + - samsung,burst-clock-frequency + - samsung,esc-clock-frequency + - samsung,pll-clock-frequency + +allOf: + - $ref: ../dsi-controller.yaml# + - if: + properties: +compatible: + contains: +const: samsung,exynos5433-mipi-dsi + +then: + properties: +clocks: + minItems: 5 + +clock-names: + items: +- const: bus_clk +- const: phyclk_mipidphy0_bitclkdiv8 +- const: phyclk_mipidphy0_rxclkesc0 +- const: sclk_rgb_vclk_to_dsim0 +- const: sclk_mipi + +ports: + required: +- port@0 + + required: +- ports +- vddcore-supply +- vddio-supply + + - if: + properties: +compatible: + contains: +const: samsung,exynos5410-mipi-dsi + +then: + properties: +
[PATCH] dt-bindings: bridge: Convert Samsung MIPI DSIM bridge to yaml
From: Jagan Teki Samsung MIPI DSIM bridge can be found on Exynos and NXP's i.MX8M Mini and Nano SoC's. Convert exynos_dsim.txt to yaml. Used the example node from latest Exynos SoC instead of the one used in legacy exynos_dsim.txt. Signed-off-by: Jagan Teki Signed-off-by: Fabio Estevam --- .../display/bridge/samsung,mipi-dsim.yaml | 275 ++ .../bindings/display/exynos/exynos_dsim.txt | 92 -- 2 files changed, 275 insertions(+), 92 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml delete mode 100644 Documentation/devicetree/bindings/display/exynos/exynos_dsim.txt diff --git a/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml b/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml new file mode 100644 index ..c131bd879caf --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml @@ -0,0 +1,275 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/samsung,mipi-dsim.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung MIPI DSIM bridge controller + +maintainers: + - Inki Dae + - Jagan Teki + +description: | + Samsung MIPI DSIM bridge controller can be found it on Exynos + and i.MX8M Mini and Nano SoC's. + +properties: + compatible: +enum: + - samsung,exynos3250-mipi-dsi + - samsung,exynos4210-mipi-dsi + - samsung,exynos5410-mipi-dsi + - samsung,exynos5422-mipi-dsi + - samsung,exynos5433-mipi-dsi + - fsl,imx8mm-mipi-dsim + - fsl,imx8mp-mipi-dsim + + reg: +maxItems: 1 + + interrupts: +maxItems: 1 + + '#address-cells': +const: 1 + + '#size-cells': +const: 0 + + clocks: +minItems: 2 +maxItems: 5 + + clock-names: +minItems: 2 +maxItems: 5 + + phys: +maxItems: 1 +description: phandle to the phy module representing the DPHY + + phy-names: +items: + - const: dsim + + samsung,phy-type: +$ref: /schemas/types.yaml#/definitions/uint32 +description: phandle to the samsung phy-type + + power-domains: +description: phandle to the associated power domain +maxItems: 1 + + samsung,power-domain: +$ref: /schemas/types.yaml#/definitions/phandle +description: phandle to the associated samsung power domain + + vddcore-supply: +description: MIPI DSIM Core voltage supply (e.g. 1.1V) + + vddio-supply: +description: MIPI DSIM I/O and PLL voltage supply (e.g. 1.8V) + + samsung,burst-clock-frequency: +$ref: /schemas/types.yaml#/definitions/uint32 +description: + DSIM high speed burst mode frequency. + + samsung,esc-clock-frequency: +$ref: /schemas/types.yaml#/definitions/uint32 +description: + DSIM escape mode frequency. + + samsung,pll-clock-frequency: +$ref: /schemas/types.yaml#/definitions/uint32 +description: + DSIM oscillator clock frequency. + + ports: +$ref: /schemas/graph.yaml#/properties/ports + +properties: + port@0: +$ref: /schemas/graph.yaml#/$defs/port-base +description: + Input port node to receive pixel data from the + display controller. Exactly one endpoint must be + specified. +properties: + endpoint@0: +$ref: /schemas/graph.yaml#/properties/endpoint +description: sub-node describing the input from MIC + +unevaluatedProperties: false + + port@1: +$ref: /schemas/graph.yaml#/properties/port +description: + DSI output port node to the panel or the next bridge + in the chain + +required: + - '#address-cells' + - '#size-cells' + - clock-names + - clocks + - compatible + - interrupts + - phy-names + - phys + - reg + - samsung,burst-clock-frequency + - samsung,esc-clock-frequency + - samsung,pll-clock-frequency + +allOf: + - $ref: ../dsi-controller.yaml# + - if: + properties: +compatible: + contains: +const: samsung,exynos5433-mipi-dsi + +then: + properties: +clocks: + minItems: 5 + +clock-names: + items: +- const: bus_clk +- const: phyclk_mipidphy0_bitclkdiv8 +- const: phyclk_mipidphy0_rxclkesc0 +- const: sclk_rgb_vclk_to_dsim0 +- const: sclk_mipi + +ports: + required: +- port@0 + + required: +- ports +- vddcore-supply +- vddio-supply + + - if: + properties: +compatible: + contains: +const: samsung,exynos5410-mipi-dsi + +then: + properties: +clocks: + minItems: 2 + +clock-names: + items: +- const: bus_clk +- const: pll_clk + + required: +- vddcore-supp
Re: [PATCH 1/2] dt-bindings: display: exynos: dsim: Add 'lane-polarities'
Hi Jagan, On Thu, Mar 30, 2023 at 4:55 AM Jagan Teki wrote: > I have a previous iteration of this conversion. Can I resend it on top > of drm-misc-next? > https://lore.kernel.org/all/20210704090230.26489-9-ja...@amarulasolutions.com/ I tried applying your patch against linux-next, but I get the following error: $ make dt_binding_check DT_SCHEMA_FILES=samsung,mipi-dsim.yaml LINTDocumentation/devicetree/bindings CHKDT Documentation/devicetree/bindings/processed-schema.json /home/fabio/linux-next/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml: properties:samsung,power-domain:maxItems: False schema does not allow 1 hint: Scalar properties should not have array keywords from schema $id: http://devicetree.org/meta-schemas/keywords.yaml# DTEX Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.example.dts DTC_CHK Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.example.dtb Could you please take a look? Thanks
[PATCH v2 2/2] drm/bridge: fsl-ldb: Add i.MX6SX support
From: Fabio Estevam
i.MX6SX has a single LVDS port and share a similar LDB_CTRL register layout
with i.MX8MP and i.MX93.
There is no LVDS CTRL register on the i.MX6SX, so only write to
this register on the appropriate SoCs.
Add support for the i.MX6SX LDB.
Tested on a imx6sx-sdb board with a Hannstar HSD100PXN1 LVDS panel
and also on a custom i.MX6SX-based board.
Signed-off-by: Fabio Estevam
---
Changes since v1:
- None
drivers/gpu/drm/bridge/fsl-ldb.c | 14 +-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/bridge/fsl-ldb.c b/drivers/gpu/drm/bridge/fsl-ldb.c
index 450b352914f4..f8e5d8ab98e3 100644
--- a/drivers/gpu/drm/bridge/fsl-ldb.c
+++ b/drivers/gpu/drm/bridge/fsl-ldb.c
@@ -56,6 +56,7 @@
#define LVDS_CTRL_VBG_ADJ_MASK GENMASK(19, 17)
enum fsl_ldb_devtype {
+ IMX6SX_LDB,
IMX8MP_LDB,
IMX93_LDB,
};
@@ -64,9 +65,14 @@ struct fsl_ldb_devdata {
u32 ldb_ctrl;
u32 lvds_ctrl;
bool lvds_en_bit;
+ bool not_lvds_ctrl;
};
static const struct fsl_ldb_devdata fsl_ldb_devdata[] = {
+ [IMX6SX_LDB] = {
+ .ldb_ctrl = 0x18,
+ .not_lvds_ctrl = true,
+ },
[IMX8MP_LDB] = {
.ldb_ctrl = 0x5c,
.lvds_ctrl = 0x128,
@@ -202,6 +208,9 @@ static void fsl_ldb_atomic_enable(struct drm_bridge *bridge,
regmap_write(fsl_ldb->regmap, fsl_ldb->devdata->ldb_ctrl, reg);
+ if (fsl_ldb->devdata->not_lvds_ctrl)
+ return;
+
/* Program LVDS_CTRL */
reg = LVDS_CTRL_CC_ADJ(2) | LVDS_CTRL_PRE_EMPH_EN |
LVDS_CTRL_PRE_EMPH_ADJ(3) | LVDS_CTRL_VBG_EN;
@@ -228,7 +237,8 @@ static void fsl_ldb_atomic_disable(struct drm_bridge
*bridge,
regmap_write(fsl_ldb->regmap, fsl_ldb->devdata->lvds_ctrl,
LVDS_CTRL_LVDS_EN);
else
- regmap_write(fsl_ldb->regmap, fsl_ldb->devdata->lvds_ctrl, 0);
+ if (!fsl_ldb->devdata->not_lvds_ctrl)
+ regmap_write(fsl_ldb->regmap,
fsl_ldb->devdata->lvds_ctrl, 0);
regmap_write(fsl_ldb->regmap, fsl_ldb->devdata->ldb_ctrl, 0);
clk_disable_unprepare(fsl_ldb->clk);
@@ -355,6 +365,8 @@ static void fsl_ldb_remove(struct platform_device *pdev)
}
static const struct of_device_id fsl_ldb_match[] = {
+ { .compatible = "fsl,imx6sx-ldb",
+ .data = &fsl_ldb_devdata[IMX6SX_LDB], },
{ .compatible = "fsl,imx8mp-ldb",
.data = &fsl_ldb_devdata[IMX8MP_LDB], },
{ .compatible = "fsl,imx93-ldb",
--
2.34.1
[PATCH v2 1/2] dt-bindings: display: bridge: ldb: Add i.MX6SX support
From: Fabio Estevam i.MX6SX has a single LVDS port and share a similar LDB_CTRL register layout with i.MX8MP and i.MX93. Signed-off-by: Fabio Estevam --- Changes since v1: - Do not duplicate the entire if. (Krzysztof) .../devicetree/bindings/display/bridge/fsl,ldb.yaml | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/bridge/fsl,ldb.yaml b/Documentation/devicetree/bindings/display/bridge/fsl,ldb.yaml index 6e0e3ba9b49e..07388bf2b90d 100644 --- a/Documentation/devicetree/bindings/display/bridge/fsl,ldb.yaml +++ b/Documentation/devicetree/bindings/display/bridge/fsl,ldb.yaml @@ -17,6 +17,7 @@ description: | properties: compatible: enum: + - fsl,imx6sx-ldb - fsl,imx8mp-ldb - fsl,imx93-ldb @@ -64,7 +65,9 @@ allOf: properties: compatible: contains: -const: fsl,imx93-ldb +enum: + - fsl,imx6sx-ldb + - fsl,imx93-ldb then: properties: ports: -- 2.34.1
[PATCH v2] dt-bindings: display: seiko, 43wvf1g: Change the maintainer's contact
From: Fabio Estevam Marco's NXP email is no longer valid. Marco told me offline that he has no interest to be listed as the maintainer contact for this binding, so add my contact. Signed-off-by: Fabio Estevam --- Changes since v1: - Use my contact instead of Marco's personal email. .../devicetree/bindings/display/panel/seiko,43wvf1g.yaml| 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/panel/seiko,43wvf1g.yaml b/Documentation/devicetree/bindings/display/panel/seiko,43wvf1g.yaml index a5426586b473..1df3cbb51ff9 100644 --- a/Documentation/devicetree/bindings/display/panel/seiko,43wvf1g.yaml +++ b/Documentation/devicetree/bindings/display/panel/seiko,43wvf1g.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Seiko Instruments Inc. 4.3" WVGA (800 x RGB x 480) TFT with Touch-Panel maintainers: - - Marco Franchi + - Fabio Estevam allOf: - $ref: panel-common.yaml# -- 2.34.1
[PATCH 2/2] drm/exynos: Implement support for DSI clock and data lane polarity swap
From: Marek Vasut
Implement support for DSI clock and data lane DN/DP polarity swap by
means of decoding 'lane-polarities' DT property. The controller does
support DN/DP swap of clock lane and all data lanes, the controller
does not support polarity swap of individual data lane bundles, add
a check which verifies all data lanes have the same polarity.
This has been validated on an imx8mm board that actually has the MIPI DSI
clock lanes inverted.
Signed-off-by: Marek Vasut
Signed-off-by: Fabio Estevam
---
drivers/gpu/drm/bridge/samsung-dsim.c | 27 ++-
include/drm/bridge/samsung-dsim.h | 2 ++
2 files changed, 28 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c
b/drivers/gpu/drm/bridge/samsung-dsim.c
index e0a402a85787..5791148e2da2 100644
--- a/drivers/gpu/drm/bridge/samsung-dsim.c
+++ b/drivers/gpu/drm/bridge/samsung-dsim.c
@@ -183,6 +183,8 @@
#define DSIM_AFC_CTL(x)(((x) & 0x7) << 5)
/* DSIM_PLLCTRL */
+#define DSIM_PLL_DPDNSWAP_CLK (1 << 25)
+#define DSIM_PLL_DPDNSWAP_DAT (1 << 24)
#define DSIM_FREQ_BAND(x) ((x) << 24)
#define DSIM_PLL_ENBIT(23)
#define DSIM_PLL_P(x, offset) ((x) << (offset))
@@ -622,6 +624,11 @@ static unsigned long samsung_dsim_set_pll(struct
samsung_dsim *dsi,
reg |= DSIM_FREQ_BAND(band);
}
+ if (dsi->swap_dn_dp_clk)
+ reg |= DSIM_PLL_DPDNSWAP_CLK;
+ if (dsi->swap_dn_dp_data)
+ reg |= DSIM_PLL_DPDNSWAP_DAT;
+
samsung_dsim_write(dsi, DSIM_PLLCTRL_REG, reg);
timeout = 1000;
@@ -1696,7 +1703,9 @@ static int samsung_dsim_parse_dt(struct samsung_dsim *dsi)
{
struct device *dev = dsi->dev;
struct device_node *node = dev->of_node;
- int ret;
+ u32 lane_polarities[5] = { 0 };
+ struct device_node *endpoint;
+ int i, nr_lanes, ret;
ret = samsung_dsim_of_read_u32(node, "samsung,pll-clock-frequency",
&dsi->pll_clk_rate);
@@ -1713,6 +1722,22 @@ static int samsung_dsim_parse_dt(struct samsung_dsim
*dsi)
if (ret < 0)
return ret;
+ endpoint = of_graph_get_endpoint_by_regs(node, 1, -1);
+ nr_lanes = of_property_count_u32_elems(endpoint, "data-lanes");
+ if (nr_lanes > 0 && nr_lanes <= 4) {
+ /* Polarity 0 is clock lane, 1..4 are data lanes. */
+ of_property_read_u32_array(endpoint, "lane-polarities",
+ lane_polarities, nr_lanes + 1);
+ for (i = 1; i <= nr_lanes; i++) {
+ if (lane_polarities[1] != lane_polarities[i])
+ DRM_DEV_ERROR(dsi->dev, "Data lanes polarities
do not match");
+ }
+ if (lane_polarities[0])
+ dsi->swap_dn_dp_clk = true;
+ if (lane_polarities[1])
+ dsi->swap_dn_dp_data = true;
+ }
+
return 0;
}
diff --git a/include/drm/bridge/samsung-dsim.h
b/include/drm/bridge/samsung-dsim.h
index ba5484de2b30..6a37d1e079bf 100644
--- a/include/drm/bridge/samsung-dsim.h
+++ b/include/drm/bridge/samsung-dsim.h
@@ -95,6 +95,8 @@ struct samsung_dsim {
u32 mode_flags;
u32 format;
+ bool swap_dn_dp_clk;
+ bool swap_dn_dp_data;
int state;
struct drm_property *brightness;
struct completion completed;
--
2.34.1
[PATCH 1/2] dt-bindings: display: exynos: dsim: Add 'lane-polarities'
From: Fabio Estevam The Samsung DSIM IP block allows the inversion of the clock and data lanes. Add an optional property called 'lane-polarities' that describes the polarities of the MIPI DSI clock and data lanes. This is property is useful for properly describing the hardware when the board designer decided to switch the polarities of the MIPI DSI clock and/or data lanes. Signed-off-by: Fabio Estevam --- .../devicetree/bindings/display/exynos/exynos_dsim.txt | 6 ++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/display/exynos/exynos_dsim.txt b/Documentation/devicetree/bindings/display/exynos/exynos_dsim.txt index 2a5f0889ec32..65ed8ef7aed7 100644 --- a/Documentation/devicetree/bindings/display/exynos/exynos_dsim.txt +++ b/Documentation/devicetree/bindings/display/exynos/exynos_dsim.txt @@ -29,6 +29,12 @@ Required properties: Optional properties: - power-domains: a phandle to DSIM power domain node + - lane-polarities: Array that describes the polarities of the clock and data lanes. +1: inverted polarity +0: normal polarity +The first entry corresponds to the clock lanes. Subsequent entries correspond to the data lanes. +Example of a 4-lane system with only the clock lanes inverted: +lane-polarities = <1 0 0 0 0>; Child nodes: Should contain DSI peripheral nodes (see MIPI DSI bindings [1]). -- 2.34.1
[PATCH 2/2] drm/bridge: fsl-ldb: Add i.MX6SX support
From: Fabio Estevam
i.MX6SX has a single LVDS port and share a similar LDB_CTRL register layout
with i.MX8MP and i.MX93.
There is no LVDS CTRL register on the i.MX6SX, so only write to
this register on the appropriate SoCs.
Add support for the i.MX6SX LDB.
Tested on a imx6sx-sdb board with a Hannstar HSD100PXN1 LVDS panel
and also on a custom i.MX6SX-based board.
Signed-off-by: Fabio Estevam
---
drivers/gpu/drm/bridge/fsl-ldb.c | 14 +-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/bridge/fsl-ldb.c b/drivers/gpu/drm/bridge/fsl-ldb.c
index 450b352914f4..f8e5d8ab98e3 100644
--- a/drivers/gpu/drm/bridge/fsl-ldb.c
+++ b/drivers/gpu/drm/bridge/fsl-ldb.c
@@ -56,6 +56,7 @@
#define LVDS_CTRL_VBG_ADJ_MASK GENMASK(19, 17)
enum fsl_ldb_devtype {
+ IMX6SX_LDB,
IMX8MP_LDB,
IMX93_LDB,
};
@@ -64,9 +65,14 @@ struct fsl_ldb_devdata {
u32 ldb_ctrl;
u32 lvds_ctrl;
bool lvds_en_bit;
+ bool not_lvds_ctrl;
};
static const struct fsl_ldb_devdata fsl_ldb_devdata[] = {
+ [IMX6SX_LDB] = {
+ .ldb_ctrl = 0x18,
+ .not_lvds_ctrl = true,
+ },
[IMX8MP_LDB] = {
.ldb_ctrl = 0x5c,
.lvds_ctrl = 0x128,
@@ -202,6 +208,9 @@ static void fsl_ldb_atomic_enable(struct drm_bridge *bridge,
regmap_write(fsl_ldb->regmap, fsl_ldb->devdata->ldb_ctrl, reg);
+ if (fsl_ldb->devdata->not_lvds_ctrl)
+ return;
+
/* Program LVDS_CTRL */
reg = LVDS_CTRL_CC_ADJ(2) | LVDS_CTRL_PRE_EMPH_EN |
LVDS_CTRL_PRE_EMPH_ADJ(3) | LVDS_CTRL_VBG_EN;
@@ -228,7 +237,8 @@ static void fsl_ldb_atomic_disable(struct drm_bridge
*bridge,
regmap_write(fsl_ldb->regmap, fsl_ldb->devdata->lvds_ctrl,
LVDS_CTRL_LVDS_EN);
else
- regmap_write(fsl_ldb->regmap, fsl_ldb->devdata->lvds_ctrl, 0);
+ if (!fsl_ldb->devdata->not_lvds_ctrl)
+ regmap_write(fsl_ldb->regmap,
fsl_ldb->devdata->lvds_ctrl, 0);
regmap_write(fsl_ldb->regmap, fsl_ldb->devdata->ldb_ctrl, 0);
clk_disable_unprepare(fsl_ldb->clk);
@@ -355,6 +365,8 @@ static void fsl_ldb_remove(struct platform_device *pdev)
}
static const struct of_device_id fsl_ldb_match[] = {
+ { .compatible = "fsl,imx6sx-ldb",
+ .data = &fsl_ldb_devdata[IMX6SX_LDB], },
{ .compatible = "fsl,imx8mp-ldb",
.data = &fsl_ldb_devdata[IMX8MP_LDB], },
{ .compatible = "fsl,imx93-ldb",
--
2.34.1
[PATCH 1/2] dt-bindings: display: bridge: ldb: Add i.MX6SX support
From: Fabio Estevam i.MX6SX has a single LVDS port and share a similar LDB_CTRL register layout with i.MX8MP and i.MX93. Signed-off-by: Fabio Estevam --- .../devicetree/bindings/display/bridge/fsl,ldb.yaml | 11 +++ 1 file changed, 11 insertions(+) diff --git a/Documentation/devicetree/bindings/display/bridge/fsl,ldb.yaml b/Documentation/devicetree/bindings/display/bridge/fsl,ldb.yaml index 6e0e3ba9b49e..4f842bcfba1a 100644 --- a/Documentation/devicetree/bindings/display/bridge/fsl,ldb.yaml +++ b/Documentation/devicetree/bindings/display/bridge/fsl,ldb.yaml @@ -17,6 +17,7 @@ description: | properties: compatible: enum: + - fsl,imx6sx-ldb - fsl,imx8mp-ldb - fsl,imx93-ldb @@ -60,6 +61,16 @@ required: - ports allOf: + - if: + properties: +compatible: + contains: +const: fsl,imx6sx-ldb +then: + properties: +ports: + properties: +port@2: false - if: properties: compatible: -- 2.34.1
Re: [PATCH v15 00/16] drm: Add Samsung MIPI DSIM bridge
Hi Inki, On Mon, Mar 13, 2023 at 9:51 PM Inki Dae wrote: >> Could you please apply v16? > > > I am planning to merge this patch series soon, but I will be proceeding with > the pull-request next week. As the DSIM driver is being moved to the bridge > folder, I would like to wait for acknowledgment from the bridge maintainers. > However, if there are no further comments until next week, I will proceed > with the pull-request. A friendly reminder: do you think you can proceed with the pull-request now? Thanks
[PATCH] dt-bindings: display: seiko, 43wvf1g: Change the maintainer's email
From: Fabio Estevam Marco's NXP email is no longer valid. Change it to his Gmail account. Signed-off-by: Fabio Estevam --- Marco, If you are no longer interested in being listed as the maintainer contact for the seiko,43wvf1g.yaml, please let me know. .../devicetree/bindings/display/panel/seiko,43wvf1g.yaml| 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/panel/seiko,43wvf1g.yaml b/Documentation/devicetree/bindings/display/panel/seiko,43wvf1g.yaml index a5426586b473..7977e07e2f48 100644 --- a/Documentation/devicetree/bindings/display/panel/seiko,43wvf1g.yaml +++ b/Documentation/devicetree/bindings/display/panel/seiko,43wvf1g.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Seiko Instruments Inc. 4.3" WVGA (800 x RGB x 480) TFT with Touch-Panel maintainers: - - Marco Franchi + - Marco Franchi allOf: - $ref: panel-common.yaml# -- 2.34.1
[PATCH 1/2] dt-bindings: display: seiko, 43wvf1g: Add the 'enable-gpios' property
Add an optional 'enable-gpios' property that can be used to turn on/off the display. Signed-off-by: Fabio Estevam --- .../devicetree/bindings/display/panel/seiko,43wvf1g.yaml| 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/display/panel/seiko,43wvf1g.yaml b/Documentation/devicetree/bindings/display/panel/seiko,43wvf1g.yaml index cfaa50cf5f5d..496a39561db0 100644 --- a/Documentation/devicetree/bindings/display/panel/seiko,43wvf1g.yaml +++ b/Documentation/devicetree/bindings/display/panel/seiko,43wvf1g.yaml @@ -25,6 +25,8 @@ properties: avdd-supply: description: 5v analog regulator + enable-gpios: true + required: - compatible - dvdd-supply -- 2.34.1
[PATCH 2/2] drm/panel: seiko-43wvf1g: Add the 'enable-gpios' property
Sometimes a GPIO is needed to turn on/off the display.
Add support for this usecase by introducing the optional 'enable-gpios'
property.
Tested on a imx53qsb board.
Signed-off-by: Fabio Estevam
---
drivers/gpu/drm/panel/panel-seiko-43wvf1g.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/panel/panel-seiko-43wvf1g.c
b/drivers/gpu/drm/panel/panel-seiko-43wvf1g.c
index 76160e5d43bd..c250ca36a5b3 100644
--- a/drivers/gpu/drm/panel/panel-seiko-43wvf1g.c
+++ b/drivers/gpu/drm/panel/panel-seiko-43wvf1g.c
@@ -7,6 +7,7 @@
*/
#include
+#include
#include
#include
#include
@@ -48,6 +49,7 @@ struct seiko_panel {
const struct seiko_panel_desc *desc;
struct regulator *dvdd;
struct regulator *avdd;
+ struct gpio_desc *enable_gpio;
};
static inline struct seiko_panel *to_seiko_panel(struct drm_panel *panel)
@@ -139,6 +141,8 @@ static int seiko_panel_unprepare(struct drm_panel *panel)
if (!p->prepared)
return 0;
+ gpiod_set_value_cansleep(p->enable_gpio, 0);
+
regulator_disable(p->avdd);
/* Add a 100ms delay as per the panel datasheet */
@@ -174,6 +178,8 @@ static int seiko_panel_prepare(struct drm_panel *panel)
goto disable_dvdd;
}
+ gpiod_set_value_cansleep(p->enable_gpio, 1);
+
p->prepared = true;
return 0;
@@ -252,6 +258,12 @@ static int seiko_panel_probe(struct device *dev,
if (IS_ERR(panel->avdd))
return PTR_ERR(panel->avdd);
+ panel->enable_gpio = devm_gpiod_get_optional(dev, "enable",
+GPIOD_OUT_LOW);
+ if (IS_ERR(panel->enable_gpio))
+ return dev_err_probe(dev, PTR_ERR(panel->enable_gpio),
+"failed to request GPIO\n");
+
drm_panel_init(&panel->base, dev, &seiko_panel_funcs,
DRM_MODE_CONNECTOR_DPI);
--
2.34.1
Re: [PATCH v15 00/16] drm: Add Samsung MIPI DSIM bridge
Hi Inki, On Mon, Mar 6, 2023 at 2:24 AM 대인기/Tizen Platform Lab(SR)/삼성전자 wrote: > Seems some issue Marek found on testing. If fixed then I will try to pick this > patch series up. Marek has successfully tested v16. Could you please apply v16? Thanks
Re: [PATCH] drm/msm: fix PM_DEVFREQ kconfig dependency warning
On Tue, Mar 7, 2023 at 2:46 PM Randy Dunlap wrote:
>
> Since DEVFREQ_GOV_SIMPLE_ONDEMAND depends on PM_DEVFREQ, the latter
> should either be selected or DRM_MSM should depend on PM_DEVFREQ.
> Since most drivers select PM_DEVFREQ instead of depending on it,
> add a select here to satisfy kconfig.
>
> WARNING: unmet direct dependencies detected for DEVFREQ_GOV_SIMPLE_ONDEMAND
> Depends on [n]: PM_DEVFREQ [=n]
> Selected by [y]:
> - DRM_MSM [=y] && HAS_IOMEM [=y] && DRM [=y] && (ARCH_QCOM || SOC_IMX5 ||
> COMPILE_TEST [=y]) && COMMON_CLK [=y] && IOMMU_SUPPORT [=y] && (QCOM_OCMEM
> [=n] || QCOM_OCMEM [=n]=n) && (QCOM_LLCC [=n] || QCOM_LLCC [=n]=n) &&
> (QCOM_COMMAND_DB [=y] || QCOM_COMMAND_DB [=y]=n)
>
> Fixes: 6563f60f14cb ("drm/msm/gpu: Add devfreq tuning debugfs")
> Signed-off-by: Randy Dunlap
> Reported-by: kernel test robot
> Link: lore.kernel.org/r/202303071922.wjqdwqpe-...@intel.com
> Cc: Rob Clark
> Cc: Paul Gazzillo
> Cc: Necip Fazil Yildiran
> Cc: Chia-I Wu
> Cc: Abhinav Kumar
> Cc: Dmitry Baryshkov
> Cc: linux-arm-...@vger.kernel.org
> Cc: dri-devel@lists.freedesktop.org
> Cc: freedr...@lists.freedesktop.org
This fixes the warning after running 'make imx_v6_v7_defconfig', thanks:
Tested-by: Fabio Estevam
Re: [PATCH v12 00/18] drm: Add Samsung MIPI DSIM bridge
On Tue, Feb 14, 2023 at 8:09 AM Fabio Estevam wrote: > Some extra ADV7535 patches were needed. Please check patches 0020-0023 > and see if they help. Sorry, forgot to put the repo URL: https://github.com/fabioestevam/meta-imx8mmevk-bsp/tree/kirkstone/recipes-kernel/linux/linux-stable/6.1/imx8mmevk
Re: [PATCH v12 00/18] drm: Add Samsung MIPI DSIM bridge
Hi Rasmus, On Tue, Feb 14, 2023 at 7:55 AM Rasmus Villemoes wrote: > Well, the data sheet for the dsi86 says up to 750MHz DSI HS clock, and > if the value specified in samsung,burst-clock-frequency is twice the DSI > HS clk, I suppose I should be good up to 1.5GHz? I have tried many > different values, but I never seem to get anything through; I think I'm > missing some piece. > > So now I've tried to use these patches on the imx8mp-evk with the > mipi->hdmi accessory from NXP, just to see if I can ever get any > graphics through the mipi interface. And there the story is the same: > the adv7535 bridge gets probed, and can read out the edid from the > monitor over hdmi. And while the mipi block and the bridge seem to > attach to each other, I still don't get any output. > > Do any of you happen to have this working on the imx8mp-evk, and if so, > can you share the .dts updates you've done and how exactly you test the > graphics? I don't have access to an imx8mp-evk, but I tested the ADV7535 MIPI to HDMI daughter card on an imx8mm-evk. Some extra ADV7535 patches were needed. Please check patches 0020-0023 and see if they help.
Re: [PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge
Hi Jagan, On Thu, Jan 19, 2023 at 2:59 PM Jagan Teki wrote: > There are two patch series prior to this need to apply. > > https://patchwork.kernel.org/project/dri-devel/patch/20221212145745.15387-1-ja...@amarulasolutions.com/ > https://patchwork.kernel.org/project/dri-devel/cover/20221212182923.29155-1-ja...@amarulasolutions.com/ Would it make sense to re-submit these two patches as part of your series?
Re: [PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge
Hi Jagan, On Thu, Jan 5, 2023 at 7:24 AM Jagan Teki wrote: > Does anyone have any other comments on this? I would like to send v11 > with a few nits on v10. Please let me know. What is blocking this series to be applied?
Re: [PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge
On Fri, Jan 6, 2023 at 11:34 AM Adam Ford wrote: > I got it working on an LVDS display that I have, but I didn't get it > working on the HDMI bridge. Since we have a few tested-by people, > it'd be nice to see this integrated so we can work on ading more > functionality Agreed. Hopefully, this series can be applied soon so we don't miss another cycle.
Re: Driver for CFAF240320X0-020T display
Hi Noralf, On Fri, Dec 16, 2022 at 9:30 AM Noralf Trønnes wrote: > There is a DRM driver that can be used with all of these controllers: > drivers/gpu/drm/tiny/panel-mipi-dbi.c. It uses a firmware file for the > init commands. > > Binding: > Documentation/devicetree/bindings/display/panel/panel-mipi-dbi-spi.yaml > Wiki: https://github.com/notro/panel-mipi-dbi/wiki Thanks for your suggestion. I was able to get the CFAF240320X0-020T display to work with the panel-mipi-dbi.c driver. You did a great job on this driver and wiki! Cheers
Re: [PATCH] drm/msm/a2xx: support loading legacy (iMX) firmware
Hi Dmitry, On Sun, Jan 1, 2023 at 12:58 PM Dmitry Baryshkov wrote: > > Support loading A200 firmware generated from the iMX firmware header > files. The firmware lacks protection support, however it allows GPU to > function properly while using the firmware files with clear license > which allows redistribution. Could you please share more details as to what firmware you are using with the i.MX53? Is it available on the linux-firmare repository? Please advise.
Driver for CFAF240320X0-020T display
Hi, Does anyone know if the Crystalfontz CFAF240320X0-020T display is supported in Linux? https://www.crystalfontz.com/product/cfaf240320x0020t-2inch-240x320-color-tft It uses a Sitronix ST7789V controller. For the ST7789V, there is a drm driver: drivers/gpu/drm/panel/panel-sitronix-st7789v.c and also an fbtft one: drivers/staging/fbtft/fb_st7789v.c Documentation/devicetree/bindings/display/panel/sitronix,st7789v.yaml shows a remote-endpoint property, so I assume this only works when st7789v is connected via RGB parallel, correct? On my board, the CFAF240320X0-020T is connected via SPI only, so I guess I should try the fbtdt driver? The arch/riscv/boot/dts/canaan/sipeed_maix_* boards use compatible = "sitronix,st7789v" Do these boards have st7789v functional? Are they using the fbtft or drm driver? Appreciate any suggestions. Thanks, Fabio Estevam
Re: [PATCH v9 10/18] drm: bridge: samsung-dsim: Init exynos host for first DSI transfer
Hi Jagan, On Tue, Dec 13, 2022 at 7:40 AM Jagan Teki wrote: > https://gitlab.com/openedev/kernel/-/commits/imx8mm-dsi-v10 Please preserve the authorship of the patches. This one is from Marek Vasut: https://gitlab.com/openedev/kernel/-/commit/e244fa552402caebcf48cd6710fd387429f7f680 but in your tree, it appears as if you were the original author. Please double-check globally.
Re: [PATCH] drm/etnaviv: Remove redundant dev_err()
On Sun, Dec 11, 2022 at 3:02 PM Kang Minchul wrote:
>
> Function dev_err() is redundant because platform_get_irq()
> already prints an error.
>
> Signed-off-by: Kang Minchul
> ---
> drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
> b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
> index a31eeff2b297..097fa9034ee8 100644
> --- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
> +++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
> @@ -1771,7 +1771,6 @@ static int etnaviv_gpu_platform_probe(struct
> platform_device *pdev)
> /* Get Interrupt: */
> gpu->irq = platform_get_irq(pdev, 0);
> if (gpu->irq < 0) {
> - dev_err(dev, "failed to get irq: %d\n", gpu->irq);
> return gpu->irq;
> }
If the dev_err() line is removed, then the { and } should be removed as well.
Re: [PATCH v4 01/10] drm: bridge: cadence: convert mailbox functions to macro functions
Hi Sandor, On Mon, Nov 21, 2022 at 4:27 AM Sandor Yu wrote: > > Mailbox access functions could be share to other mhdp driver and > HDP-TX HDMI/DP PHY drivers, move those functions to head file > include/drm/bridge/cdns-mhdp-mailbox.h and convert them to > macro functions. What is the reason for converting the functions to macro?
Re: [PATCH v2 2/4] usb: gadget: hid: Convert to use list_count()
On Mon, Nov 14, 2022 at 1:22 PM Andy Shevchenko wrote: > > The list API now provides the list_count() to help with counting > existing nodes in the list. Uilise it. s/Uilise/Utilise
