On 11/15/23 2:38 AM, Dmitry Baryshkov wrote:
On Wed, 15 Nov 2023 at 01:00, Jonathan Marek wrote:
Make it clear why the pkt_per_line value is being "divided by 2".
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 2 ++
1 file changed, 2 insertions(+)
di
On 11/15/23 3:53 AM, Dmitry Baryshkov wrote:
On Wed, 15 Nov 2023 at 01:00, Jonathan Marek wrote:
Add necessary DPU changes for DSC to work with DSI video mode.
Note this changes the logic to enable HCTL to match downstream, it will
now be enabled for the no-DSC no-widebus case.
Signed-off
For the bonded DSI case, DSC pic_width and timing calculations should use
the width of a single panel instead of the total combined width.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/dsi/dsi.h | 3 ++-
drivers/gpu/drm/msm/dsi/dsi_host.c| 20 +++-
drivers
Add a dsc_slice_per_pkt field to mipi_dsi_device struct and the necessary
changes to msm driver to support this field.
Note that the removed "pkt_per_line = slice_per_intf * slice_per_pkt"
comment is incorrect.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/dsi/dsi_h
Make it clear why the pkt_per_line value is being "divided by 2".
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
b/drivers/gpu/drm/msm/dsi/dsi_host.c
index 66f198e21a7e..84
Video mode DSC won't work if this field is not set correctly. Set it to fix
video mode DSC (for slice_per_pkt==1 cases at least).
Fixes: 08802f515c3 ("drm/msm/dsi: Add support for DSC configuration")
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 3 +++
1
The value returned by msm_dsi_wide_bus_enabled() doesn't match what the
driver is doing in video mode. Fix that by actually enabling widebus for
video mode.
Fixes: efcbd6f9cdeb ("drm/msm/dsi: Enable widebus for DSI")
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/dsi
Add necessary DPU changes for DSC to work with DSI video mode.
Note this changes the logic to enable HCTL to match downstream, it will
now be enabled for the no-DSC no-widebus case.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 2 +-
drivers/gpu/drm
v2: added new patches (first two patches) to get DSC video mode running with
the upstream DPU driver (tested with the vtdr6130 panel)
Jonathan Marek (6):
drm/msm/dpu: fix video mode DSC for DSI
drm/msm/dsi: set video mode widebus enable bit when widebus is enabled
drm/msm/dsi: set
bonded DSI.
I am also using DPU 6+ but I won't be posting patches for DPU to support
this as I am not using the upstream DPU codebase.
On 2023-11-14 12:42:16, Jonathan Marek wrote:
For the bonded DSI case, DSC pic_width and timing calculations should use
the width of a single panel in
For the bonded DSI case, DSC pic_width and timing calculations should use
the width of a single panel instead of the total combined width.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/dsi/dsi.h | 3 ++-
drivers/gpu/drm/msm/dsi/dsi_host.c| 20 +++-
drivers
Add a dsc_slice_per_pkt field to mipi_dsi_device struct and the necessary
changes to msm driver to support this field.
Note that the removed "pkt_per_line = slice_per_intf * slice_per_pkt"
comment is incorrect.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/dsi/dsi_h
Make it clear why the pkt_per_line value is being "divided by 2".
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
b/drivers/gpu/drm/msm/dsi/dsi_host.c
index bddc57726fb9..2e
Video mode DSC won't work if this field is not set correctly. Set it to fix
video mode DSC (for slice_per_pkt==1 cases at least).
Fixes: 08802f515c3 ("drm/msm/dsi: Add support for DSC configuration")
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 3 +++
1
Use the same value as the downstream driver. This change is needed for CPHY
mode to work correctly.
Fixes: 8b034e6771113 ("drm/msm/dsi: add support for DSI-PHY on SM8550")
Signed-off-by: Jonathan Marek
---
v2: fixed the Fixes: line
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 2
Use the same value as the downstream driver. This change is needed for CPHY
mode to work correctly.
Fixes: 93f0ca6fd61c ("drm/msm/dsi: fix VREG_CTRL_1 value for 4nm cphy")
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 2 +-
1 file changed, 1 inser
sm8550 has 16 vbif clients.
This fixes the extra 2 clients (DMA4/DMA5) not having their memtype
initialized. This fixes DMA4/DMA5 planes not displaying correctly.
Fixes: efcd0107 ("drm/msm/dpu: add support for SM8550")
Signed-off-by: Jonathan Marek
---
.../msm/disp/dpu1/catalog/dpu_
Note that with this, DMA4/DMA5 are still non-functional, but at least
display *something* in modetest instead of nothing or underflow.
Fixes: efcd0107727c ("drm/msm/dpu: add support for SM8550")
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 8 ++
On 5/17/23 3:08 PM, Konrad Dybcio wrote:
On 17.05.2023 20:09, Jonathan Marek wrote:
AFAIK GMU_ALWAYS_ON_COUNTER does not have the same value as
CP_ALWAYS_ON_COUNTER (only the same frequency), so changing this would break
userspace expecting to be able to compare the value returned by
AFAIK GMU_ALWAYS_ON_COUNTER does not have the same value as
CP_ALWAYS_ON_COUNTER (only the same frequency), so changing this would
break userspace expecting to be able to compare the value returned by
MSM_PARAM_TIMESTAMP with CP timestamp values.
On 5/17/23 12:50 PM, Konrad Dybcio wrote:
Use
This won't work because a2xx freedreno userspace expects to own all the
perfcounters.
This will break perfcounters for userspace, and when userspace isn't
using perfcounters, this won't count correctly because userspace writes
0 to CP_PERFMON_CNTL at the start of every submit.
On 2/23/23 5:5
This patch broke drm/msm in 6.2-rc1 for me. drm_sched_entity_destroy()
never returns when exiting a process from gdb if it has a drm/msm fd
opened (if the fd is closed normally then it doesn't have this problem).
agetable")
Signed-off-by: Jonathan Marek
---
v2: use for_each_sgtable_sg and update commit message
drivers/gpu/drm/msm/msm_iommu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/msm_iommu.c b/drivers/gpu/drm/msm/msm_iommu.c
index bcaddbba564df..a54ed354578b5
create a local pagetable")
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/msm_iommu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/msm_iommu.c b/drivers/gpu/drm/msm/msm_iommu.c
index bcaddbba564df..22935ef26a3a1 100644
--- a/drivers/gpu/drm/ms
pport the GPU core clock and turning on the GX rail, which is normally
offloaded to the GMU).
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/Makefile| 1 +
drivers/gpu/drm/msm/adreno/a7xx_gpu.c | 777
drivers/gpu/drm/msm/adreno/a7xx_gpu.h
Adds a7xx changes for the kernel driver.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a7xx.xml.h | 666
drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h | 63 +-
2 files changed, 716 insertions(+), 13 deletions(-)
create mode 100644 drivers/gpu/drm/msm
The high half of 64-bit registers is always at +1 offset, so change these
helpers to be more convenient by removing the unnecessary argument.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 3 +--
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 27
These will be used by a7xx, so move them to common code. A6XX_ prefix is
kept because the generic ADRENO_ is already in use.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 17 -
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 6 ++
2 files changed, 6
pport the GPU core clock and turning on the GX rail, which is normally
offloaded to the GMU).
Register updates:
https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15602
Jonathan Marek (4):
drm/msm/adreno: move a6xx CP_PROTECT macros to common code
drm/msm/adreno: use a single reg
Add the required changes to support 7nm pll/phy in CPHY mode.
This adds a "qcom,dsi-phy-cphy-mode" property for the PHY node to enable
the CPHY mode.
Signed-off-by: Jonathan Marek
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/dsi/dsi.xml.h | 2 +
drivers/gpu/d
Document a new phy-type property which will be used to determine whether
the phy should operate in D-PHY or C-PHY mode.
Signed-off-by: Jonathan Marek
Reviewed-by: Laurent Pinchart
---
.../devicetree/bindings/display/msm/dsi-phy-7nm.yaml | 5 +
include/dt-bindings/phy/phy.h
These got lost when going from .txt to .yaml bindings, add them back.
Signed-off-by: Jonathan Marek
---
.../bindings/display/msm/dsi-phy-7nm.yaml | 66 +++
1 file changed, 66 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml
l bindings
- changed binding to "phy-type = ;"
v4:
- PHY_TYPE_{DPHY,CPHY} instead of PHY_TYPE_DSI_{DPHY,CPHY}
- use enum/default for phy-type property
- remove a stray semicolon in dts example
Jonathan Marek (3):
dt-bindings: msm: dsi: add missing 7nm bindings
dt-bindings: msm: ds
On 6/16/21 1:50 AM, rajee...@codeaurora.org wrote:
On 03-06-2021 01:32, rajee...@codeaurora.org wrote:
On 02-06-2021 02:28, Rob Herring wrote:
On Mon, May 31, 2021 at 07:03:53PM +0530, Rajeev Nandan wrote:
+
+properties:
+ compatible:
+ oneOf:
+ - const: qcom,dsi-phy-7nm
When woul
Add the required changes to support 7nm pll/phy in CPHY mode.
This adds a "qcom,dsi-phy-cphy-mode" property for the PHY node to enable
the CPHY mode.
Signed-off-by: Jonathan Marek
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/dsi/dsi.xml.h | 2 +
drivers/gpu/d
Document a new phy-type property which will be used to determine whether
the phy should operate in D-PHY or C-PHY mode.
Signed-off-by: Jonathan Marek
---
.../devicetree/bindings/display/msm/dsi-phy-7nm.yaml | 4
include/dt-bindings/phy/phy.h | 2
These got lost when going from .txt to .yaml bindings, add them back.
Signed-off-by: Jonathan Marek
---
.../bindings/display/msm/dsi-phy-7nm.yaml | 66 +++
1 file changed, 66 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml
l bindings
- changed binding to "phy-mode = ;"
Jonathan Marek (3):
dt-bindings: msm: dsi: add missing 7nm bindings
dt-bindings: msm: dsi: document phy-type property for 7nm dsi phy
drm/msm/dsi: support CPHY mode for 7nm pll/phy
.../bindings/display/msm/dsi-phy-7nm.yaml | 70 ++
On 6/8/21 1:27 PM, Jonathan Marek wrote:
downstream msm-5.14 kernel added a write to this register, so match that.
Note: this should say msm-5.4 (msm-5.14 is not a thing)
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 4 +++-
drivers/gpu/drm/msm/adreno
g GMU allocations, additional register init,
dummy hfi BW table, cp protect list, entry in gpulist table, hwcg table,
updated a6xx_ucode_check_version check.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a6xx.xml.h | 4 +
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 32 +++-
driver
See downstream's "disable_tseskip" flag.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
ind
downstream msm-5.14 kernel added a write to this register, so match that.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 4 +++-
drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h | 2 ++
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm
SM8250 AOP firmware already sets up PDC registers for us, and it only needs
to be enabled. This path will be used for other newer GPUs.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 21 -
1 file changed, 16 insertions(+), 5 deletions(-)
diff
These aren't used by anything anymore.
Signed-off-by: Jonathan Marek
Reviewed-by: Akhil P Oommen
---
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 3 ---
drivers/gpu/drm/msm/msm_gpu.h | 9 -
2 files changed, 12 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu
already picked up by robclark
- added patches for missing PC_DBG_ECO_CNTL/GMU_CX_FALNEXT_INTF settings
- changed a660_protect to exclude CP_PERFCTR_CP_SEL
- removed 635 id from adreno_is_a650_family
- squashed a660 patches
Jonathan Marek (5):
drm/msm: remove unused icc_path/ocmem_icc_path
drm
On 5/31/21 11:05 AM, Akhil P Oommen wrote:
On 5/13/2021 10:44 PM, Jonathan Marek wrote:
...
@@ -519,7 +519,7 @@ static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu)
if (!pdcptr)
goto err;
- if (adreno_is_a650(adreno_gpu))
+ if (adreno_is_a650(adreno_gpu
On 5/31/21 3:24 AM, Akhil P Oommen wrote:
On 5/13/2021 10:43 PM, Jonathan Marek wrote:
SM8250 AOP firmware already sets up PDC registers for us, and it only
needs
to be enabled. This path will be used for other newer GPUs.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno
On 5/3/21 1:11 PM, Rob Herring wrote:
On Fri, Apr 23, 2021 at 01:24:40PM -0400, Jonathan Marek wrote:
Document qcom,dsi-phy-cphy-mode option, which can be used to control
whether DSI will operate in D-PHY (default) or C-PHY mode.
Given this is a standard MIPI thing, I think this needs to be a
Add a660 hwcg table, ported over from downstream.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 53 ++
drivers/gpu/drm/msm/adreno/adreno_device.c | 1 +
drivers/gpu/drm/msm/adreno/adreno_gpu.h| 2 +-
3 files changed, 55 insertions(+), 1
Accept all SQE firmware versions for A660.
Re-organize the function a bit and print an error message for unexpected
GPU IDs instead of failing silently.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 36 +--
1 file changed, 17 insertions
g GMU allocations, additional register init,
dummy hfi BW table, cp protect list, entry in gpulist table.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a6xx.xml.h | 4 ++
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 32 +++---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c
ned-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 909e3ff08f89..ff3c328604f8 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_g
Update CP_PROTECT register programming based on downstream.
A6XX_PROTECT_RW is renamed to A6XX_PROTECT_NORDWR to make things aligned
and also be more clear about what it does.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 143 +++---
drivers/gpu
Value was shifted in the wrong direction, resulting in the field always
being zero, which is incorrect for A650.
Fixes: d0bac4e9cd66 ("drm/msm/a6xx: set ubwc config for A640 and A650")
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 +-
1 file changed, 1
SM8250 AOP firmware already sets up PDC registers for us, and it only needs
to be enabled. This path will be used for other newer GPUs.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 21 -
1 file changed, 16 insertions(+), 5 deletions(-)
diff
These aren't used by anything anymore.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 3 ---
drivers/gpu/drm/msm/msm_gpu.h | 9 -
2 files changed, 12 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
b/drivers/gpu/drm/msm/a
Add support for Adreno 660 to the drm/msm driver. Very similar to A650
on the kernel side.
v2:
- added AOP PDC path for a650 and use it for a660 too
- fix UBWC config for a650 (also affects a660)
- add CP_PROTECT update, and corresponding a660 settings in A660 patch
Jonathan Marek (8):
drm
Add a660 hwcg table, ported over from downstream.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 53 ++
drivers/gpu/drm/msm/adreno/adreno_device.c | 1 +
drivers/gpu/drm/msm/adreno/adreno_gpu.h| 2 +-
3 files changed, 55 insertions(+), 1
Accept all SQE firmware versions for A660.
Re-organize the function a bit and print an error message for unexpected
GPU IDs instead of failing silently.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 36 +--
1 file changed, 17 insertions
g GMU allocations, additional register init,
dummy hfi BW table, entry in gpulist table.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a6xx.xml.h | 4 +++
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 32 +++--
drivers/gpu/drm/msm/adreno/a6xx_gpu.c
ned-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 727d111a413f..01bd31b3c504 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_g
These aren't used by anything anymore.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 3 ---
drivers/gpu/drm/msm/msm_gpu.h | 9 -
2 files changed, 12 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
b/drivers/gpu/drm/msm/a
Add support for Adreno 660 to the drm/msm driver. Very similar to A650
on the kernel side.
Jonathan Marek (5):
drm/msm: remove unused icc_path/ocmem_icc_path
drm/msm/a6xx: avoid shadow NULL reference in failure path
drm/msm/a6xx: add support for Adreno 660 GPU
drm/msm/a6xx: update
mmu500 targets don't have a "cx_mem" region, set llc_mmio to NULL in that
case to avoid the IS_ERR() condition in a6xx_llc_activate().
Fixes: 3d247123b5a1 ("drm/msm/a6xx: Add support for using system cache on
MMU500 based targets")
Signed-off-by: Jonathan Marek
---
d
There shouldn't be any reason to ever use uncached over writecombine,
so just use writecombine for MSM_BO_UNCACHED.
Note: userspace never used MSM_BO_UNCACHED anyway
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/msm_gem.c | 4 +---
include/uapi/drm/msm_drm.h| 2 +-
2 files ch
Add a new cache mode for creating coherent host-cached BOs.
Signed-off-by: Jonathan Marek
Reviewed-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/adreno_device.c | 1 +
drivers/gpu/drm/msm/msm_drv.c | 3 ++-
drivers/gpu/drm/msm/msm_drv.h | 1 +
drivers/gpu/drm/msm
Use the same logic as the userspace mapping.
This fixes msm_rd with cached BOs.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/msm_gem.c | 19 +++
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_gem.c b/drivers/gpu/drm/msm/msm_gem.c
msm_gem_get_vaddr() currently always maps as writecombine, so use the right
flag instead of relying on broken behavior (things don't actually work if
they are mapped as uncached).
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 4 ++--
drivers/gpu/drm/msm/a
Add support for MSM_BO_CACHED_COHERENT, a coherent version of MSM_BO_CACHED
which is implemented by setting the IOMMU_CACHE flag.
Jonathan Marek (5):
drm/msm: remove unnecessary mmap logic for cached BOs
drm/msm: replace MSM_BO_UNCACHED with MSM_BO_WC for internal objects
drm/msm: use the
No one knows what this is for anymore, so just remove it.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/msm_gem.c | 15 +++
1 file changed, 3 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_gem.c b/drivers/gpu/drm/msm/msm_gem.c
index b199942266a2
Increase the minor version to indicate that MSM_PARAM_SUSPENDS is supported.
Fixes: 3ab1c5cc3939 ("drm/msm: Add param for userspace to query suspend count")
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/msm_drv.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
di
Add the required changes to support 7nm pll/phy in CPHY mode.
This adds a "qcom,dsi-phy-cphy-mode" property for the PHY node to enable
the CPHY mode.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/dsi/dsi.xml.h | 2 +
drivers/gpu/drm/msm/dsi/dsi_host.c
Document qcom,dsi-phy-cphy-mode option, which can be used to control
whether DSI will operate in D-PHY (default) or C-PHY mode.
Signed-off-by: Jonathan Marek
---
Documentation/devicetree/bindings/display/msm/dsi.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree
Add the required changes to support 7nm pll/phy in CPHY mode.
This adds a "qcom,dsi-phy-cphy-mode" property for the PHY node to enable
the CPHY mode.
v2:
- rebased on DSI PHY reworks
- reworked getting cphy_mode in dsi_host.c
- documentation change in separate patch
Jonathan Marek
Tested-by: Jonathan Marek
On 4/11/21 8:01 PM, Dmitry Baryshkov wrote:
msm_dsi_phy_get_clk_provider() always returns two provided clocks, so
return 0 instead of returning incorrect -EINVAL error code.
Fixes: 5d13459650b3 ("drm/msm/dsi: push provided clocks handling into a generic
On 3/5/21 5:45 PM, Dmitry Baryshkov wrote:
On 15/02/2021 19:27, Jonathan Marek wrote:
Add the required changes to support 7nm pll/phy in CPHY mode.
This adds a "qcom,dsi-phy-cphy-mode" property for the PHY node to enable
the CPHY mode.
Signed-off-by: Jonathan Marek
Other that fe
On 3/5/21 4:48 PM, Rob Herring wrote:
On Mon, Feb 15, 2021 at 11:27:44AM -0500, Jonathan Marek wrote:
Add the required changes to support 7nm pll/phy in CPHY mode.
This adds a "qcom,dsi-phy-cphy-mode" property for the PHY node to enable
the CPHY mode.
Signed-off-by: Jona
On 2/17/21 3:18 PM, Rob Clark wrote:
On Wed, Feb 17, 2021 at 11:08 AM Jordan Crouse wrote:
On Wed, Feb 17, 2021 at 07:14:16PM +0530, Akhil P Oommen wrote:
On 2/17/2021 8:36 AM, Rob Clark wrote:
On Tue, Feb 16, 2021 at 12:10 PM Jonathan Marek wrote:
Ignore nvmem_cell_get() EOPNOTSUPP
Ignore nvmem_cell_get() EOPNOTSUPP error in the same way as a ENOENT error,
to fix the case where the kernel was compiled without CONFIG_NVMEM.
Fixes: fe7952c629da ("drm/msm: Add speed-bin support to a618 gpu")
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a6xx
On 2/16/21 11:54 AM, Dmitry Baryshkov wrote:
On Mon, 15 Feb 2021 at 19:25, Jonathan Marek wrote:
The driver already has support for sm8150/sm8250, but the compatibles were
never added.
Also inverse the non-mdp4 condition in add_display_components() to avoid
having to check every new
Add the required changes to support 7nm pll/phy in CPHY mode.
This adds a "qcom,dsi-phy-cphy-mode" property for the PHY node to enable
the CPHY mode.
Signed-off-by: Jonathan Marek
---
.../devicetree/bindings/display/msm/dsi.txt | 1 +
drivers/gpu/drm/msm/dsi/dsi.c
The driver already has support for sm8150/sm8250, but the compatibles were
never added.
Also inverse the non-mdp4 condition in add_display_components() to avoid
having to check every new compatible in the condition.
Signed-off-by: Jonathan Marek
---
Documentation/devicetree/bindings/display
Add sm8150/sm8250 compatibles to drm/msm and fix the sm8250
display nodes.
v2: do not remove mmcx-supply from dispcc node
v3: remove references to dp_phy (missed this in v2, sorry for the spam)
Jonathan Marek (2):
drm/msm: add compatibles for sm8150/sm8250 display
arm64: dts: qcom: sm8250
The driver already has support for sm8150/sm8250, but the compatibles were
never added.
Also inverse the non-mdp4 condition in add_display_components() to avoid
having to check every new compatible in the condition.
Signed-off-by: Jonathan Marek
---
Documentation/devicetree/bindings/display
Add sm8150/sm8250 compatibles to drm/msm and fix the sm8250
display nodes.
v2: do not remove mmcx-supply from dispcc node
Jonathan Marek (2):
drm/msm: add compatibles for sm8150/sm8250 display
arm64: dts: qcom: sm8250: fix display nodes
.../devicetree/bindings/display/msm/dpu.txt | 4
The driver already has support for sm8150/sm8250, but the compatibles were
never added.
Also inverse the non-mdp4 condition in add_display_components() to avoid
having to check every new compatible in the condition.
Signed-off-by: Jonathan Marek
---
Documentation/devicetree/bindings/display
Add sm8150/sm8250 compatibles to drm/msm and fix the sm8250
display nodes.
Jonathan Marek (2):
drm/msm: add compatibles for sm8150/sm8250 display
arm64: dts: qcom: sm8250: fix display nodes
.../devicetree/bindings/display/msm/dpu.txt | 4 +--
arch/arm64/boot/dts/qcom/sm8250.dtsi
The cleanup patch broke a6xx_gmu_clear_oob, fix it by adding the missing
bitshift operation.
Fixes: 555c50a4a19b ("drm/msm: Clean up GMU OOB set/clear handling")
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletio
On 11/16/20 12:50 PM, Rob Clark wrote:
On Mon, Nov 16, 2020 at 9:33 AM Christoph Hellwig wrote:
On Sat, Nov 14, 2020 at 03:07:20PM -0500, Jonathan Marek wrote:
qcom's vulkan driver has nonCoherentAtomSize=1, and it looks like
dma_sync_single_for_cpu() does deal in some way with the pa
On 11/14/20 1:46 PM, Rob Clark wrote:
On Sat, Nov 14, 2020 at 8:24 AM Christoph Hellwig wrote:
On Sat, Nov 14, 2020 at 10:17:12AM -0500, Jonathan Marek wrote:
+void msm_gem_sync_cache(struct drm_gem_object *obj, uint32_t flags,
+ size_t range_start, size_t range_end
.
Jonathan Marek (5):
drm/msm: add MSM_BO_CACHED_COHERENT
dma-direct: add dma_direct_bypass() to force direct ops
drm/msm: call dma_direct_bypass()
drm/msm: add DRM_MSM_GEM_SYNC_CACHE for non-coherent cache maintenance
drm/msm: bump up the uapi version
drivers/gpu/drm/msm/Kconfig
Always use direct dma ops and no swiotlb.
Note: arm-smmu-qcom already avoids creating iommu dma ops, but not
everything uses arm-smmu-qcom and this also sets the dma mask.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/Kconfig | 1 +
drivers/gpu/drm/msm/msm_drv.c | 8 +---
2 files
On 11/14/20 2:39 PM, Rob Clark wrote:
On Sat, Nov 14, 2020 at 10:58 AM Jonathan Marek wrote:
On 11/14/20 1:46 PM, Rob Clark wrote:
On Sat, Nov 14, 2020 at 8:24 AM Christoph Hellwig wrote:
On Sat, Nov 14, 2020 at 10:17:12AM -0500, Jonathan Marek wrote:
+void msm_gem_sync_cache(struct
Add a new cache mode for creating coherent host-cached BOs.
Signed-off-by: Jonathan Marek
Reviewed-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/adreno_device.c | 1 +
drivers/gpu/drm/msm/msm_drv.h | 1 +
drivers/gpu/drm/msm/msm_gem.c | 8
include/uapi/drm
This makes it possible to use the non-coherent cached MSM_BO_CACHED mode,
which otherwise doesn't provide any method for cleaning/invalidating the
cache to sync with the device.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/msm_drv.c | 21 +
drivers/gpu/dr
Increase the minor version to indicate the presence of new features.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/msm_drv.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index 3f17acdf6594
Increase the minor version to indicate the presence of new features.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/msm_drv.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index 3f17acdf6594
This makes it possible to use the non-coherent cached MSM_BO_CACHED mode,
which otherwise doesn't provide any method for cleaning/invalidating the
cache to sync with the device.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/msm_drv.c | 21 +
drivers/gpu/dr
Add a new cache mode for creating coherent host-cached BOs.
Signed-off-by: Jonathan Marek
Reviewed-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/adreno_device.c | 1 +
drivers/gpu/drm/msm/msm_drv.h | 1 +
drivers/gpu/drm/msm/msm_gem.c | 8
include/uapi/drm
dma_ops_bypass part,
this is what I came up with reading the emails.
Jonathan Marek (5):
drm/msm: add MSM_BO_CACHED_COHERENT
dma-direct: add dma_direct_bypass() to force direct ops
drm/msm: call dma_direct_bypass()
drm/msm: add DRM_MSM_GEM_SYNC_CACHE for non-coherent cache maintenance
drm
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