From: Robert Chiras
The flag MIPI_DSI_CLOCK_NON_CONTINUOUS was wrong used in the DSI driver,
so it was added to this panel, but not necessary.
So, remove this flag since it is not needed.
Signed-off-by: Robert Chiras
---
drivers/gpu/drm/panel/panel-raydium-rm67191.c | 3 +--
1 file changed, 1
From: Robert Chiras
This patch adds support for a new clock 'video_pll' in order to better
set the video_pll clock to a clock-rate that satisfies a mode's clock.
The video PLL, on i.MX8MQ, can drive both DC pixel-clock and DSI phy_ref
clock. When used with a bridge that can drive multiple modes
From: Robert Chiras
Add documentation for a new property: 'fsl,clock-drop-level'.
Signed-off-by: Robert Chiras
---
Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml | 4
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/bridge/nwl
From: Robert Chiras
Add documentation for a new clock 'video_pll'.
Signed-off-by: Robert Chiras
---
Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml
b
From: Robert Chiras
This patch-set adds the new following features to the nwl-dsi bridge driver:
1. Control Video PLL from nwl-dsi driver
Add support for the Video PLL into the nwl-dsi driver, in order
to better control it's rate, depending on the requested video mode.
Controlling the Video
From: Laurentiu Palcu
DCSS needs active low VSYNC and HSYNC. Also, move the input selection in
the probe function, as this will not change at runtime.
Signed-off-by: Laurentiu Palcu
Signed-off-by: Robert Chiras
---
drivers/gpu/drm/bridge/nwl-dsi.c | 24
1 file
From: Robert Chiras
The clock-drop-level is needed in order to add more blanking space needed
by DSI panels when sending DSI commands. One level is the equivalent of
phy_ref rate from the PLL rate. Since the PLL rate is targeted as highest
possible, each level should not get the crtc_clock too
On Mi, 2019-12-04 at 13:06 +0100, Guido Günther wrote:
> Hi Robert,
> On Tue, Dec 03, 2019 at 09:50:03AM +, Robert Chiras wrote:
> >
> > Hi Guido,
> >
> > Since your last revision sent, I've done more tests here and found
> > a
> > few more impro
ontroller found
> on
> i.MX8 SoCs.
>
> It adds support for the i.MX8MQ but the same IP can be found on
> e.g. the i.MX8QXP.
>
> It has been tested on the Librem 5 devkit using mxsfb.
>
> Signed-off-by: Guido Günther
> Co-developed-by: Robert Chiras
> Signed-off-by:
the clk API function for enable/disable the clock. Those functions
are already checking for NULL clk and returning 0 if that's the case.
Signed-off-by: Robert Chiras
Acked-by: Leonard Crestez
Tested-by: Guido Günther
---
drivers/gpu/drm/mxsfb/mxsfb_crtc.c | 8
drivers/gpu/drm/mxsfb
This IP requires full stop and re-start when changing display timings,
but we can change the pixel format while running.
Signed-off-by: Robert Chiras
Tested-by: Guido Günther
---
drivers/gpu/drm/mxsfb/mxsfb_crtc.c | 16 +++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff
Bit 21 can alter the CTRL2_OUTSTANDING_REQS value right after the eLCDIF
is enabled, since it comes up with default value of 1 (this behaviour
has been seen on some imx8 platforms).
In order to fix this, clear CTRL2_OUTSTANDING_REQS bits before setting
its value.
Signed-off-by: Robert Chiras
a better representation (guido)
- Included a patch submitted by Guido, while he was testing my patch-set
Guido Günther (1):
drm/mxsfb: Read bus flags from bridge if present
Mirela Rabulea (1):
drm/mxsfb: Signal mode changed when bpp changed
Robert Chiras (12):
drm/mxsfb: Update mxsfb to sup
The eLCDIF controller has control pin for the external LCD reset pin.
Add support for it and assert this pin in enable and de-assert it in
disable.
Signed-off-by: Robert Chiras
Tested-by: Guido Günther
---
drivers/gpu/drm/mxsfb/mxsfb_crtc.c | 14 ++
drivers/gpu/drm/mxsfb
Some of the registers, like LCDC_CTRL, CTRL2_OUTSTANDING_REQS and
CTRL1_RECOVERY_ON_UNDERFLOW needs to be properly cleared/initialized
for a better start and stop routine.
Signed-off-by: Robert Chiras
Tested-by: Guido Günther
---
drivers/gpu/drm/mxsfb/mxsfb_crtc.c | 12
1 file
Use BIT(x) and GEN_MASK(h, l) for better representation the inside of
various registers.
Signed-off-by: Robert Chiras
Tested-by: Guido Günther
---
drivers/gpu/drm/mxsfb/mxsfb_regs.h | 151 ++---
1 file changed, 89 insertions(+), 62 deletions(-)
diff --git
Some of the existing registers in this controller are not defined, but
also not used. Add them to the register definitions, so that they can be
easily used in future improvements or fixes.
Signed-off-by: Robert Chiras
Tested-by: Guido Günther
---
drivers/gpu/drm/mxsfb/mxsfb_regs.h | 15
Add new optional property 'max-memory-bandwidth', to limit the maximum
bandwidth used by the MXSFB_DRM driver.
Signed-off-by: Robert Chiras
Tested-by: Guido Günther
Reviewed-by: Rob Herring
---
Documentation/devicetree/bindings/display/mxsfb.txt | 5 +
1 file changed, 5 insertions
based on input from the user and panel
capabilities.
Save the bus format in crtc->mode.private_flags, so the bridge can
use it.
Signed-off-by: Robert Chiras
Signed-off-by: Mirela Rabulea
Tested-by: Guido Günther
---
drivers/gpu/drm/mxsfb/mxsfb_crtc.c |
in
order to do horizontal crop on the frame buffer processed by the eLCDIF
block.
Signed-off-by: Robert Chiras
Tested-by: Guido Günther
---
drivers/gpu/drm/mxsfb/mxsfb_crtc.c | 79 --
drivers/gpu/drm/mxsfb/mxsfb_drv.c | 1 +
drivers/gpu/drm/mxsfb
From: Mirela Rabulea
Add mxsfb_atomic_helper_check to signal mode changed when bpp changed.
This will trigger the execution of disable/enable on
a modeset with different bpp than the current one.
Signed-off-by: Mirela Rabulea
Signed-off-by: Robert Chiras
Tested-by: Guido Günther
---
drivers
From: Guido Günther
The bridge might have special requirmentes on the input bus. This
is e.g. used by the imx-nwl bridge.
Signed-off-by: Guido Günther
Reviewed-by: Stefan Agner
---
drivers/gpu/drm/mxsfb/mxsfb_crtc.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git
Because of stability issues, we may want to limit the maximum bandwidth
required by the MXSFB (eLCDIF) driver.
Signed-off-by: Robert Chiras
Tested-by: Guido Günther
---
drivers/gpu/drm/mxsfb/mxsfb_drv.c | 48 +++
drivers/gpu/drm/mxsfb/mxsfb_drv.h | 2 ++
2
.
Signed-off-by: Robert Chiras
Tested-by: Guido Günther
---
drivers/gpu/drm/mxsfb/mxsfb_crtc.c | 17 +++---
drivers/gpu/drm/mxsfb/mxsfb_drv.c | 46 +-
drivers/gpu/drm/mxsfb/mxsfb_drv.h | 4 +++-
drivers/gpu/drm/mxsfb/mxsfb_out.c | 26
e.g. the i.MX8QXP.
>
> It has been tested on the Librem 5 devkit using mxsfb.
>
> Signed-off-by: Guido Günther
> Co-developed-by: Robert Chiras
> ---
> drivers/gpu/drm/bridge/Kconfig | 2 +
> drivers/gpu/drm/bridge/Makefile | 1 +
> drivers/gpu/dr
it will allow this driver to dinamically set the
video_pll clock for any kind of mode.
So, for the whole patch-set, you can add:
Tested-by: Robert Chiras
Signed-off-by: Robert Chiras
Best regards,
Robert
On Jo, 2019-08-22 at 12:44 +0200, Guido Günther wrote:
> This adds initial support for the
Hi Leonard,
On Lu, 2019-08-26 at 19:19 +, Leonard Crestez wrote:
> On 26.08.2019 17:35, Stefan Agner wrote:
> >
> > On 2019-08-26 14:05, Guido Günther wrote:
> > >
> > > Hi,
> > > On Wed, Aug 21, 2019 at 01:15:40PM +0300, Robert Chiras wrote:
> &
On Thu, Aug 22, 2019 at 01:18:21PM +, Robert Chiras wrote:
> >
> > Hi Guido,
> >
> > I added my signed-off, plus some comments inline.
> >
> > On Jo, 2019-08-22 at 12:44 +0200, Guido Günther wrote:
> > >
> > > This adds initial support
e.g. the i.MX8QXP.
>
> It has been tested on the Librem 5 devkit using mxsfb.
>
> Signed-off-by: Guido Günther
Signed-off-by: Robert Chiras
> Co-developed-by: Robert Chiras
> ---
> drivers/gpu/drm/bridge/Kconfig | 2 +
> drivers/gpu/drm/bridge/Makefile
based on input from the user and panel
capabilities.
Save the bus format in crtc->mode.private_flags, so the bridge can
use it.
Signed-off-by: Robert Chiras
Signed-off-by: Mirela Rabulea
---
drivers/gpu/drm/mxsfb/mxsfb_crtc.c | 147 ++---
drivers/gpu/drm/mx
changed when bpp changed
Robert Chiras (13):
drm/mxsfb: Update mxsfb to support a bridge
drm/mxsfb: Add defines for the rest of registers
drm/mxsfb: Reset vital registers for a proper initialization
drm/mxsfb: Update register definitions using bit manipulation defines
drm/mxsfb: Update mxsfb
Some of the registers, like LCDC_CTRL, CTRL2_OUTSTANDING_REQS and
CTRL1_RECOVERY_ON_UNDERFLOW needs to be properly cleared/initialized
for a better start and stop routine.
Signed-off-by: Robert Chiras
---
drivers/gpu/drm/mxsfb/mxsfb_crtc.c | 12
1 file changed, 12 insertions
This IP requires full stop and re-start when changing display timings,
but we can change the pixel format while running.
Signed-off-by: Robert Chiras
---
drivers/gpu/drm/mxsfb/mxsfb_crtc.c | 16 +++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mxsfb
Use BIT(x) and GEN_MASK(h, l) for better representation the inside of
various registers.
Signed-off-by: Robert Chiras
---
drivers/gpu/drm/mxsfb/mxsfb_regs.h | 151 ++---
1 file changed, 89 insertions(+), 62 deletions(-)
diff --git a/drivers/gpu/drm/mxsfb
From: Guido Günther
The bridge might have special requirmentes on the input bus. This
is e.g. used by the imx-nwl bridge.
Signed-off-by: Guido Günther
Reviewed-by: Stefan Agner
---
drivers/gpu/drm/mxsfb/mxsfb_crtc.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git
.
Signed-off-by: Robert Chiras
Tested-by: Guido Günther
---
drivers/gpu/drm/mxsfb/mxsfb_crtc.c | 17 +++---
drivers/gpu/drm/mxsfb/mxsfb_drv.c | 46 +-
drivers/gpu/drm/mxsfb/mxsfb_drv.h | 4 +++-
drivers/gpu/drm/mxsfb/mxsfb_out.c | 26
Bit 21 can alter the CTRL2_OUTSTANDING_REQS value right after the eLCDIF
is enabled, since it comes up with default value of 1 (this behaviour
has been seen on some imx8 platforms).
In order to fix this, clear CTRL2_OUTSTANDING_REQS bits before setting
its value.
Signed-off-by: Robert Chiras
Add new optional property 'max-memory-bandwidth', to limit the maximum
bandwidth used by the MXSFB_DRM driver.
Signed-off-by: Robert Chiras
---
Documentation/devicetree/bindings/display/mxsfb.txt | 5 +
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/display
From: Mirela Rabulea
Add mxsfb_atomic_helper_check to signal mode changed when bpp changed.
This will trigger the execution of disable/enable on
a modeset with different bpp than the current one.
Signed-off-by: Mirela Rabulea
Signed-off-by: Robert Chiras
---
drivers/gpu/drm/mxsfb/mxsfb_drv.c
Because of stability issues, we may want to limit the maximum bandwidth
required by the MXSFB (eLCDIF) driver.
Signed-off-by: Robert Chiras
---
drivers/gpu/drm/mxsfb/mxsfb_drv.c | 48 +++
drivers/gpu/drm/mxsfb/mxsfb_drv.h | 2 ++
2 files changed, 50
in
order to do horizontal crop on the frame buffer processed by the eLCDIF
block.
Signed-off-by: Robert Chiras
---
drivers/gpu/drm/mxsfb/mxsfb_crtc.c | 79 --
drivers/gpu/drm/mxsfb/mxsfb_drv.c | 1 +
drivers/gpu/drm/mxsfb/mxsfb_regs.h | 16
3 files
Some of the existing registers in this controller are not defined, but
also not used. Add them to the register definitions, so that they can be
easily used in future improvements or fixes.
Signed-off-by: Robert Chiras
---
drivers/gpu/drm/mxsfb/mxsfb_regs.h | 15 +++
1 file changed
the clk API function for enable/disable the clock. Those functions
are already checking for NULL clk and returning 0 if that's the case.
Signed-off-by: Robert Chiras
Acked-by: Leonard Crestez
---
drivers/gpu/drm/mxsfb/mxsfb_crtc.c | 8
drivers/gpu/drm/mxsfb/mxsfb_drv.c | 32
The eLCDIF controller has control pin for the external LCD reset pin.
Add support for it and assert this pin in enable and de-assert it in
disable.
Signed-off-by: Robert Chiras
---
drivers/gpu/drm/mxsfb/mxsfb_crtc.c | 14 ++
drivers/gpu/drm/mxsfb/mxsfb_regs.h | 2 ++
2 files
with the '-v' parameter will result
in an astronomical refresh rate (1+ Hz), because of that.
Signed-off-by: Robert Chiras
---
drivers/gpu/drm/mxsfb/mxsfb_drv.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mxsfb/mxsfb_drv.c
b/drivers/gpu/drm/mxsfb
Hi Daniel,
On Mi, 2019-08-14 at 12:44 +0100, Daniel Stone wrote:
> Hi Robert,
>
> On Wed, 14 Aug 2019 at 11:49, Robert Chiras
> wrote:
> >
> > + case DRM_FORMAT_BGR565: /* BG16 */
> > + if (mxsfb->devdata->ipversion <
Hi Stefann,
On Mi, 2019-08-14 at 13:25 +0200, Stefan Agner wrote:
> On 2019-08-14 13:14, Robert Chiras wrote:
> >
> > Hi Stefan,
> > On Mi, 2019-08-14 at 13:03 +0200, Stefan Agner wrote:
> > >
> > > On 2019-08-14 12:48, Robert Chiras wrote:
> > &g
Hi Stefan,
On Mi, 2019-08-14 at 13:11 +0200, Stefan Agner wrote:
> On 2019-08-14 12:48, Robert Chiras wrote:
> >
> > Some of the regiters need, like LCDC_CTRL and
> > CTRL2_OUTSTANDING_REQS
> Typo in registers, and there is a need to many.
Thanks, will fix this.
>
&g
Hi Stefan,
On Mi, 2019-08-14 at 13:06 +0200, Stefan Agner wrote:
> On 2019-08-14 12:48, Robert Chiras wrote:
> >
> > Currently, the enable of the axi clock return status is ignored,
> > causing
> > issues when the enable fails then we try to disable it. Therefore,
&g
Hi Stefan,
On Mi, 2019-08-14 at 13:03 +0200, Stefan Agner wrote:
> On 2019-08-14 12:48, Robert Chiras wrote:
> >
> > Add new optional property 'max-res', to limit the maximum supported
> > resolution by the MXSFB_DRM driver.
> I would also mention the reason why we
Use BIT(x) and GEN_MASK(h, l) for better representation the inside of
various registers.
Signed-off-by: Robert Chiras
---
drivers/gpu/drm/mxsfb/mxsfb_regs.h | 151 ++---
1 file changed, 89 insertions(+), 62 deletions(-)
diff --git a/drivers/gpu/drm/mxsfb
.
Signed-off-by: Robert Chiras
Tested-by: Guido Günther
---
drivers/gpu/drm/mxsfb/mxsfb_crtc.c | 17 +++---
drivers/gpu/drm/mxsfb/mxsfb_drv.c | 46 +-
drivers/gpu/drm/mxsfb/mxsfb_drv.h | 4 +++-
drivers/gpu/drm/mxsfb/mxsfb_out.c | 26
Some of the regiters need, like LCDC_CTRL and CTRL2_OUTSTANDING_REQS
needs to be properly cleared and initialized for a better start and stop
routine.
Signed-off-by: Robert Chiras
---
drivers/gpu/drm/mxsfb/mxsfb_crtc.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers
with the '-v' parameter will result
in an astronomical refresh rate (1+ Hz), because of that.
Signed-off-by: Robert Chiras
---
drivers/gpu/drm/mxsfb/mxsfb_drv.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mxsfb/mxsfb_drv.c
b/drivers/gpu/drm/mxsfb
Add new optional property 'max-res', to limit the maximum supported
resolution by the MXSFB_DRM driver.
Signed-off-by: Robert Chiras
---
Documentation/devicetree/bindings/display/mxsfb.txt | 6 ++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/display
Because of stability issues, we may want to limit the maximum resolution
supported by the MXSFB (eLCDIF) driver.
This patch add support for a new property which we can use to impose such
limitation.
Signed-off-by: Robert Chiras
---
drivers/gpu/drm/mxsfb/mxsfb_drv.c | 12 ++--
1 file
This IP requires full stop and re-start when changing display timings,
but we can change the pixel format while running.
Signed-off-by: Robert Chiras
---
drivers/gpu/drm/mxsfb/mxsfb_crtc.c | 16 +++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mxsfb
in
order to do horizontal crop on the frame buffer processed by the eLCDIF
block.
Signed-off-by: Robert Chiras
---
drivers/gpu/drm/mxsfb/mxsfb_crtc.c | 79 --
drivers/gpu/drm/mxsfb/mxsfb_drv.c | 26 -
drivers/gpu/drm/mxsfb/mxsfb_regs.h | 16
the clk API function for enable/disable the clock. Those functions
are already checking for NULL clk and returning 0 if that's the case.
Signed-off-by: Robert Chiras
Acked-by: Leonard Crestez
---
drivers/gpu/drm/mxsfb/mxsfb_crtc.c | 8
drivers/gpu/drm/mxsfb/mxsfb_drv.c | 32
based on input from the user and panel
capabilities.
Save the bus format in crtc->mode.private_flags, so the bridge can
use it.
Signed-off-by: Robert Chiras
Signed-off-by: Mirela Rabulea
---
drivers/gpu/drm/mxsfb/mxsfb_crtc.c | 147 ++---
drivers/gpu/drm/mx
From: Mirela Rabulea
Add mxsfb_atomic_helper_check to signal mode changed when bpp changed.
This will trigger the execution of disable/enable on
a modeset with different bpp than the current one.
Signed-off-by: Mirela Rabulea
Signed-off-by: Robert Chiras
---
drivers/gpu/drm/mxsfb/mxsfb_drv.c
Some of the existing registers in this controller are not defined, but
also not used. Add them to the register definitions, so that they can be
easily used in future improvements or fixes.
Signed-off-by: Robert Chiras
---
drivers/gpu/drm/mxsfb/mxsfb_regs.h | 15 +++
1 file changed
From: Guido Günther
The bridge might have special requirmentes on the input bus. This
is e.g. used by the imx-nwl bridge.
Signed-off-by: Guido Günther
Reviewed-by: Stefan Agner
---
drivers/gpu/drm/mxsfb/mxsfb_crtc.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git
Günther (1):
drm/mxsfb: Read bus flags from bridge if present
Mirela Rabulea (1):
drm/mxsfb: Signal mode changed when bpp changed
Robert Chiras (13):
drm/mxsfb: Update mxsfb to support a bridge
drm/mxsfb: Add defines for the rest of registers
drm/mxsfb: Reset vital register for a proper
The eLCDIF controller has control pin for the external LCD reset pin.
Add support for it and assert this pin in enable and de-assert it in
disable.
Signed-off-by: Robert Chiras
---
drivers/gpu/drm/mxsfb/mxsfb_crtc.c | 14 ++
drivers/gpu/drm/mxsfb/mxsfb_regs.h | 2 ++
2 files
Bit 21 can alter the CTRL2_OUTSTANDING_REQS value right after the eLCDIF
is enabled, since it comes up with default value of 1 (this behaviour
has been seen on some imx8 platforms).
In order to fix this, clear CTRL2_OUTSTANDING_REQS bits before setting
its value.
Signed-off-by: Robert Chiras
On Lu, 2019-07-22 at 11:48 -0600, Rob Herring wrote:
> On Wed, Jun 26, 2019 at 04:32:13PM +0300, Robert Chiras wrote:
> >
> > Add new optional property 'max-res', to limit the maximum supported
> > resolution by the MXSFB_DRM driver.
> Bindings are for h/w descri
On Ma, 2019-08-13 at 12:23 +0200, Guido Günther wrote:
> Hi Robert,
> On Wed, Jun 26, 2019 at 04:32:08PM +0300, Robert Chiras wrote:
> >
> > This patch-set improves the use of eLCDIF block on iMX 8 SoCs (like
> > 8MQ, 8MM
> > and 8QXP). Following, are the new
Hi Guido,
On Jo, 2019-07-11 at 17:04 +0200, Guido Günther wrote:
> Hi Robert,
> On Wed, Jun 26, 2019 at 04:32:08PM +0300, Robert Chiras wrote:
> >
> > This patch-set improves the use of eLCDIF block on iMX 8 SoCs (like
> > 8MQ, 8MM
> > and 8QXP). Following, are th
Because of stability issues, we may want to limit the maximum resolution
supported by the MXSFB (eLCDIF) driver.
This patch add support for a new property which we can use to impose such
limitation.
Signed-off-by: Robert Chiras
---
drivers/gpu/drm/mxsfb/mxsfb_drv.c | 12 ++--
1 file
Add new optional property 'max-res', to limit the maximum supported
resolution by the MXSFB_DRM driver.
Signed-off-by: Robert Chiras
---
Documentation/devicetree/bindings/display/mxsfb.txt | 6 ++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/display
From: Mirela Rabulea
Add mxsfb_atomic_helper_check to signal mode changed when bpp changed.
This will trigger the execution of disable/enable on
a modeset with different bpp than the current one.
Signed-off-by: Mirela Rabulea
Signed-off-by: Robert Chiras
---
drivers/gpu/drm/mxsfb/mxsfb_drv.c
The eLCDIF controller has control pin for the external LCD reset pin.
Add support for it and assert this pin in enable and de-assert it in
disable.
Signed-off-by: Robert Chiras
---
drivers/gpu/drm/mxsfb/mxsfb_crtc.c | 10 --
drivers/gpu/drm/mxsfb/mxsfb_regs.h | 1 +
2 files changed, 9
the clk API function for enable/disable the clock. Those functions
are already checking for NULL clk and returning 0 if that's the case.
Signed-off-by: Robert Chiras
Acked-by: Leonard Crestez
---
drivers/gpu/drm/mxsfb/mxsfb_crtc.c | 8
drivers/gpu/drm/mxsfb/mxsfb_drv.c | 32
in
order to do horizontal crop on the frame buffer processed by the eLCDIF
block.
Signed-off-by: Robert Chiras
---
drivers/gpu/drm/mxsfb/mxsfb_crtc.c | 79 +++---
drivers/gpu/drm/mxsfb/mxsfb_drv.c | 26 -
drivers/gpu/drm/mxsfb/mxsfb_regs.h | 16
of them at maximum capacity (like it is the case on
8MQ, where there are two display controllers: DCSS and eLCDIF).
The rest of the patches are bug-fixes.
Mirela Rabulea (1):
drm/mxsfb: Signal mode changed when bpp changed
Robert Chiras (9):
drm/mxsfb: Update mxsfb to support a bridge
drm
based on input from the user and panel capabilities.
Save the bus format in crtc->mode.private_flags, so the bridge can use
it.
Signed-off-by: Robert Chiras
Signed-off-by: Mirela Rabulea
---
drivers/gpu/drm/mxsfb/mxsfb_crtc.c | 158 ++---
drivers/gpu/drm/mx
Bit 21 can alter the CTRL2_OUTSTANDING_REQS value right after the eLCDIF
is enabled, since it comes up with default value of 1 (this behaviour
has been seen on some imx8 platforms).
In order to fix this, clear CTRL2_OUTSTANDING_REQS bits before setting
its value.
Signed-off-by: Robert Chiras
with the '-v' parameter will result
in an astronomical refresh rate (1+ Hz), because of that.
Signed-off-by: Robert Chiras
---
drivers/gpu/drm/mxsfb/mxsfb_drv.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mxsfb/mxsfb_drv.c
b/drivers/gpu/drm/mxsfb
.
Signed-off-by: Robert Chiras
---
drivers/gpu/drm/mxsfb/mxsfb_crtc.c | 46 +++---
drivers/gpu/drm/mxsfb/mxsfb_drv.c | 46 +-
drivers/gpu/drm/mxsfb/mxsfb_drv.h | 4 +++-
drivers/gpu/drm/mxsfb/mxsfb_out.c | 26
Hi Sam,
On Mi, 2019-06-26 at 13:33 +0200, Sam Ravnborg wrote:
> Hi Robert.
>
> On Wed, Jun 26, 2019 at 01:20:20PM +0300, Robert Chiras wrote:
> >
> > This patch adds Raydium RM67191 TFT LCD panel driver (MIPI-DSI
> > protocol).
> I was about to apply these - but I
Add dt-bindings documentation for Raydium RM67191 DSI panel.
Signed-off-by: Robert Chiras
Reviewed-by: Sam Ravnborg
Reviewed-by: Fabio Estevam
---
.../bindings/display/panel/raydium,rm67191.txt | 41 ++
1 file changed, 41 insertions(+)
create mode 100644
in enable (sam)
*** SUBJECT HERE ***
*** BLURB HERE ***
Robert Chiras (2):
dt-bindings: display: panel: Add support for Raydium RM67191 panel
drm/panel: Add support for Raydium RM67191 panel driver
.../bindings/display/panel/raydium,rm67191.txt | 41 ++
MAINTAINERS
This patch adds Raydium RM67191 TFT LCD panel driver (MIPI-DSI
protocol).
Signed-off-by: Robert Chiras
Reviewed-by: Sam Ravnborg
Reviewed-by: Fabio Estevam
---
MAINTAINERS | 6 +
drivers/gpu/drm/panel/Kconfig | 9 +
drivers/gpu/drm/panel
)
- Fixed copyright statement (daniel)
- Reordered includes (sam)
- Added defines for panel specific color formats (fabio)
- Removed unnecessary tests in enable and unprepare (sam)
- Removed the unnecessary backlight write in enable (sam)
Robert Chiras (2):
dt-bindings: display: panel: Add support
Add dt-bindings documentation for Raydium RM67191 DSI panel.
Signed-off-by: Robert Chiras
Reviewed-by: Sam Ravnborg
---
.../bindings/display/panel/raydium,rm67191.txt | 41 ++
1 file changed, 41 insertions(+)
create mode 100644
Documentation/devicetree/bindings
This patch adds Raydium RM67191 TFT LCD panel driver (MIPI-DSI
protocol).
Signed-off-by: Robert Chiras
Reviewed-by: Sam Ravnborg
---
MAINTAINERS | 6 +
drivers/gpu/drm/panel/Kconfig | 9 +
drivers/gpu/drm/panel/Makefile| 1
Add dt-bindings documentation for Raydium RM67191 DSI panel.
Signed-off-by: Robert Chiras
Reviewed-by: Sam Ravnborg
---
.../bindings/display/panel/raydium,rm67191.txt | 41 ++
1 file changed, 41 insertions(+)
create mode 100644
Documentation/devicetree/bindings
This patch adds Raydium RM67191 TFT LCD panel driver (MIPI-DSI
protocol).
Signed-off-by: Robert Chiras
Reviewed-by: Sam Ravnborg
---
MAINTAINERS | 6 +
drivers/gpu/drm/panel/Kconfig | 9 +
drivers/gpu/drm/panel/Makefile| 1
specific color formats (fabio)
- Removed unnecessary tests in enable and unprepare (sam)
- Removed the unnecessary backlight write in enable (sam)
Robert Chiras (2):
dt-bindings: display: panel: Add support for Raydium RM67191 panel
drm/panel: Add support for Raydium RM67191 panel driver
On Lu, 2019-06-24 at 13:12 -0300, Fabio Estevam wrote:
> Caution: EXT Email
>
> Hi Robert,
>
> On Mon, Jun 24, 2019 at 4:44 AM Robert Chiras
> wrote:
>
> >
> > >
> > > You did not handle the "power" regulator.
> > There is no nee
On Vi, 2019-06-21 at 12:46 -0300, Fabio Estevam wrote:
> Caution: EXT Email
>
> Hi Robert,
>
> On Fri, Jun 21, 2019 at 11:16 AM Robert Chiras > wrote:
>
> >
> > From what I've seen in the schematics, the power lines on the DSI
> > port
> >
Hi Fabio,
Thanks for your feedback. I will handle them all, but for the pm_ops I
have some comments. See inline.
On Vi, 2019-06-21 at 10:59 -0300, Fabio Estevam wrote:
> Hi Robert,
>
> On Thu, Jun 20, 2019 at 10:31 AM Robert Chiras > wrote:
>
> >
> > +fail:
Hi Fabio,
On Vi, 2019-06-21 at 11:00 -0300, Fabio Estevam wrote:
> Hi Robert,
>
> On Thu, Jun 20, 2019 at 10:32 AM Robert Chiras > wrote:
> >
> >
> > Add dt-bindings documentation for Raydium RM67191 DSI panel.
> >
> > Signed-off-by: Ro
This patch adds Raydium RM67191 TFT LCD panel driver (MIPI-DSI
protocol).
Signed-off-by: Robert Chiras
Reviewed-by: Sam Ravnborg
---
MAINTAINERS | 6 +
drivers/gpu/drm/panel/Kconfig | 9 +
drivers/gpu/drm/panel/Makefile| 1
(daniel)
- Reordered includes (sam)
- Added defines for panel specific color formats (fabio)
- Removed unnecessary tests in enable and unprepare (sam)
- Removed the unnecessary backlight write in enable (sam)
Robert Chiras (2):
dt-bindings: display: panel: Add support for Raydium RM67191 panel
Add dt-bindings documentation for Raydium RM67191 DSI panel.
Signed-off-by: Robert Chiras
Reviewed-by: Sam Ravnborg
---
.../bindings/display/panel/raydium,rm67191.txt | 39 ++
1 file changed, 39 insertions(+)
create mode 100644
Documentation/devicetree/bindings
On Mi, 2019-06-19 at 10:28 -0300, Fabio Estevam wrote:
> Caution: EXT Email
>
> Hi Robert,
>
> On Tue, Jun 18, 2019 at 10:31 AM Robert Chiras > wrote:
>
> >
> > +static const struct display_timing rad_default_timing = {
> > + .pixelc
Hi Sam,
On Mi, 2019-06-19 at 15:25 +0200, Sam Ravnborg wrote:
> On Tue, Jun 18, 2019 at 04:30:46PM +0300, Robert Chiras wrote:
> >
> > This patch adds Raydium RM67191 TFT LCD panel driver (MIPI-DSI
> > protocol).
> >
> > Signed-off-by: Robert Chiras
> Pl
On Mi, 2019-06-19 at 10:21 -0300, Fabio Estevam wrote:
> Caution: EXT Email
>
> Hi Robert,
>
> On Tue, Jun 18, 2019 at 10:33 AM Robert Chiras > wrote:
>
> >
> > +Optional properties:
> > +- reset-gpios: a GPIO spec for the RST_B GPIO pin
> &g
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