t defaults to 0.
Remove this dead code, simplify the way that enable_psr is handled and
update the module parameter string to match the actual functionality.
Cc: Dhinakaran Pandiyan
Cc: Rodrigo Vivi
Signed-off-by: Ross Zwisler
---
drivers/gpu/drm/i915/i915_drv.h| 1 -
drivers/gpu/drm/i915/i9
On Fri, Dec 21, 2018 at 11:23:07AM -0800, Dhinakaran Pandiyan wrote:
> On Fri, 2018-12-21 at 10:23 -0700, Ross Zwisler wrote:
> > The following commit:
> >
> > commit 2bdd045e3a30 ("drm/i915/psr: Check if VBT says PSR can be
> > enabled.")
> >
>
On Mon, Jul 24, 2017 at 01:25:30PM +0200, Jan Kara wrote:
> > @@ -1658,14 +1658,28 @@ static int insert_pfn(struct vm_area_struct *vma,
> > unsigned long addr,
> > if (!pte)
> > goto out;
> > retval = -EBUSY;
> > - if (!pte_none(*pte))
> > - goto out_unlock;
> > +
On Mon, Jul 24, 2017 at 01:15:31PM +0200, Jan Kara wrote:
> On Sat 22-07-17 09:21:31, Dan Williams wrote:
> > On Fri, Jul 21, 2017 at 3:39 PM, Ross Zwisler
> > wrote:
> > > To be able to use the common 4k zero page in DAX we need to have our PTE
> > > fault path
loads, and it simplifies the DAX code,
removing over 100 lines in total.
This series has passed my targeted testing and a full xfstests run on both
XFS and ext4.
Ross Zwisler (5):
mm: add mkwrite param to vm_insert_mixed()
dax: relocate some dax functions
dax: use common 4k zero page for dax mma
kwrite' is set
insert_pfn() will do the work that was previously done by wp_page_reuse()
as part of the dax_pfn_mkwrite() call path.
***
Signed-off-by: Ross Zwisler
---
Documentation/filesystems/dax.txt | 5 +-
fs/dax.c | 240 --
: Ross Zwisler
---
fs/dax.c | 138 +++
1 file changed, 69 insertions(+), 69 deletions(-)
diff --git a/fs/dax.c b/fs/dax.c
index c844a51..779dc5e 100644
--- a/fs/dax.c
+++ b/fs/dax.c
@@ -121,6 +121,31 @@ static int
Now that we no longer insert struct page pointers in DAX radix trees the
page cache code no longer needs to know anything about DAX exceptional
entries. Move all the DAX exceptional entry definitions from dax.h to
fs/dax.c.
Signed-off-by: Ross Zwisler
Suggested-by: Jan Kara
---
fs/dax.c
e
dax_pfn_mkwrite() call path.
Signed-off-by: Ross Zwisler
---
drivers/dax/device.c| 2 +-
drivers/gpu/drm/exynos/exynos_drm_gem.c | 3 ++-
drivers/gpu/drm/gma500/framebuffer.c| 2 +-
drivers/gpu/drm/msm/msm_gem.c | 3 ++-
drivers/gpu/drm/omapdrm/omap_gem.c
Now that we no longer insert struct page pointers in DAX radix trees we can
remove the special casing for DAX in page_cache_tree_insert(). This also
allows us to make dax_wake_mapping_entry_waiter() local to fs/dax.c,
removing it from dax.h.
Signed-off-by: Ross Zwisler
Suggested-by: Jan Kara
uot;)
They are just unnecessary wrappers that do nothing. Remove them, and
rename the the drm_do_* fault handlers to remove the "do_" since they no
longer have corresponding wrappers.
Signed-off-by: Ross Zwisler
Reviewed-by: Sean Paul
Acked-by: Daniel Vetter
---
Andrew,
I initially posted t
uot;)
They are just unnecessary wrappers that do nothing. Remove them.
Signed-off-by: Ross Zwisler
---
drivers/gpu/drm/drm_vm.c | 28
1 file changed, 4 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/drm_vm.c b/drivers/gpu/drm/drm_vm.c
index bae6e26..e677b11 1006
uot;)
They are just unnecessary wrappers that do nothing. Remove them, and
rename the the drm_do_* fault handlers to remove the "do_" since they no
longer have corresponding wrappers.
Signed-off-by: Ross Zwisler
---
This patch applies cleanly to mmots/master, which is currently at
v4
On Mon, Jan 30, 2017 at 03:09:39PM -0700, Ross Zwisler wrote:
> This patch applies cleanly to mmots/master, which is currently at
> v4.10-rc5-mmots-2017-01-26-15-49.
Which may not be what you want... The reason I was looking at this code was
because it was recently changed by Dave Ji
; Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92501
> Testcase: gem_tiled_partial_pwrite_pread/read
> Signed-off-by: Chris Wilson
> Cc: Ross Zwisler
> Cc: H. Peter Anvin
> Cc: Imre Deak
> Cc: Daniel Vetter
> Cc: dri-devel at lists.freedesktop.org
> ---
> arch/x86/include/asm
On Wed, 2015-02-18 at 13:02 +0100, Christian König wrote:
> Well, what the patch does is just changing where buffers are placed in
> memory. E.g. now we place the buffer at the end of memory as well.
>
> So I can imagine at least three possible causes for the issues you see:
> 1. We haven't impl
On Sat, 2015-02-14 at 06:25 +, Deucher, Alexander wrote:
> > -Original Message-
> > From: Ross Zwisler [mailto:ross.zwisler at linux.intel.com]
> > Sent: Friday, February 13, 2015 10:55 PM
> > To: Michel Dänzer
> > Cc: linux-kernel at
On Fri, 2015-02-13 at 11:41 +0900, Michel Dänzer wrote:
> On 13.02.2015 05:30, Ross Zwisler wrote:
> > This patch reverts the changes made in this commit:
> >
> > deadcb36f49b ("drm/radeon: Use two-ended allocation by size, v2")
> >
> > That patch
f the time.
This patch applies cleanly to v3.19, and fixes the screen flicker issue
on my system. Here is the hardware that I'm using (from lspci):
01:00.0 VGA compatible controller: Advanced Micro Devices, Inc.
[AMD/ATI] Seymour [Radeon HD 6400M/7400M Series]
Signed-off-by: Ross Zwisler
Cc
On Wed, 2014-11-12 at 19:25 -0800, Andy Lutomirski wrote:
> On 11/11/2014 10:43 AM, Ross Zwisler wrote:
> > Add support for the new pcommit instruction. This instruction was
> > announced in the document "Intel Architecture Instruction Set Extensions
> > Programming
On Wed, 2014-11-12 at 15:12 +0100, Borislav Petkov wrote:
> On Wed, Nov 12, 2014 at 01:38:45PM +, Anvin, H Peter wrote:
> > No, it doesn't. x86 requires 3.4+ at a minimum.
>
> The only test I see is:
>
> #if GCC_VERSION < 30200
> # error Sorry, your compiler is too old - please upgrade it.
>
On Tue, 2014-11-11 at 20:46 +0100, Borislav Petkov wrote:
> On Tue, Nov 11, 2014 at 12:40:00PM -0700, Ross Zwisler wrote:
> > Yep, it's weird, I know. :)
>
> But sure, saving opcode space, makes sense to me.
>
> Btw, I'd still be interested about this:
>
>
On Tue, 2014-11-11 at 20:12 +0100, Borislav Petkov wrote:
> On Tue, Nov 11, 2014 at 11:43:13AM -0700, Ross Zwisler wrote:
> > Add support for the new clwb instruction. This instruction was
> > announced in the document "Intel Architecture Instruction Set Extensions
> > P
On Tue, 2014-11-11 at 20:19 +0100, Borislav Petkov wrote:
> On Tue, Nov 11, 2014 at 08:12:39PM +0100, Borislav Petkov wrote:
> > > + ".byte 0x66; xsaveopt %P0",
> >
> > Huh, XSAVEOPT?!? Shouldn't that be CLWB??
>
> Bah, the same opcodes, only 0x66 prefix makes it into CLWB. Could
If clwb is available on the system, use it in drm_clflush_virt_range.
If clwb is not available, fall back to clflushopt if you can.
If clflushopt is not supported, fall all the way back to clflush.
Signed-off-by: Ross Zwisler
Cc: H Peter Anvin
Cc: Ingo Molnar
Cc: Thomas Gleixner
Cc: David
If clwb is available on the system, use it in drm_clflush_page.
If clwb is not available, fall back to clflushopt if you can.
If clflushopt is not supported, fall all the way back to clflush.
Signed-off-by: Ross Zwisler
Cc: H Peter Anvin
Cc: Ingo Molnar
Cc: Thomas Gleixner
Cc: David Airlie
If clwb is available on the system, use it in clflush_cache_range.
If clwb is not available, fall back to clflushopt if you can.
If clflushopt is not supported, fall all the way back to clflush.
Signed-off-by: Ross Zwisler
Cc: H Peter Anvin
Cc: Ingo Molnar
Cc: Thomas Gleixner
Cc: David Airlie
n x86_64 kernel code.
Based on this, I don't believe I need to account for this extra prefix when
dealing with the assembly language created for clwb. Please correct me if
I'm wrong.
Signed-off-by: Ross Zwisler
Cc: H Peter Anvin
Cc: Ingo Molnar
Cc: Thomas Gleixner
Cc:
Add alternative_io_2 in the spirit of alternative_input_2 and
alternative_io. This will allow us to have instructions with an output
parameter that vary based on two CPU features.
Signed-off-by: Ross Zwisler
Cc: H Peter Anvin
Cc: Ingo Molnar
Cc: Thomas Gleixner
Cc: David Airlie
Cc: dri
Add support for the new pcommit instruction. This instruction was
announced in the document "Intel Architecture Instruction Set Extensions
Programming Reference" with reference number 319433-022.
https://software.intel.com/sites/default/files/managed/0d/53/319433-022.pdf
Signed-of
erenced again
in the future while it is still in the CPU cache, giving us a performance
boost.
Cc: H Peter Anvin
Cc: Ingo Molnar
Cc: Thomas Gleixner
Cc: David Airlie
Cc: dri-devel at lists.freedesktop.org
Cc: x86 at kernel.org
Ross Zwisler (6):
x86: Add support for the pcommit inst
clflush call to clflushopt.
Signed-off-by: Ross Zwisler
Reported-by: Matthew Wilcox
Cc: David Airlie
Cc: dri-devel at lists.freedesktop.org
Cc: H Peter Anvin
Cc: Ingo Molnar
Cc: Thomas Gleixner
---
drivers/gpu/drm/drm_cache.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
On Wed, 2 Apr 2014, Ross Zwisler wrote:
> With this commit:
>
> 2a0788dc9bc4 x86: Use clflushopt in drm_clflush_virt_range
>
> If clflushopt is available on the system, we use it instead of clflush
> in drm_clflush_virt_range. There were two calls to clflush in this
> funct
clflush call to clflushopt.
Signed-off-by: Ross Zwisler
Reported-by: Matthew Wilcox
---
drivers/gpu/drm/drm_cache.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c
index 534cb89..041b73b 100644
--- a/drivers/gpu/drm
34 matches
Mail list logo
