Hi Alex,
On 2023-12-11 9:17 AM, Alex Deucher wrote:
> On Sun, Dec 10, 2023 at 5:10 AM Samuel Holland
> wrote:
>>
>> Hi Arnd,
>>
>> On 2023-12-09 2:38 PM, Arnd Bergmann wrote:
>>> On Fri, Dec 8, 2023, at 06:04, Samuel Holland wrote:
>>>
Hi Arnd,
On 2023-12-09 2:38 PM, Arnd Bergmann wrote:
> On Fri, Dec 8, 2023, at 06:04, Samuel Holland wrote:
>> On 2023-11-29 6:42 PM, Nathan Chancellor wrote:
>>> On Thu, Nov 23, 2023 at 02:23:01PM +, Conor Dooley wrote:
>>>> On Tue, Nov 21, 2023 at 07:05:15
Hi Christoph,
On 2023-11-22 2:33 AM, Christoph Hellwig wrote:
> On Tue, Nov 21, 2023 at 07:05:13PM -0800, Samuel Holland wrote:
>> +static inline void kernel_fpu_begin(void)
>> +{
>> +preempt_disable();
>> +fstate_save(current, task_pt_regs(current));
>>
Hi Christoph,
On 2023-11-22 2:40 AM, Christoph Hellwig wrote:
>> -select DRM_AMD_DC_FP if (X86 || LOONGARCH || (PPC64 && ALTIVEC) ||
>> (ARM64 && KERNEL_MODE_NEON && !CC_IS_CLANG))
>> +select DRM_AMD_DC_FP if ARM64 && KERNEL_MODE_NEON && !CC_IS_CLANG
>> +select DRM_AMD_DC_FP if PPC64
Hi Nathan,
On 2023-11-29 6:42 PM, Nathan Chancellor wrote:
> On Thu, Nov 23, 2023 at 02:23:01PM +, Conor Dooley wrote:
>> On Tue, Nov 21, 2023 at 07:05:15PM -0800, Samuel Holland wrote:
>>> RISC-V uses kernel_fpu_begin()/kernel_fpu_end() like several other
>>> archi
This is needed to support recent hardware in the amdgpu DRM driver. The
FPU code in that driver is not performance-critical, so only provide the
minimal support.
Signed-off-by: Samuel Holland
---
arch/riscv/include/asm/switch_to.h | 14 ++
arch/riscv/kernel/process.c| 3
. I assume patch 3 would be merged
separately, after patches 1-2 are merged.
Samuel Holland (3):
riscv: Add support for kernel-mode FPU
riscv: Factor out riscv-march-y to a separate Makefile
drm/amd/display: Support DRM_AMD_DC_FP on RISC-V
arch/riscv/Makefile| 12
needed.
Signed-off-by: Samuel Holland
---
arch/riscv/Makefile | 12 +---
arch/riscv/Makefile.isa | 15 +++
2 files changed, 16 insertions(+), 11 deletions(-)
create mode 100644 arch/riscv/Makefile.isa
diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
index a74be78678eb
RISC-V uses kernel_fpu_begin()/kernel_fpu_end() like several other
architectures. Enabling hardware FP requires overriding the ISA string
for the relevant compilation units.
Signed-off-by: Samuel Holland
---
drivers/gpu/drm/amd/display/Kconfig| 5 -
drivers/gpu/drm/amd/display
efinitions in this file.
Signed-off-by: Samuel Holland
---
.../drm/amd/pm/powerplay/hwmgr/pptable_v1_0.h | 20 +--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/pptable_v1_0.h
b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppta
clang on RISC-V appears to be unaffected by the bug causing excessive
stack usage in calculate_bandwidth(). clang 16 with -fstack-usage
reports a 304 byte stack frame size with CONFIG_ARCH_RV32I, and 512
bytes with CONFIG_ARCH_RV64I.
Signed-off-by: Samuel Holland
---
drivers/gpu/drm/amd
FIG_HELPER_PM_OPS() macro instead of an
> exported dev_pm_ops.
>
> Signed-off-by: Paul Cercueil
> ---
>
> Samuel: since the code changed I had to remove your reviewed-by, sorry
> about that.
>
> Cc: Maxime Ripard
> Cc: Chen-Yu Tsai
> Cc:
On 11/7/22 11:50, Paul Cercueil wrote:
> Use the drm_mode_config_pm_ops structure exported by
> drm_modeset_helper.c, which provides the exact same PM callbacks.
>
> Signed-off-by: Paul Cercueil
> ---
> Cc: Maxime Ripard
> Cc: Chen-Yu Tsai
> Cc: Jernej Skrabec
&g
troller")
Acked-by: Krzysztof Kozlowski
Signed-off-by: Samuel Holland
---
(no changes since v1)
.../bindings/display/allwinner,sun6i-a31-mipi-dsi.yaml | 10 ++
1 file changed, 2 insertions(+), 8 deletions(-)
diff --git
a/Documentation/devicetree/bindings/display/allwinner,sun6i-
o now uses pins on Port D instead of dedicated pins,
so it drops the separate power domain.
Acked-by: Krzysztof Kozlowski
Signed-off-by: Samuel Holland
---
Removal of the vcc-dsi-supply is maybe a bit questionable. Since there
is no "VCC-DSI" pin anymore, it's not obvious which pin
series.
Changes in v2:
- Add the variant check to the probe error path
Samuel Holland (4):
dt-bindings: display: sun6i-dsi: Fix clock conditional
dt-bindings: display: sun6i-dsi: Add the A100 variant
drm/sun4i: dsi: Add a variant structure
drm/sun4i: dsi: Add the A100 variant
.../display/all
Replace the ad-hoc calls to of_device_is_compatible() with a structure
describing the differences between variants. This is in preparation for
adding more variants to the driver.
Reviewed-by: Jernej Skrabec
Signed-off-by: Samuel Holland
---
Changes in v2:
- Add the variant check to the probe
The A100 variant of the MIPI DSI controller now gets its module clock
from the TCON via the TCON TOP, so the clock rate cannot be set to a
fixed value. Otherwise, it appears to be the same as the A31 variant.
Reviewed-by: Jernej Skrabec
Signed-off-by: Samuel Holland
---
(no changes since v1
Hi Max,
On 9/17/22 22:44, Max Fierke wrote:
> Add a prefix for Clockwork Tech LLC, known as ClockworkPi. They
> produce a number of hobbyist devices, including the ClockworkPi
> DevTerm and GameShell.
>
> Signed-off-by: Max Fierke
> Acked-by: Krzysztof Kozlowski
> ---
>
On 8/14/22 2:55 AM, Jernej Škrabec wrote:
> Dne petek, 12. avgust 2022 ob 05:16:23 CEST je Samuel Holland napisal(a):
>> Currently, the packet overhead is subtracted using unsigned arithmetic.
>> With a short sync pulse, this could underflow and wrap around to near
>> the m
Hi Krzysztof,
On 8/12/22 5:49 AM, Krzysztof Kozlowski wrote:
> On 12/08/2022 10:42, Samuel Holland wrote:
>> The "40nm" MIPI DSI controller found in the A100 and D1 SoCs has the
>> same register layout as previous SoC integrations. However, its module
>> clock now c
The A100 variant of the MIPI DSI controller now gets its module clock
from the TCON via the TCON TOP, so the clock rate cannot be set to a
fixed value. Otherwise, it appears to be the same as the A31 variant.
Signed-off-by: Samuel Holland
---
drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 8
Replace the ad-hoc calls to of_device_is_compatible() with a structure
describing the differences between variants. This is in preparation for
adding more variants to the driver.
Signed-off-by: Samuel Holland
---
drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 50 +-
drivers
o now uses pins on Port D instead of dedicated pins,
so it drops the separate power domain.
Signed-off-by: Samuel Holland
---
Removal of the vcc-dsi-supply is maybe a bit questionable. Since there
is no "VCC-DSI" pin anymore, it's not obvious which pin actually does
power the DSI cont
n a different subset of SoCs (V5 and A50).
A100/D1 also come with an updated DPHY, described by the BSP as a
"combo" PHY, which is now also used for LVDS channel 0. (LVDS and DSI
share the same pins on Port D.) Since that is a different subsystem,
I am sending that as a separate seri
roller")
Signed-off-by: Samuel Holland
---
.../bindings/display/allwinner,sun6i-a31-mipi-dsi.yaml | 10 ++
1 file changed, 2 insertions(+), 8 deletions(-)
diff --git
a/Documentation/devicetree/bindings/display/allwinner,sun6i-a31-mipi-dsi.yaml
b/Documentation/devicetree/bindings/dis
t;)
Signed-off-by: Samuel Holland
---
.../devicetree/bindings/display/allwinner,sun4i-a10-tcon.yaml | 4
1 file changed, 4 insertions(+)
diff --git
a/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-tcon.yaml
b/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-tcon.
fix to the other timings, even though those subtractions
are less likely to underflow.
Fixes: 133add5b5ad4 ("drm/sun4i: Add Allwinner A31 MIPI-DSI controller support")
Signed-off-by: Samuel Holland
---
drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 10 +-
1 file changed, 5 insert
On 6/15/22 4:38 AM, Suniel Mahesh wrote:
> Add a binding for the RenewWorldOutReach R16-Vista-E board based on
> allwinner R16.
>
> Signed-off-by: Christopher Vollo
> Signed-off-by: Jagan Teki
> Signed-off-by: Suniel Mahesh
The primary author of the commit (the From:) should be the first
On 6/15/22 4:39 AM, Suniel Mahesh wrote:
> The R16-Vista-E board from RenewWorldOutreach based on allwinner
> R16(A33).
>
> General features:
> - 1GB RAM
> - microSD slot
> - Realtek Wifi
> - 1 x USB 2.0
> - HDMI IN
> - HDMI OUT
> - Audio out
> - MIPI DSI
> - TI DLPC3433
>
> It has also
by default, which is found on 64-bit SoCs as well.
Signed-off-by: Samuel Holland
---
drivers/gpu/drm/sun4i/Kconfig | 26 +++---
1 file changed, 15 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/Kconfig b/drivers/gpu/drm/sun4i/Kconfig
index 3a43c436c74a
When adding the bindings for the D1 display engine, I missed the
condition for the number of pipelines. D1 has two mixers, so it
will have two pipeline references.
Fixes: ae5a5d26c15c ("dt-bindings: display: Add D1 display engine compatibles")
Signed-off-by: Samuel Holland
---
..
> [ 184.491354] el0t_64_sync_handler+0x11c/0x150
> [ 184.495723] el0t_64_sync+0x18c/0x190
> [ 184.499397] ---[ end trace ]---
>
> Fix that by setting DMA mask and segment size.
>
> Signed-off-by: Jernej Skrabec
Reviewed-by: Samuel Holland
On 6/16/22 11:13 PM, Jernej Škrabec wrote:
> Dne petek, 17. junij 2022 ob 05:03:11 CEST je Samuel Holland napisal(a):
>> Hi Jernej,
>>
>> On 6/16/22 4:32 PM, Jernej Skrabec wrote:
>>> Kernel occasionally complains that there is mismatch in segment size
>>>
Hi Jernej,
On 6/16/22 4:32 PM, Jernej Skrabec wrote:
> Kernel occasionally complains that there is mismatch in segment size
> when trying to render HW decoded videos and rendering them directly with
> sun4i DRM driver.
>
> Fix that by setting DMA mask and segment size.
>
> Signed-off-by: Jernej
data while the platform driver holds
a reference to the drm_device.
Fixes: 624b4b48d9d8 ("drm: sun4i: Add support for suspending the display
driver")
Signed-off-by: Samuel Holland
---
drivers/gpu/drm/sun4i/sun4i_drv.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git
Now that the PHY ops are separated, sort them topologically, with the
common sun8i_hdmi_phy_set_polarity helper at the top. No function
contents are changed in this commit.
Signed-off-by: Samuel Holland
---
(no changes since v1)
drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 67
The D1 SoC comes with a new custom HDMI PHY, which does not share any
registers with the existing custom PHY. So it needs a new set of ops.
Instead of providing a flag in the variant structure, provide the ops
themselves.
Signed-off-by: Samuel Holland
---
(no changes since v1)
drivers/gpu/drm
Since the driver already needs to support multiple sets of ops, we can
drop the mid-layer used by the A83T and H3 PHYs. They share only a small
amount of code; factor this out as sun8i_hdmi_phy_set_polarity.
For clarity, this commit keeps the existing function order.
Signed-off-by: Samuel
Now that the HDMI PHY is using a platform driver, it can use device-
managed resources. Use these, as well as the dev_err_probe helper, to
simplify the probe function and get rid of the remove function.
Signed-off-by: Samuel Holland
---
Changes in v2:
- Move error handling inside variant
The struct resource is not used for anything else, so we can simplify
the code a bit by using the helper function.
Signed-off-by: Samuel Holland
---
(no changes since v1)
drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 9 +
1 file changed, 1 insertion(+), 8 deletions(-)
diff --git a/drivers
Now that the HDMI PHY is using a platform driver, we can use the usual
helper function for getting the variant structure.
Signed-off-by: Samuel Holland
---
(no changes since v1)
drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h | 2 +-
drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 11 ++-
2 files
This series prepares the sun8i HDMI PHY driver for supporting the new
custom PHY in the Allwinner D1 SoC. No functional change intended here.
This series was tested on D1, H3, and H6.
Changes in v2:
- Move error handling inside variant checks in probe function
Samuel Holland (6):
drm/sun4i
en gpio support")
Signed-off-by: Samuel Holland
---
drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c | 54 ++-
drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h | 2 -
2 files changed, 4 insertions(+), 52 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
b/drivers/gpu/drm/s
Hi Sasha,
On 5/30/22 8:49 AM, Sasha Levin wrote:
> From: Samuel Holland
>
> [ Upstream commit b9b52d2f4aafa2bd637ace0f24615bdad8e49f01 ]
>
> D1 has a TCON TOP, so its quirks are similar to those for the R40 TCONs.
> While there are some register changes, the part of the
On 5/23/22 8:14 AM, Icenowy Zheng wrote:
> 在 2022-05-22星期日的 10:36 +0200，Jernej Škrabec写道：
>> Hi!
>>
>> Dne sobota, 21. maj 2022 ob 15:34:43 CEST je Genfu Pan napisal(a):
>>> Accrording the SDK from Allwinner, the scanline value of yuv and
>>> rgb for
>>> V3s are both 1024.
>>
>> s/scanline
a new quirks structure.
D1's TCON LCD hardware supports LVDS; in fact it provides dual-link LVDS
from a single TCON. However, it comes with a brand new LVDS PHY. Since
this PHY has not been tested, leave out LVDS driver support for now.
Signed-off-by: Samuel Holland
---
(no changes since v1
Now that the various blocks in the D1 display engine pipeline are
supported, we can enable the overall engine.
Acked-by: Jernej Skrabec
Signed-off-by: Samuel Holland
---
(no changes since v1)
drivers/gpu/drm/sun4i/sun4i_drv.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu
D1 has a display engine with the usual pair of mixers, albeit with
relatively few layers. In fact, D1 appears to be the first SoC to have
a mixer without any UI layers. Add support for these new variants.
Acked-by: Jernej Skrabec
Signed-off-by: Samuel Holland
---
(no changes since v1
D1 changes the MMIO offsets for the CSC blocks in the first mixer. The
mixers' ccsc property is used as an index into the ccsc_base array. Use
an enumeration to describe this index, and add the new set of offsets.
Signed-off-by: Samuel Holland
---
(no changes since v2)
Changes in v2:
- Use
D1's mixer 1 has no UI layers, only a single VI layer. That means the
mixer can only be used if the primary plane comes from this VI layer.
Add the code to handle this case.
Signed-off-by: Samuel Holland
---
(no changes since v2)
Changes in v2:
- Use Jernej's patches for mixer mode setting
D1 has a TCON TOP with TCON TV0 and DSI, but no TCON TV1. This puts the
DSI clock name at index 1 in clock-output-names. Support this by only
incrementing the index for clocks that are actually supported.
Signed-off-by: Samuel Holland
---
(no changes since v1)
drivers/gpu/drm/sun4i
Skrabec
[Samuel: drop unused 'interlaced' variable]
Signed-off-by: Samuel Holland
---
(no changes since v2)
Changes in v2:
- Use Jernej's patches for mixer mode setting.
drivers/gpu/drm/sun4i/sun4i_backend.c | 40 +--
1 file changed, 20 insertions(+), 20 deletions
Allwinner D1 is a RISC-V SoC which contains a DE 2.0 engine. Let's
remove the dependency on a specific CPU architecture, so the driver can
be built wherever ARCH_SUNXI is selected.
Acked-by: Jernej Skrabec
Signed-off-by: Samuel Holland
---
(no changes since v1)
drivers/gpu/drm/sun4i/Kconfig
limitation to primary planes.
3. The current code only works for UI layers, but some mixers do not
have any UI layers.
Signed-off-by: Jernej Skrabec
[Samuel: update commit message]
Signed-off-by: Samuel Holland
---
(no changes since v2)
Changes in v2:
- Use Jernej's patches for mixer mode setting
readsb/writesb are unavailable on some architectures. In preparation for
removing the Kconfig architecture dependency, switch to the equivalent
but more portable ioread/write8_rep helpers.
Reported-by: kernel test robot
Signed-off-by: Samuel Holland
---
(no changes since v2)
Changes in v2
that in follow up patches,
which will migrate that code to this newly defined callback.
Signed-off-by: Jernej Skrabec
Signed-off-by: Samuel Holland
---
(no changes since v2)
Changes in v2:
- Use Jernej's patches for mixer mode setting.
drivers/gpu/drm/sun4i/sun4i_crtc.c | 1 +
drivers/gpu/drm/sun4i
, but no TCON TV1. This
cannot be supported by the existing scheme because it puts a gap in the
middle of the item lists. To prepare for adding D1 support, use separate
lists for variants with different combinations of clocks.
Reviewed-by: Krzysztof Kozlowski
Signed-off-by: Samuel Holland
---
Changes
0 ("soc: sunxi: Deal with the MBUS DMA offsets in a central
place")
Reviewed-by: Jernej Skrabec
Signed-off-by: Samuel Holland
---
(no changes since v1)
drivers/gpu/drm/sun4i/sun4i_frontend.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun4i_front
Allwinner D1 contains a display engine 2.0. It features two mixers, a
TCON TOP (with DSI and HDMI), one TCON LCD, and one TCON TV.
Reviewed-by: Krzysztof Kozlowski
Signed-off-by: Samuel Holland
---
Changes in v3:
- Drop redundant minItems and maxItems
.../allwinner,sun4i-a10-display
: Add mode_set callback
sun4i/drm: backend: use mode_set engine callback
sun4i/drm: sun8i: use mode_set engine callback
Samuel Holland (11):
dt-bindings: display: Separate clock item lists by compatible
dt-bindings: display: Add D1 display engine compatibles
drm/sun4i: Remove obsolete
r 2022 17:19:02 -0500
> Samuel Holland wrote:
>
> [...]
> we have sy7636a driver in kernel which should be suitable for powering a EPD
> and temperature measurement. So I would expect that to be
>> + io-channels:
>> +maxItems: 1
>> +description: I/O channel
brightness accuracy. On the other hand, it doesn't leave
random lines all over the screen.
Signed-off-by: Samuel Holland
---
drivers/gpu/drm/rockchip/rockchip_ebc.c | 97 ++---
1 file changed, 88 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/rockchip
The PineNote contains an eInk ED103TC2 panel connected to the EBC,
powered by a TI TPS651851 PMIC.
Signed-off-by: Samuel Holland
---
.../boot/dts/rockchip/rk3566-pinenote.dtsi| 80 +++
1 file changed, 80 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3566
The RK356x SoCs contain an EBC. Add its node.
Signed-off-by: Samuel Holland
---
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
index 7cdef800cb3c
width.
Datasheet:
https://files.pine64.org/doc/quartz64/Eink%20P-511-828-V1_ED103TC2%20Formal%20Spec%20V1.0_20190514.pdf
Signed-off-by: Samuel Holland
---
drivers/gpu/drm/panel/panel-simple.c | 31
1 file changed, 31 insertions(+)
diff --git a/drivers/gpu/drm/panel/panel-sim
buffers when an area completes. (This
extra frame is a no-op and is not sent to the hardware.)
Signed-off-by: Samuel Holland
---
drivers/gpu/drm/rockchip/rockchip_ebc.c | 346 +++-
1 file changed, 344 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/rockchip
pixel value, frame number) in the LUT and sends
the resulting polarity value to the display.
Signed-off-by: Samuel Holland
---
drivers/gpu/drm/rockchip/rockchip_ebc.c | 48 -
1 file changed, 47 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/rockchip
Some panels, like the one in the PineNote, are reflected. Since the
driver already has to copy pixels, the driver can handle this with
little additional overhead.
Currently, there is no devicetree binding for this situation, so control
the behavior via a module parameter.
Signed-off-by: Samuel
).
This additional timing information is packed inside drm_display_mode as
hskew and DRM_MODE_FLAG_CLKDIV2. This allows getting the complete mode
from a DRM bridge.
Signed-off-by: Samuel Holland
---
drivers/gpu/drm/rockchip/rockchip_ebc.c | 102
1 file changed, 102 insertions
and always send zeroes for pixels with unchanged values.
Signed-off-by: Samuel Holland
---
drivers/gpu/drm/rockchip/rockchip_ebc.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c
b/drivers/gpu/drm/rockchip/rockchip_ebc.c
index c3e4b65bdee6
is disabled.
Signed-off-by: Samuel Holland
---
drivers/gpu/drm/rockchip/rockchip_ebc.c | 82 -
1 file changed, 81 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c
b/drivers/gpu/drm/rockchip/rockchip_ebc.c
index 5f9502313657..ebe60d5e011a 100644
aps between two buffers to minimize the delay between phases,
as these buffers must be updated for every phase in the waveform.
Signed-off-by: Samuel Holland
---
drivers/gpu/drm/rockchip/rockchip_ebc.c | 166 +++-
1 file changed, 163 insertions(+), 3 deletions(-)
diff --git a/drive
The EBC contains a 16 KiB SRAM which stores the current LUT. It needs to
be programmed any time the LUT changes or the hardware block is enabled.
Since both of these triggers can happen at the same time, use a flag to
avoid writing the LUT twice.
Signed-off-by: Samuel Holland
---
drivers/gpu
they
are only needed during display refreshes. They do not match the normal
panel prepare/enable lifecycle.
Signed-off-by: Samuel Holland
---
drivers/gpu/drm/Makefile| 2 +-
drivers/gpu/drm/rockchip/Kconfig| 11 +
drivers/gpu/drm/rockchip/Makefile | 2 +
drivers/gpu
of the shadow plane helpers.
Signed-off-by: Samuel Holland
---
drivers/gpu/drm/rockchip/rockchip_ebc.c | 359 +++-
1 file changed, 356 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c
b/drivers/gpu/drm/rockchip/rockchip_ebc.c
index 5ed66c6cd2f0.
to declare their desired format. It will then convert
LUTs to that format before returning them.
Signed-off-by: Samuel Holland
---
drivers/gpu/drm/Kconfig | 6 +
drivers/gpu/drm/Makefile | 2 +
drivers/gpu/drm/drm_epd_helper.c | 663 +++
include/drm
they are
only needed during display refreshes. They do not match the normal
panel prepare/enable lifecycle.
Signed-off-by: Samuel Holland
---
.../display/rockchip/rockchip,rk3568-ebc.yaml | 106 ++
1 file changed, 106 insertions(+)
create mode 100644
Documentation/devicetree
[4]: https://lore.kernel.org/lkml/cover.1646683502.git.ge...@linux-m68k.org/T/
[5]:
https://lore.kernel.org/lkml/20220330094126.30252-1-alist...@alistair23.me/T/
[6]: https://github.com/megous/linux/commits/pb-5.17
[7]: https://github.com/megous/linux/commit/3cdf84388959
[8]: https://github.com/fread
On 4/12/22 8:23 AM, Maxime Ripard wrote:
> Hi,
>
> On Mon, Apr 11, 2022 at 11:35:08PM -0500, Samuel Holland wrote:
>> Now that the HDMI PHY is using a platform driver, it can use device-
>> managed resources. Use these, as well as the dev_err_probe helper, to
>>
Now that the PHY ops are separated, sort them topologically, with the
common sun8i_hdmi_phy_set_polarity helper at the top. No function
contents are changed in this commit.
Signed-off-by: Samuel Holland
---
drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 67 --
1 file changed
Since the driver already needs to support multiple sets of ops, we can
drop the mid-layer used by the A83T and H3 PHYs. They share only a small
amount of code; factor this out as sun8i_hdmi_phy_set_polarity.
For clarity, this commit keeps the existing function order.
Signed-off-by: Samuel
The D1 SoC comes with a new custom HDMI PHY, which does not share any
registers with the existing custom PHY. So it needs a new set of ops.
Instead of providing a flag in the variant structure, provide the ops
themselves.
Signed-off-by: Samuel Holland
---
drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
Now that the HDMI PHY is using a platform driver, it can use device-
managed resources. Use these, as well as the dev_err_probe helper, to
simplify the probe function and get rid of the remove function.
Signed-off-by: Samuel Holland
---
drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 100
The struct resource is not used for anything else, so we can simplify
the code a bit by using the helper function.
Signed-off-by: Samuel Holland
---
drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 9 +
1 file changed, 1 insertion(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/sun4i
Now that the HDMI PHY is using a platform driver, we can use the usual
helper function for getting the variant structure.
Signed-off-by: Samuel Holland
---
drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h | 2 +-
drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 11 ++-
2 files changed, 3 insertions
This series prepares the sun8i HDMI PHY driver for supporting the new
custom PHY in the Allwinner D1 SoC. No functional change intended here.
This series was tested on D1 and H3.
Samuel Holland (6):
drm/sun4i: sun8i-hdmi-phy: Use of_device_get_match_data
drm/sun4i: sun8i-hdmi-phy: Use
Now that the various blocks in the D1 display engine pipeline are
supported, we can enable the overall engine.
Acked-by: Jernej Skrabec
Signed-off-by: Samuel Holland
---
(no changes since v1)
drivers/gpu/drm/sun4i/sun4i_drv.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu
a new quirks structure.
D1's TCON LCD hardware supports LVDS; in fact it provides dual-link LVDS
from a single TCON. However, it comes with a brand new LVDS PHY. Since
this PHY has not been tested, leave out LVDS driver support for now.
Signed-off-by: Samuel Holland
---
(no changes since v1
D1 has a TCON TOP with TCON TV0 and DSI, but no TCON TV1. This puts the
DSI clock name at index 1 in clock-output-names. Support this by only
incrementing the index for clocks that are actually supported.
Signed-off-by: Samuel Holland
---
(no changes since v1)
drivers/gpu/drm/sun4i
D1 has a display engine with the usual pair of mixers, albeit with
relatively few layers. In fact, D1 appears to be the first SoC to have
a mixer without any UI layers. Add support for these new variants.
Acked-by: Jernej Skrabec
Signed-off-by: Samuel Holland
---
(no changes since v1
D1 changes the MMIO offsets for the CSC blocks in the first mixer. The
mixers' ccsc property is used as an index into the ccsc_base array. Use
an enumeration to describe this index, and add the new set of offsets.
Signed-off-by: Samuel Holland
---
Changes in v2:
- Use an enumeration
D1's mixer 1 has no UI layers, only a single VI layer. That means the
mixer can only be used if the primary plane comes from this VI layer.
Add the code to handle this case.
Signed-off-by: Samuel Holland
---
Changes in v2:
- Use Jernej's patches for mixer mode setting.
drivers/gpu/drm/sun4i
limitation to primary planes.
3. The current code only works for UI layers, but some mixers do not
have any UI layers.
Signed-off-by: Jernej Skrabec
[Samuel: update commit message]
Signed-off-by: Samuel Holland
---
Changes in v2:
- Use Jernej's patches for mixer mode setting.
drivers/gpu/drm
Skrabec
[Samuel: drop unused 'interlaced' variable]
Signed-off-by: Samuel Holland
---
Changes in v2:
- Use Jernej's patches for mixer mode setting.
drivers/gpu/drm/sun4i/sun4i_backend.c | 40 +--
1 file changed, 20 insertions(+), 20 deletions(-)
diff --git a/drivers
that in follow up patches,
which will migrate that code to this newly defined callback.
Signed-off-by: Jernej Skrabec
Signed-off-by: Samuel Holland
---
Changes in v2:
- Use Jernej's patches for mixer mode setting.
drivers/gpu/drm/sun4i/sun4i_crtc.c | 1 +
drivers/gpu/drm/sun4i/sunxi_engine.h | 27
readsb/writesb are unavailable on some architectures. In preparation for
removing the Kconfig architecture dependency, switch to the equivalent
but more portable ioread/write8_rep helpers.
Reported-by: kernel test robot
Signed-off-by: Samuel Holland
---
Changes in v2:
- New patch: I/O helper
Allwinner D1 is a RISC-V SoC which contains a DE 2.0 engine. Let's
remove the dependency on a specific CPU architecture, so the driver can
be built wherever ARCH_SUNXI is selected.
Acked-by: Jernej Skrabec
Signed-off-by: Samuel Holland
---
(no changes since v1)
drivers/gpu/drm/sun4i/Kconfig
0 ("soc: sunxi: Deal with the MBUS DMA offsets in a central
place")
Reviewed-by: Jernej Skrabec
Signed-off-by: Samuel Holland
---
(no changes since v1)
drivers/gpu/drm/sun4i/sun4i_frontend.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun4i_front
Allwinner D1 contains a display engine 2.0. It features two mixers, a
TCON TOP (with DSI and HDMI), one TCON LCD, and one TCON TV.
Reviewed-by: Krzysztof Kozlowski
Signed-off-by: Samuel Holland
---
(no changes since v1)
.../allwinner,sun4i-a10-display-engine.yaml | 1 +
.../display
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