[PATCH v3] drm/edid DSC pass-through timing support

Yaroslav Bolyukin (2): drm/edid: parse DRM VESA dsc bpp target drm/amd: use fixed dsc bits-per-pixel from edid .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 2 + .../gpu/drm/amd/display/dc/core/dc_stream.c | 2 + drivers/gpu/drm/amd/display/dc/dc_types.h | 3 ++ drivers/gpu/drm

[PATCH v3 1/2] drm/edid: parse DRM VESA dsc bpp target

As per DisplayID v2.0 Errata E9 spec "DSC pass-through timing support" VESA vendor-specific data block may contain target DSC bits per pixel fields Signed-off-by: Yaroslav Bolyukin --- drivers/gpu/drm/drm_edid.c | 38 + include/drm/drm_connec

[PATCH v3 2/2] drm/amd: use fixed dsc bits-per-pixel from edid

VESA vendor header from DisplayID spec may contain fixed bit per pixel rate, it should be respected by drm driver Signed-off-by: Yaroslav Bolyukin Reviewed-by: Wayne Lin --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 2 ++ drivers/gpu/drm/amd/display/dc/core/dc_stream.c

[RESEND PATCH v2 1/2] drm/edid: parse DRM VESA dsc bpp target

As per DisplayID v2.0 Errata E9 spec "DSC pass-through timing support" VESA vendor-specific data block may contain target DSC bits per pixel fields Signed-off-by: Yaroslav Bolyukin --- drivers/gpu/drm/drm_edid.c | 33 ++--- include/drm/drm_connec

[RESEND PATCH v2 2/2] drm/amd: use fixed dsc bits-per-pixel from edid

VESA vendor header from DisplayID spec may contain fixed bit per pixel rate, it should be respected by drm driver Signed-off-by: Yaroslav Bolyukin Reviewed-by: Wayne Lin --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 2 ++ drivers/gpu/drm/amd/display/dc/core/dc_stream.c

[PATCH v2 2/2] drm/amd: use fixed dsc bits-per-pixel from edid

VESA vendor header from DisplayID spec may contain fixed bit per pixel rate, it should be respected by drm driver Signed-off-by: Yaroslav Bolyukin Reviewed-by: Wayne Lin --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 2 ++ drivers/gpu/drm/amd/display/dc/core/dc_stream.c

[PATCH v2 1/2] drm/edid: parse DRM VESA dsc bpp target

As per DisplayID v2.0 Errata E9 spec "DSC pass-through timing support" VESA vendor-specific data block may contain target DSC bits per pixel fields Signed-off-by: Yaroslav Bolyukin --- drivers/gpu/drm/drm_edid.c | 33 ++--- include/drm/drm_connec

[PATCH 2/2] drm/amd: use fixed dsc bits-per-pixel from edid

VESA vendor header from DisplayID spec may contain fixed bit per pixel rate, it should be respected by drm driver Signed-off-by: Yaroslav Bolyukin --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 2 ++ drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 3 ++- drivers/gpu

[PATCH 1/2] edid: parse DRM VESA dsc bpp target

As per DisplayID v2.0 Errata E9 spec Signed-off-by: Yaroslav Bolyukin --- drivers/gpu/drm/drm_edid.c | 31 --- include/drm/drm_connector.h | 6 ++ include/drm/drm_displayid.h | 4 3 files changed, 30 insertions(+), 11 deletions(-) diff --git a/drivers

[PATCH] drm/edid: Support type 7 timings

Per VESA DisplayID Standard v2.0: Type VII Timing – Detailed Timing Data Definitions were already provided as type I, but not used Signed-off-by: Yaroslav Bolyukin --- drivers/gpu/drm/drm_edid.c | 26 +- include/drm/drm_displayid.h | 6 +++--- 2 files changed, 20