Re: [PATCH 2/2] drm: bridge: Add SN65DSI84 DSI to LVDS bridge
Hi Riadh, On Wed, Feb 17, 2021 at 8:44 PM Riadh Ghaddab wrote: > > Hi Jagan, > > On 20/01/2021 12:21, Jagan Teki wrote: > > SN65DSI84 is a Single Channel DSI to Dual-link LVDS bridge from > Texas Instruments. > > SN65DSI83, SN65DSI85 are variants of the same family of bridge > controllers. > > Right now the bridge driver is supporting a single link, dual-link > support requires to initiate I2C Channel B registers. > > Tested with STM32MP1 MIPI DSI host design configuration. > > Do you have the code to support the Dual channel LVDS feature ? > If not I recently developed the code for a board using sn65dsi84 with Dual > LVDS channel I have the basic one, but not have the proper hardware to verify dual-link. Please have a look at V2 of similar patches. We will sort out the driver so-that it can work with possible configurations. > > Signed-off-by: Matteo Lisi > Signed-off-by: Jagan Teki > --- > MAINTAINERS | 6 + > drivers/gpu/drm/bridge/Kconfig| 19 + > drivers/gpu/drm/bridge/Makefile | 1 + > drivers/gpu/drm/bridge/ti-sn65dsi84.c | 488 ++ > 4 files changed, 514 insertions(+) > create mode 100644 drivers/gpu/drm/bridge/ti-sn65dsi84.c > > diff --git a/MAINTAINERS b/MAINTAINERS > index 12dd1fff2a39..44750ff7640c 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -5984,6 +5984,12 @@ S: Maintained > F: Documentation/devicetree/bindings/display/ti/ > F: drivers/gpu/drm/omapdrm/ > > +DRM DRIVERS FOR TI SN65DSI84 DSI TO LVDS BRIDGE > +M: Jagan Teki > +S: Maintained > +F: Documentation/devicetree/bindings/display/bridge/ti,sn65dsi84.yaml > +F: drivers/gpu/drm/bridge/ti-sn65dsi84.c > + > DRM DRIVERS FOR V3D > M: Eric Anholt > S: Supported > diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig > index e4110d6ca7b3..6494881bffb3 100644 > --- a/drivers/gpu/drm/bridge/Kconfig > +++ b/drivers/gpu/drm/bridge/Kconfig > @@ -232,6 +232,25 @@ config DRM_TI_TFP410 > help >Texas Instruments TFP410 DVI/HDMI Transmitter driver > > +config DRM_TI_SN65DSI84 > + tristate "TI SN65DSI84 DSI to LVDS bridge" > + depends on OF > + select DRM_KMS_HELPER > + select REGMAP_I2C > + select DRM_PANEL > + select DRM_MIPI_DSI > + help > + Texas Instruments SN65DSI84 Single Channel DSI to Dual-link LVDS > + bridge driver. > + > + Bridge decodes MIPI DSI 18bpp RGB666 and 240bpp RG888 packets and > + converts the formatted video data stream to a FlatLink compatible > + LVDS output operating at pixel clocks operating from 25 MHx to > + 154 MHz. > + > + SN65DSI84 offers a Dual-Link LVDS, Single-Link LVDS interface with > + four data lanes per link. > + > config DRM_TI_SN65DSI86 > tristate "TI SN65DSI86 DSI to eDP bridge" > depends on OF > diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile > index 86e7acc76f8d..3906052ef639 100644 > --- a/drivers/gpu/drm/bridge/Makefile > +++ b/drivers/gpu/drm/bridge/Makefile > @@ -20,6 +20,7 @@ obj-$(CONFIG_DRM_TOSHIBA_TC358767) += tc358767.o > obj-$(CONFIG_DRM_TOSHIBA_TC358768) += tc358768.o > obj-$(CONFIG_DRM_TOSHIBA_TC358775) += tc358775.o > obj-$(CONFIG_DRM_I2C_ADV7511) += adv7511/ > +obj-$(CONFIG_DRM_TI_SN65DSI84) += ti-sn65dsi84.o > obj-$(CONFIG_DRM_TI_SN65DSI86) += ti-sn65dsi86.o > obj-$(CONFIG_DRM_TI_TFP410) += ti-tfp410.o > obj-$(CONFIG_DRM_TI_TPD12S015) += ti-tpd12s015.o > diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi84.c > b/drivers/gpu/drm/bridge/ti-sn65dsi84.c > new file mode 100644 > index ..3ed1f9a7d898 > --- /dev/null > +++ b/drivers/gpu/drm/bridge/ti-sn65dsi84.c > @@ -0,0 +1,488 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (c) 2021 Engicam srl > + * Copyright (C) 2021 Amarula Solutions(India) > + * Author: Jagan Teki > + */ > + > +#include > +#include > +#include > +#include > + > +#include > +#include > +#include > +#include > +#include > + > +/* sn65dsi84 registers */ > +#define SN65DSI_SOFT_RESET 0x09 > +#define SN65DSI_LVDS_CLK 0x0a > +#define SN65DSI_CLK_DIV 0x0b > +#define SN65DSI_CLK_PLL 0x0d > +#define SN65DSI_DSI_CFG 0x10 > +#define SN65DSI_DSI_CLK_EQ 0x11 > +#define SN65DSI_DSI_CLK_RANGE 0x12 > +#define SN65DSI_LVDS_MODE 0x18 > +#define SN65DSI_CHA_LINE_LO 0x20 > +#define SN65DSI_CHA_LINE_HI 0x21 > +#define SN65DSI_CHA_VIRT_LO 0x24 > +#define SN65DSI_CHA_VIRT_HI 0x25 > +#define SN65DSI_CHA_SYNC_DELAY_LO 0x28 > +#define SN65DSI_CHA_SYNC_DELAY_HI 0x29 > +#define SN65DSI_CHA_HSYNC_WIDTH_LO 0x2c > +#define SN65DSI_CHA_HSYNC_WIDTH_HI 0x2d > +#define SN65DSI_CHA_VSYNC_WIDTH_LO 0x30 > +#define SN65DSI_CHA_VSYNC_WIDTH_HI 0x31 > +#define SN65DSI_CHA_HBACK_PORCH 0x34 > +#define SN65DSI_CHA_VBACK_PORCH 0x36 > +#define SN65DSI_CHA_HFRONT_PORCH 0x38 > +#define SN65DSI_CHA_VFRONT_PORCH 0x3a > +#define SN65DSI_CHA_ERR 0xe5 > + > +/* sn65dsi register bits */ > +#define SN65DSI_RESET_EN BIT(0) > +#define SN65DSI_PLL_EN BIT(0) > +#define SN65DSI_LVDS_CLK_MASK GENMASK(3, 1) > +#define SN65DSI_LVDS_CLK_SHIFT
Re: [PATCH 2/2] drm: bridge: Add SN65DSI84 DSI to LVDS bridge
Hi Jagan, On 20/01/2021 12:21, Jagan Teki wrote: SN65DSI84 is a Single Channel DSI to Dual-link LVDS bridge from Texas Instruments. SN65DSI83, SN65DSI85 are variants of the same family of bridge controllers. Right now the bridge driver is supporting a single link, dual-link support requires to initiate I2C Channel B registers. Tested with STM32MP1 MIPI DSI host design configuration. Do you have the code to support the Dual channel LVDS feature ? If not I recently developed the code for a board using sn65dsi84 with Dual LVDS channel Signed-off-by: Matteo Lisi Signed-off-by: Jagan Teki --- MAINTAINERS | 6 + drivers/gpu/drm/bridge/Kconfig| 19 + drivers/gpu/drm/bridge/Makefile | 1 + drivers/gpu/drm/bridge/ti-sn65dsi84.c | 488 ++ 4 files changed, 514 insertions(+) create mode 100644 drivers/gpu/drm/bridge/ti-sn65dsi84.c diff --git a/MAINTAINERS b/MAINTAINERS index 12dd1fff2a39..44750ff7640c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -5984,6 +5984,12 @@ S: Maintained F:Documentation/devicetree/bindings/display/ti/ F:drivers/gpu/drm/omapdrm/ +DRM DRIVERS FOR TI SN65DSI84 DSI TO LVDS BRIDGE +M: Jagan Teki +S: Maintained +F: Documentation/devicetree/bindings/display/bridge/ti,sn65dsi84.yaml +F: drivers/gpu/drm/bridge/ti-sn65dsi84.c + DRM DRIVERS FOR V3D M:Eric Anholt S:Supported diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig index e4110d6ca7b3..6494881bffb3 100644 --- a/drivers/gpu/drm/bridge/Kconfig +++ b/drivers/gpu/drm/bridge/Kconfig @@ -232,6 +232,25 @@ config DRM_TI_TFP410 help Texas Instruments TFP410 DVI/HDMI Transmitter driver +config DRM_TI_SN65DSI84 + tristate "TI SN65DSI84 DSI to LVDS bridge" + depends on OF + select DRM_KMS_HELPER + select REGMAP_I2C + select DRM_PANEL + select DRM_MIPI_DSI + help + Texas Instruments SN65DSI84 Single Channel DSI to Dual-link LVDS + bridge driver. + + Bridge decodes MIPI DSI 18bpp RGB666 and 240bpp RG888 packets and + converts the formatted video data stream to a FlatLink compatible + LVDS output operating at pixel clocks operating from 25 MHx to + 154 MHz. + + SN65DSI84 offers a Dual-Link LVDS, Single-Link LVDS interface with + four data lanes per link. + config DRM_TI_SN65DSI86 tristate "TI SN65DSI86 DSI to eDP bridge" depends on OF diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile index 86e7acc76f8d..3906052ef639 100644 --- a/drivers/gpu/drm/bridge/Makefile +++ b/drivers/gpu/drm/bridge/Makefile @@ -20,6 +20,7 @@ obj-$(CONFIG_DRM_TOSHIBA_TC358767) += tc358767.o obj-$(CONFIG_DRM_TOSHIBA_TC358768) += tc358768.o obj-$(CONFIG_DRM_TOSHIBA_TC358775) += tc358775.o obj-$(CONFIG_DRM_I2C_ADV7511) += adv7511/ +obj-$(CONFIG_DRM_TI_SN65DSI84) += ti-sn65dsi84.o obj-$(CONFIG_DRM_TI_SN65DSI86) += ti-sn65dsi86.o obj-$(CONFIG_DRM_TI_TFP410) += ti-tfp410.o obj-$(CONFIG_DRM_TI_TPD12S015) += ti-tpd12s015.o diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi84.c b/drivers/gpu/drm/bridge/ti-sn65dsi84.c new file mode 100644 index ..3ed1f9a7d898 --- /dev/null +++ b/drivers/gpu/drm/bridge/ti-sn65dsi84.c @@ -0,0 +1,488 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2021 Engicam srl + * Copyright (C) 2021 Amarula Solutions(India) + * Author: Jagan Teki + */ + +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +/* sn65dsi84 registers */ +#define SN65DSI_SOFT_RESET 0x09 +#define SN65DSI_LVDS_CLK 0x0a +#define SN65DSI_CLK_DIV0x0b +#define SN65DSI_CLK_PLL0x0d +#define SN65DSI_DSI_CFG0x10 +#define SN65DSI_DSI_CLK_EQ 0x11 +#define SN65DSI_DSI_CLK_RANGE 0x12 +#define SN65DSI_LVDS_MODE 0x18 +#define SN65DSI_CHA_LINE_LO0x20 +#define SN65DSI_CHA_LINE_HI0x21 +#define SN65DSI_CHA_VIRT_LO0x24 +#define SN65DSI_CHA_VIRT_HI0x25 +#define SN65DSI_CHA_SYNC_DELAY_LO 0x28 +#define SN65DSI_CHA_SYNC_DELAY_HI 0x29 +#define SN65DSI_CHA_HSYNC_WIDTH_LO 0x2c +#define SN65DSI_CHA_HSYNC_WIDTH_HI 0x2d +#define SN65DSI_CHA_VSYNC_WIDTH_LO 0x30 +#define SN65DSI_CHA_VSYNC_WIDTH_HI 0x31 +#define SN65DSI_CHA_HBACK_PORCH0x34 +#define SN65DSI_CHA_VBACK_PORCH0x36 +#define SN65DSI_CHA_HFRONT_PORCH 0x38 +#define SN65DSI_CHA_VFRONT_PORCH 0x3a +#define SN65DSI_CHA_ERR0xe5 + +/* sn65dsi register bits */ +#define SN65DSI_RESET_EN BIT(0) +#define SN65DSI_PLL_EN BIT(0) +#define SN65DSI_LVDS_CLK_MASK GENMASK(3, 1) +#define SN65DSI_LVDS_CLK_SHIFT 1 +#define SN65DSI_LVDS_CLK_SRC_DSI BIT(0)
Re: [PATCH 2/2] drm: bridge: Add SN65DSI84 DSI to LVDS bridge
On Wed, Jan 20, 2021 at 12:29 PM Jagan Teki wrote: > > On Wed, Jan 20, 2021 at 4:55 PM Michael Nazzareno Trimarchi > wrote: > > > > Hi Jagan > > > > On Wed, Jan 20, 2021 at 12:22 PM Jagan Teki > > wrote: > > > > > > SN65DSI84 is a Single Channel DSI to Dual-link LVDS bridge from > > > Texas Instruments. > > > > > > SN65DSI83, SN65DSI85 are variants of the same family of bridge > > > controllers. > > > > > > Right now the bridge driver is supporting a single link, dual-link > > > support requires to initiate I2C Channel B registers. > > > > > > Tested with STM32MP1 MIPI DSI host design configuration. > > > > > > Signed-off-by: Matteo Lisi > > > Signed-off-by: Jagan Teki > > > --- > > > MAINTAINERS | 6 + > > > drivers/gpu/drm/bridge/Kconfig| 19 + > > > drivers/gpu/drm/bridge/Makefile | 1 + > > > drivers/gpu/drm/bridge/ti-sn65dsi84.c | 488 ++ > > > 4 files changed, 514 insertions(+) > > > create mode 100644 drivers/gpu/drm/bridge/ti-sn65dsi84.c > > > > > > diff --git a/MAINTAINERS b/MAINTAINERS > > > index 12dd1fff2a39..44750ff7640c 100644 > > > --- a/MAINTAINERS > > > +++ b/MAINTAINERS > > > @@ -5984,6 +5984,12 @@ S: Maintained > > > F: Documentation/devicetree/bindings/display/ti/ > > > F: drivers/gpu/drm/omapdrm/ > > > > > > +DRM DRIVERS FOR TI SN65DSI84 DSI TO LVDS BRIDGE > > > +M: Jagan Teki > > > +S: Maintained > > > +F: Documentation/devicetree/bindings/display/bridge/ti,sn65dsi84.yaml > > > +F: drivers/gpu/drm/bridge/ti-sn65dsi84.c > > > + > > > DRM DRIVERS FOR V3D > > > M: Eric Anholt > > > S: Supported > > > diff --git a/drivers/gpu/drm/bridge/Kconfig > > > b/drivers/gpu/drm/bridge/Kconfig > > > index e4110d6ca7b3..6494881bffb3 100644 > > > --- a/drivers/gpu/drm/bridge/Kconfig > > > +++ b/drivers/gpu/drm/bridge/Kconfig > > > @@ -232,6 +232,25 @@ config DRM_TI_TFP410 > > > help > > > Texas Instruments TFP410 DVI/HDMI Transmitter driver > > > > > > +config DRM_TI_SN65DSI84 > > > + tristate "TI SN65DSI84 DSI to LVDS bridge" > > > + depends on OF > > > + select DRM_KMS_HELPER > > > + select REGMAP_I2C > > > + select DRM_PANEL > > > + select DRM_MIPI_DSI > > > + help > > > + Texas Instruments SN65DSI84 Single Channel DSI to Dual-link LVDS > > > + bridge driver. > > > + > > > + Bridge decodes MIPI DSI 18bpp RGB666 and 240bpp RG888 packets > > > and > > > + converts the formatted video data stream to a FlatLink > > > compatible > > > + LVDS output operating at pixel clocks operating from 25 MHx to > > > + 154 MHz. > > > + > > > + SN65DSI84 offers a Dual-Link LVDS, Single-Link LVDS interface > > > with > > > + four data lanes per link. > > > + > > > config DRM_TI_SN65DSI86 > > > tristate "TI SN65DSI86 DSI to eDP bridge" > > > depends on OF > > > diff --git a/drivers/gpu/drm/bridge/Makefile > > > b/drivers/gpu/drm/bridge/Makefile > > > index 86e7acc76f8d..3906052ef639 100644 > > > --- a/drivers/gpu/drm/bridge/Makefile > > > +++ b/drivers/gpu/drm/bridge/Makefile > > > @@ -20,6 +20,7 @@ obj-$(CONFIG_DRM_TOSHIBA_TC358767) += tc358767.o > > > obj-$(CONFIG_DRM_TOSHIBA_TC358768) += tc358768.o > > > obj-$(CONFIG_DRM_TOSHIBA_TC358775) += tc358775.o > > > obj-$(CONFIG_DRM_I2C_ADV7511) += adv7511/ > > > +obj-$(CONFIG_DRM_TI_SN65DSI84) += ti-sn65dsi84.o > > > obj-$(CONFIG_DRM_TI_SN65DSI86) += ti-sn65dsi86.o > > > obj-$(CONFIG_DRM_TI_TFP410) += ti-tfp410.o > > > obj-$(CONFIG_DRM_TI_TPD12S015) += ti-tpd12s015.o > > > diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi84.c > > > b/drivers/gpu/drm/bridge/ti-sn65dsi84.c > > > new file mode 100644 > > > index ..3ed1f9a7d898 > > > --- /dev/null > > > +++ b/drivers/gpu/drm/bridge/ti-sn65dsi84.c > > > @@ -0,0 +1,488 @@ > > > +// SPDX-License-Identifier: GPL-2.0 > > > +/* > > > + * Copyright (c) 2021 Engicam srl > > > + * Copyright (C) 2021 Amarula Solutions(India) > > > + * Author: Jagan Teki > > > + */ > > > + > > > +#include > > > +#include > > > +#include > > > +#include > > > + > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > + > > > +/* sn65dsi84 registers */ > > > +#define SN65DSI_SOFT_RESET 0x09 > > > +#define SN65DSI_LVDS_CLK 0x0a > > > +#define SN65DSI_CLK_DIV0x0b > > > +#define SN65DSI_CLK_PLL0x0d > > > +#define SN65DSI_DSI_CFG0x10 > > > +#define SN65DSI_DSI_CLK_EQ 0x11 > > > +#define SN65DSI_DSI_CLK_RANGE 0x12 > > > +#define SN65DSI_LVDS_MODE 0x18 > > > +#define SN65DSI_CHA_LINE_LO0x20 > > > +#define SN65DSI_CHA_LINE_HI0x21 > > > +#define SN65DSI_CHA_VIRT_LO0x24 > > > +#define SN65DSI_CHA_VIRT_HI0x25 > > > +#define SN65DSI_CHA_SYNC_DELAY_LO 0x28 > > >
Re: [PATCH 2/2] drm: bridge: Add SN65DSI84 DSI to LVDS bridge
Hi Jagan On Wed, Jan 20, 2021 at 12:22 PM Jagan Teki wrote: > > SN65DSI84 is a Single Channel DSI to Dual-link LVDS bridge from > Texas Instruments. > > SN65DSI83, SN65DSI85 are variants of the same family of bridge > controllers. > > Right now the bridge driver is supporting a single link, dual-link > support requires to initiate I2C Channel B registers. > > Tested with STM32MP1 MIPI DSI host design configuration. > > Signed-off-by: Matteo Lisi > Signed-off-by: Jagan Teki > --- > MAINTAINERS | 6 + > drivers/gpu/drm/bridge/Kconfig| 19 + > drivers/gpu/drm/bridge/Makefile | 1 + > drivers/gpu/drm/bridge/ti-sn65dsi84.c | 488 ++ > 4 files changed, 514 insertions(+) > create mode 100644 drivers/gpu/drm/bridge/ti-sn65dsi84.c > > diff --git a/MAINTAINERS b/MAINTAINERS > index 12dd1fff2a39..44750ff7640c 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -5984,6 +5984,12 @@ S: Maintained > F: Documentation/devicetree/bindings/display/ti/ > F: drivers/gpu/drm/omapdrm/ > > +DRM DRIVERS FOR TI SN65DSI84 DSI TO LVDS BRIDGE > +M: Jagan Teki > +S: Maintained > +F: Documentation/devicetree/bindings/display/bridge/ti,sn65dsi84.yaml > +F: drivers/gpu/drm/bridge/ti-sn65dsi84.c > + > DRM DRIVERS FOR V3D > M: Eric Anholt > S: Supported > diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig > index e4110d6ca7b3..6494881bffb3 100644 > --- a/drivers/gpu/drm/bridge/Kconfig > +++ b/drivers/gpu/drm/bridge/Kconfig > @@ -232,6 +232,25 @@ config DRM_TI_TFP410 > help > Texas Instruments TFP410 DVI/HDMI Transmitter driver > > +config DRM_TI_SN65DSI84 > + tristate "TI SN65DSI84 DSI to LVDS bridge" > + depends on OF > + select DRM_KMS_HELPER > + select REGMAP_I2C > + select DRM_PANEL > + select DRM_MIPI_DSI > + help > + Texas Instruments SN65DSI84 Single Channel DSI to Dual-link LVDS > + bridge driver. > + > + Bridge decodes MIPI DSI 18bpp RGB666 and 240bpp RG888 packets and > + converts the formatted video data stream to a FlatLink compatible > + LVDS output operating at pixel clocks operating from 25 MHx to > + 154 MHz. > + > + SN65DSI84 offers a Dual-Link LVDS, Single-Link LVDS interface with > + four data lanes per link. > + > config DRM_TI_SN65DSI86 > tristate "TI SN65DSI86 DSI to eDP bridge" > depends on OF > diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile > index 86e7acc76f8d..3906052ef639 100644 > --- a/drivers/gpu/drm/bridge/Makefile > +++ b/drivers/gpu/drm/bridge/Makefile > @@ -20,6 +20,7 @@ obj-$(CONFIG_DRM_TOSHIBA_TC358767) += tc358767.o > obj-$(CONFIG_DRM_TOSHIBA_TC358768) += tc358768.o > obj-$(CONFIG_DRM_TOSHIBA_TC358775) += tc358775.o > obj-$(CONFIG_DRM_I2C_ADV7511) += adv7511/ > +obj-$(CONFIG_DRM_TI_SN65DSI84) += ti-sn65dsi84.o > obj-$(CONFIG_DRM_TI_SN65DSI86) += ti-sn65dsi86.o > obj-$(CONFIG_DRM_TI_TFP410) += ti-tfp410.o > obj-$(CONFIG_DRM_TI_TPD12S015) += ti-tpd12s015.o > diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi84.c > b/drivers/gpu/drm/bridge/ti-sn65dsi84.c > new file mode 100644 > index ..3ed1f9a7d898 > --- /dev/null > +++ b/drivers/gpu/drm/bridge/ti-sn65dsi84.c > @@ -0,0 +1,488 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (c) 2021 Engicam srl > + * Copyright (C) 2021 Amarula Solutions(India) > + * Author: Jagan Teki > + */ > + > +#include > +#include > +#include > +#include > + > +#include > +#include > +#include > +#include > +#include > + > +/* sn65dsi84 registers */ > +#define SN65DSI_SOFT_RESET 0x09 > +#define SN65DSI_LVDS_CLK 0x0a > +#define SN65DSI_CLK_DIV0x0b > +#define SN65DSI_CLK_PLL0x0d > +#define SN65DSI_DSI_CFG0x10 > +#define SN65DSI_DSI_CLK_EQ 0x11 > +#define SN65DSI_DSI_CLK_RANGE 0x12 > +#define SN65DSI_LVDS_MODE 0x18 > +#define SN65DSI_CHA_LINE_LO0x20 > +#define SN65DSI_CHA_LINE_HI0x21 > +#define SN65DSI_CHA_VIRT_LO0x24 > +#define SN65DSI_CHA_VIRT_HI0x25 > +#define SN65DSI_CHA_SYNC_DELAY_LO 0x28 > +#define SN65DSI_CHA_SYNC_DELAY_HI 0x29 > +#define SN65DSI_CHA_HSYNC_WIDTH_LO 0x2c > +#define SN65DSI_CHA_HSYNC_WIDTH_HI 0x2d > +#define SN65DSI_CHA_VSYNC_WIDTH_LO 0x30 > +#define SN65DSI_CHA_VSYNC_WIDTH_HI 0x31 > +#define SN65DSI_CHA_HBACK_PORCH0x34 > +#define SN65DSI_CHA_VBACK_PORCH0x36 > +#define SN65DSI_CHA_HFRONT_PORCH 0x38 > +#define SN65DSI_CHA_VFRONT_PORCH 0x3a > +#define SN65DSI_CHA_ERR0xe5 > + > +/* sn65dsi register bits */ > +#define SN65DSI_RESET_EN BIT(0) > +#define SN65DSI_PLL_EN BIT(0) > +#define SN65DSI_LVDS_CLK_MASK
Re: [PATCH 2/2] drm: bridge: Add SN65DSI84 DSI to LVDS bridge
On Wed, Jan 20, 2021 at 12:55:40PM +0100, Michael Nazzareno Trimarchi wrote: > On Wed, Jan 20, 2021 at 12:29 PM Jagan Teki wrote: > > On Wed, Jan 20, 2021 at 4:55 PM Michael Nazzareno Trimarchi wrote: > > > On Wed, Jan 20, 2021 at 12:22 PM Jagan Teki wrote: > > > > > > > > SN65DSI84 is a Single Channel DSI to Dual-link LVDS bridge from > > > > Texas Instruments. > > > > > > > > SN65DSI83, SN65DSI85 are variants of the same family of bridge > > > > controllers. > > > > > > > > Right now the bridge driver is supporting a single link, dual-link > > > > support requires to initiate I2C Channel B registers. > > > > > > > > Tested with STM32MP1 MIPI DSI host design configuration. > > > > > > > > Signed-off-by: Matteo Lisi > > > > Signed-off-by: Jagan Teki > > > > --- > > > > MAINTAINERS | 6 + > > > > drivers/gpu/drm/bridge/Kconfig| 19 + > > > > drivers/gpu/drm/bridge/Makefile | 1 + > > > > drivers/gpu/drm/bridge/ti-sn65dsi84.c | 488 ++ > > > > 4 files changed, 514 insertions(+) > > > > create mode 100644 drivers/gpu/drm/bridge/ti-sn65dsi84.c > > > > > > > > diff --git a/MAINTAINERS b/MAINTAINERS > > > > index 12dd1fff2a39..44750ff7640c 100644 > > > > --- a/MAINTAINERS > > > > +++ b/MAINTAINERS > > > > @@ -5984,6 +5984,12 @@ S: Maintained > > > > F: Documentation/devicetree/bindings/display/ti/ > > > > F: drivers/gpu/drm/omapdrm/ > > > > > > > > +DRM DRIVERS FOR TI SN65DSI84 DSI TO LVDS BRIDGE > > > > +M: Jagan Teki > > > > +S: Maintained > > > > +F: > > > > Documentation/devicetree/bindings/display/bridge/ti,sn65dsi84.yaml > > > > +F: drivers/gpu/drm/bridge/ti-sn65dsi84.c > > > > + > > > > DRM DRIVERS FOR V3D > > > > M: Eric Anholt > > > > S: Supported > > > > diff --git a/drivers/gpu/drm/bridge/Kconfig > > > > b/drivers/gpu/drm/bridge/Kconfig > > > > index e4110d6ca7b3..6494881bffb3 100644 > > > > --- a/drivers/gpu/drm/bridge/Kconfig > > > > +++ b/drivers/gpu/drm/bridge/Kconfig > > > > @@ -232,6 +232,25 @@ config DRM_TI_TFP410 > > > > help > > > > Texas Instruments TFP410 DVI/HDMI Transmitter driver > > > > > > > > +config DRM_TI_SN65DSI84 > > > > + tristate "TI SN65DSI84 DSI to LVDS bridge" > > > > + depends on OF > > > > + select DRM_KMS_HELPER > > > > + select REGMAP_I2C > > > > + select DRM_PANEL > > > > + select DRM_MIPI_DSI > > > > + help > > > > + Texas Instruments SN65DSI84 Single Channel DSI to Dual-link > > > > LVDS > > > > + bridge driver. > > > > + > > > > + Bridge decodes MIPI DSI 18bpp RGB666 and 240bpp RG888 packets > > > > and > > > > + converts the formatted video data stream to a FlatLink > > > > compatible > > > > + LVDS output operating at pixel clocks operating from 25 MHx to > > > > + 154 MHz. > > > > + > > > > + SN65DSI84 offers a Dual-Link LVDS, Single-Link LVDS interface > > > > with > > > > + four data lanes per link. > > > > + > > > > config DRM_TI_SN65DSI86 > > > > tristate "TI SN65DSI86 DSI to eDP bridge" > > > > depends on OF > > > > diff --git a/drivers/gpu/drm/bridge/Makefile > > > > b/drivers/gpu/drm/bridge/Makefile > > > > index 86e7acc76f8d..3906052ef639 100644 > > > > --- a/drivers/gpu/drm/bridge/Makefile > > > > +++ b/drivers/gpu/drm/bridge/Makefile > > > > @@ -20,6 +20,7 @@ obj-$(CONFIG_DRM_TOSHIBA_TC358767) += tc358767.o > > > > obj-$(CONFIG_DRM_TOSHIBA_TC358768) += tc358768.o > > > > obj-$(CONFIG_DRM_TOSHIBA_TC358775) += tc358775.o > > > > obj-$(CONFIG_DRM_I2C_ADV7511) += adv7511/ > > > > +obj-$(CONFIG_DRM_TI_SN65DSI84) += ti-sn65dsi84.o > > > > obj-$(CONFIG_DRM_TI_SN65DSI86) += ti-sn65dsi86.o > > > > obj-$(CONFIG_DRM_TI_TFP410) += ti-tfp410.o > > > > obj-$(CONFIG_DRM_TI_TPD12S015) += ti-tpd12s015.o > > > > diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi84.c > > > > b/drivers/gpu/drm/bridge/ti-sn65dsi84.c > > > > new file mode 100644 > > > > index ..3ed1f9a7d898 > > > > --- /dev/null > > > > +++ b/drivers/gpu/drm/bridge/ti-sn65dsi84.c > > > > @@ -0,0 +1,488 @@ > > > > +// SPDX-License-Identifier: GPL-2.0 > > > > +/* > > > > + * Copyright (c) 2021 Engicam srl > > > > + * Copyright (C) 2021 Amarula Solutions(India) > > > > + * Author: Jagan Teki > > > > + */ > > > > + > > > > +#include > > > > +#include > > > > +#include > > > > +#include > > > > + > > > > +#include > > > > +#include > > > > +#include > > > > +#include > > > > +#include > > > > + > > > > +/* sn65dsi84 registers */ > > > > +#define SN65DSI_SOFT_RESET 0x09 > > > > +#define SN65DSI_LVDS_CLK 0x0a > > > > +#define SN65DSI_CLK_DIV0x0b > > > > +#define SN65DSI_CLK_PLL0x0d > > > > +#define SN65DSI_DSI_CFG0x10 > > > > +#define SN65DSI_DSI_CLK_EQ 0x11 > > > > +#define SN65DSI_DSI_CLK_RANGE 0x12 > > > >
Re: [PATCH 2/2] drm: bridge: Add SN65DSI84 DSI to LVDS bridge
On Wed, Jan 20, 2021 at 4:55 PM Michael Nazzareno Trimarchi wrote: > > Hi Jagan > > On Wed, Jan 20, 2021 at 12:22 PM Jagan Teki > wrote: > > > > SN65DSI84 is a Single Channel DSI to Dual-link LVDS bridge from > > Texas Instruments. > > > > SN65DSI83, SN65DSI85 are variants of the same family of bridge > > controllers. > > > > Right now the bridge driver is supporting a single link, dual-link > > support requires to initiate I2C Channel B registers. > > > > Tested with STM32MP1 MIPI DSI host design configuration. > > > > Signed-off-by: Matteo Lisi > > Signed-off-by: Jagan Teki > > --- > > MAINTAINERS | 6 + > > drivers/gpu/drm/bridge/Kconfig| 19 + > > drivers/gpu/drm/bridge/Makefile | 1 + > > drivers/gpu/drm/bridge/ti-sn65dsi84.c | 488 ++ > > 4 files changed, 514 insertions(+) > > create mode 100644 drivers/gpu/drm/bridge/ti-sn65dsi84.c > > > > diff --git a/MAINTAINERS b/MAINTAINERS > > index 12dd1fff2a39..44750ff7640c 100644 > > --- a/MAINTAINERS > > +++ b/MAINTAINERS > > @@ -5984,6 +5984,12 @@ S: Maintained > > F: Documentation/devicetree/bindings/display/ti/ > > F: drivers/gpu/drm/omapdrm/ > > > > +DRM DRIVERS FOR TI SN65DSI84 DSI TO LVDS BRIDGE > > +M: Jagan Teki > > +S: Maintained > > +F: Documentation/devicetree/bindings/display/bridge/ti,sn65dsi84.yaml > > +F: drivers/gpu/drm/bridge/ti-sn65dsi84.c > > + > > DRM DRIVERS FOR V3D > > M: Eric Anholt > > S: Supported > > diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig > > index e4110d6ca7b3..6494881bffb3 100644 > > --- a/drivers/gpu/drm/bridge/Kconfig > > +++ b/drivers/gpu/drm/bridge/Kconfig > > @@ -232,6 +232,25 @@ config DRM_TI_TFP410 > > help > > Texas Instruments TFP410 DVI/HDMI Transmitter driver > > > > +config DRM_TI_SN65DSI84 > > + tristate "TI SN65DSI84 DSI to LVDS bridge" > > + depends on OF > > + select DRM_KMS_HELPER > > + select REGMAP_I2C > > + select DRM_PANEL > > + select DRM_MIPI_DSI > > + help > > + Texas Instruments SN65DSI84 Single Channel DSI to Dual-link LVDS > > + bridge driver. > > + > > + Bridge decodes MIPI DSI 18bpp RGB666 and 240bpp RG888 packets and > > + converts the formatted video data stream to a FlatLink compatible > > + LVDS output operating at pixel clocks operating from 25 MHx to > > + 154 MHz. > > + > > + SN65DSI84 offers a Dual-Link LVDS, Single-Link LVDS interface with > > + four data lanes per link. > > + > > config DRM_TI_SN65DSI86 > > tristate "TI SN65DSI86 DSI to eDP bridge" > > depends on OF > > diff --git a/drivers/gpu/drm/bridge/Makefile > > b/drivers/gpu/drm/bridge/Makefile > > index 86e7acc76f8d..3906052ef639 100644 > > --- a/drivers/gpu/drm/bridge/Makefile > > +++ b/drivers/gpu/drm/bridge/Makefile > > @@ -20,6 +20,7 @@ obj-$(CONFIG_DRM_TOSHIBA_TC358767) += tc358767.o > > obj-$(CONFIG_DRM_TOSHIBA_TC358768) += tc358768.o > > obj-$(CONFIG_DRM_TOSHIBA_TC358775) += tc358775.o > > obj-$(CONFIG_DRM_I2C_ADV7511) += adv7511/ > > +obj-$(CONFIG_DRM_TI_SN65DSI84) += ti-sn65dsi84.o > > obj-$(CONFIG_DRM_TI_SN65DSI86) += ti-sn65dsi86.o > > obj-$(CONFIG_DRM_TI_TFP410) += ti-tfp410.o > > obj-$(CONFIG_DRM_TI_TPD12S015) += ti-tpd12s015.o > > diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi84.c > > b/drivers/gpu/drm/bridge/ti-sn65dsi84.c > > new file mode 100644 > > index ..3ed1f9a7d898 > > --- /dev/null > > +++ b/drivers/gpu/drm/bridge/ti-sn65dsi84.c > > @@ -0,0 +1,488 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +/* > > + * Copyright (c) 2021 Engicam srl > > + * Copyright (C) 2021 Amarula Solutions(India) > > + * Author: Jagan Teki > > + */ > > + > > +#include > > +#include > > +#include > > +#include > > + > > +#include > > +#include > > +#include > > +#include > > +#include > > + > > +/* sn65dsi84 registers */ > > +#define SN65DSI_SOFT_RESET 0x09 > > +#define SN65DSI_LVDS_CLK 0x0a > > +#define SN65DSI_CLK_DIV0x0b > > +#define SN65DSI_CLK_PLL0x0d > > +#define SN65DSI_DSI_CFG0x10 > > +#define SN65DSI_DSI_CLK_EQ 0x11 > > +#define SN65DSI_DSI_CLK_RANGE 0x12 > > +#define SN65DSI_LVDS_MODE 0x18 > > +#define SN65DSI_CHA_LINE_LO0x20 > > +#define SN65DSI_CHA_LINE_HI0x21 > > +#define SN65DSI_CHA_VIRT_LO0x24 > > +#define SN65DSI_CHA_VIRT_HI0x25 > > +#define SN65DSI_CHA_SYNC_DELAY_LO 0x28 > > +#define SN65DSI_CHA_SYNC_DELAY_HI 0x29 > > +#define SN65DSI_CHA_HSYNC_WIDTH_LO 0x2c > > +#define SN65DSI_CHA_HSYNC_WIDTH_HI 0x2d > > +#define SN65DSI_CHA_VSYNC_WIDTH_LO 0x30 > > +#define SN65DSI_CHA_VSYNC_WIDTH_HI 0x31 > > +#define SN65DSI_CHA_HBACK_PORCH0x34 > > +#define SN65DSI_CHA_VBACK_PORCH
[PATCH 2/2] drm: bridge: Add SN65DSI84 DSI to LVDS bridge
SN65DSI84 is a Single Channel DSI to Dual-link LVDS bridge from Texas Instruments. SN65DSI83, SN65DSI85 are variants of the same family of bridge controllers. Right now the bridge driver is supporting a single link, dual-link support requires to initiate I2C Channel B registers. Tested with STM32MP1 MIPI DSI host design configuration. Signed-off-by: Matteo Lisi Signed-off-by: Jagan Teki --- MAINTAINERS | 6 + drivers/gpu/drm/bridge/Kconfig| 19 + drivers/gpu/drm/bridge/Makefile | 1 + drivers/gpu/drm/bridge/ti-sn65dsi84.c | 488 ++ 4 files changed, 514 insertions(+) create mode 100644 drivers/gpu/drm/bridge/ti-sn65dsi84.c diff --git a/MAINTAINERS b/MAINTAINERS index 12dd1fff2a39..44750ff7640c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -5984,6 +5984,12 @@ S: Maintained F: Documentation/devicetree/bindings/display/ti/ F: drivers/gpu/drm/omapdrm/ +DRM DRIVERS FOR TI SN65DSI84 DSI TO LVDS BRIDGE +M: Jagan Teki +S: Maintained +F: Documentation/devicetree/bindings/display/bridge/ti,sn65dsi84.yaml +F: drivers/gpu/drm/bridge/ti-sn65dsi84.c + DRM DRIVERS FOR V3D M: Eric Anholt S: Supported diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig index e4110d6ca7b3..6494881bffb3 100644 --- a/drivers/gpu/drm/bridge/Kconfig +++ b/drivers/gpu/drm/bridge/Kconfig @@ -232,6 +232,25 @@ config DRM_TI_TFP410 help Texas Instruments TFP410 DVI/HDMI Transmitter driver +config DRM_TI_SN65DSI84 + tristate "TI SN65DSI84 DSI to LVDS bridge" + depends on OF + select DRM_KMS_HELPER + select REGMAP_I2C + select DRM_PANEL + select DRM_MIPI_DSI + help + Texas Instruments SN65DSI84 Single Channel DSI to Dual-link LVDS + bridge driver. + + Bridge decodes MIPI DSI 18bpp RGB666 and 240bpp RG888 packets and + converts the formatted video data stream to a FlatLink compatible + LVDS output operating at pixel clocks operating from 25 MHx to + 154 MHz. + + SN65DSI84 offers a Dual-Link LVDS, Single-Link LVDS interface with + four data lanes per link. + config DRM_TI_SN65DSI86 tristate "TI SN65DSI86 DSI to eDP bridge" depends on OF diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile index 86e7acc76f8d..3906052ef639 100644 --- a/drivers/gpu/drm/bridge/Makefile +++ b/drivers/gpu/drm/bridge/Makefile @@ -20,6 +20,7 @@ obj-$(CONFIG_DRM_TOSHIBA_TC358767) += tc358767.o obj-$(CONFIG_DRM_TOSHIBA_TC358768) += tc358768.o obj-$(CONFIG_DRM_TOSHIBA_TC358775) += tc358775.o obj-$(CONFIG_DRM_I2C_ADV7511) += adv7511/ +obj-$(CONFIG_DRM_TI_SN65DSI84) += ti-sn65dsi84.o obj-$(CONFIG_DRM_TI_SN65DSI86) += ti-sn65dsi86.o obj-$(CONFIG_DRM_TI_TFP410) += ti-tfp410.o obj-$(CONFIG_DRM_TI_TPD12S015) += ti-tpd12s015.o diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi84.c b/drivers/gpu/drm/bridge/ti-sn65dsi84.c new file mode 100644 index ..3ed1f9a7d898 --- /dev/null +++ b/drivers/gpu/drm/bridge/ti-sn65dsi84.c @@ -0,0 +1,488 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2021 Engicam srl + * Copyright (C) 2021 Amarula Solutions(India) + * Author: Jagan Teki + */ + +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +/* sn65dsi84 registers */ +#define SN65DSI_SOFT_RESET 0x09 +#define SN65DSI_LVDS_CLK 0x0a +#define SN65DSI_CLK_DIV0x0b +#define SN65DSI_CLK_PLL0x0d +#define SN65DSI_DSI_CFG0x10 +#define SN65DSI_DSI_CLK_EQ 0x11 +#define SN65DSI_DSI_CLK_RANGE 0x12 +#define SN65DSI_LVDS_MODE 0x18 +#define SN65DSI_CHA_LINE_LO0x20 +#define SN65DSI_CHA_LINE_HI0x21 +#define SN65DSI_CHA_VIRT_LO0x24 +#define SN65DSI_CHA_VIRT_HI0x25 +#define SN65DSI_CHA_SYNC_DELAY_LO 0x28 +#define SN65DSI_CHA_SYNC_DELAY_HI 0x29 +#define SN65DSI_CHA_HSYNC_WIDTH_LO 0x2c +#define SN65DSI_CHA_HSYNC_WIDTH_HI 0x2d +#define SN65DSI_CHA_VSYNC_WIDTH_LO 0x30 +#define SN65DSI_CHA_VSYNC_WIDTH_HI 0x31 +#define SN65DSI_CHA_HBACK_PORCH0x34 +#define SN65DSI_CHA_VBACK_PORCH0x36 +#define SN65DSI_CHA_HFRONT_PORCH 0x38 +#define SN65DSI_CHA_VFRONT_PORCH 0x3a +#define SN65DSI_CHA_ERR0xe5 + +/* sn65dsi register bits */ +#define SN65DSI_RESET_EN BIT(0) +#define SN65DSI_PLL_EN BIT(0) +#define SN65DSI_LVDS_CLK_MASK GENMASK(3, 1) +#define SN65DSI_LVDS_CLK_SHIFT 1 +#define SN65DSI_LVDS_CLK_SRC_DSI BIT(0) +#define SN65DSI_CLK_DIV_MASK GENMASK(7, 3) +#define SN65DSI_CLK_DIV_SHIFT 3 +#define SN65DSI_DSI_LANE_MASK GENMASK(4, 3) +#define SN65DSI_DSI_LANE_SHIFT 3 +#define SN65DSI_LVDS_LINK_CFG
