Re: [PATCH 4/5] drm/msm/adreno: Move hwcg table into a6xx specific info

2023-12-06 Thread Dmitry Baryshkov 
On Wed, 6 Dec 2023 at 00:06, Rob Clark  wrote:
>
> From: Rob Clark 
>
> Introduce a6xx_info where we can stash gen specific stuff without
> polluting the toplevel adreno_info struct.
>
> Signed-off-by: Rob Clark 
> ---
>  drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 55 +--
>  drivers/gpu/drm/msm/adreno/a6xx_gpu.c |  4 +-
>  drivers/gpu/drm/msm/adreno/a6xx_gpu.h |  9 
>  drivers/gpu/drm/msm/adreno/adreno_gpu.h   |  6 ++-
>  4 files changed, 58 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c 
> b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> index a35d4c112a61..3fb9e249567a 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> @@ -7,6 +7,7 @@
>   */
>
>  #include "adreno_gpu.h"
> +#include "a6xx_gpu.h"
>  #include "a6xx.xml.h"
>  #include "a6xx_gmu.xml.h"
>
> @@ -465,7 +466,9 @@ const struct adreno_info a6xx_gpus[] = {
> .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> .init = a6xx_gpu_init,
> .zapfw = "a610_zap.mdt",
> -   .hwcg = a612_hwcg,
> +   .a6xx = &(struct a6xx_info) {
> +   .hwcg = a612_hwcg,
> +   },
> /*
>  * There are (at least) three SoCs implementing A610: SM6125
>  * (trinket), SM6115 (bengal) and SM6225 (khaje). Trinket does
> @@ -492,6 +495,8 @@ const struct adreno_info a6xx_gpus[] = {
> .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
> .init = a6xx_gpu_init,
> +   .a6xx = &(struct a6xx_info) {
> +   },
> .speedbins = ADRENO_SPEEDBINS(
> { 0,   0 },
> { 169, 1 },
> @@ -510,7 +515,9 @@ const struct adreno_info a6xx_gpus[] = {
> .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> .init = a6xx_gpu_init,
> .zapfw = "a615_zap.mdt",
> -   .hwcg = a615_hwcg,
> +   .a6xx = &(struct a6xx_info) {
> +   .hwcg = a615_hwcg,
> +   },
> .speedbins = ADRENO_SPEEDBINS(
> { 0,   0 },
> { 138, 1 },
> @@ -529,7 +536,9 @@ const struct adreno_info a6xx_gpus[] = {
> .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> .init = a6xx_gpu_init,
> .zapfw = "a615_zap.mdt",
> -   .hwcg = a615_hwcg,
> +   .a6xx = &(struct a6xx_info) {
> +   .hwcg = a615_hwcg,
> +   },
> .speedbins = ADRENO_SPEEDBINS(
> { 0,   0 },
> { 190, 1 },
> @@ -548,7 +557,9 @@ const struct adreno_info a6xx_gpus[] = {
> .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
> .init = a6xx_gpu_init,
> .zapfw = "a615_zap.mdt",
> -   .hwcg = a615_hwcg,
> +   .a6xx = &(struct a6xx_info) {
> +   .hwcg = a615_hwcg,
> +   },
> .speedbins = ADRENO_SPEEDBINS(
> { 0,   0 },
> { 120, 4 },
> @@ -572,7 +583,9 @@ const struct adreno_info a6xx_gpus[] = {
> .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
> .init = a6xx_gpu_init,
> .zapfw = "a630_zap.mdt",
> -   .hwcg = a630_hwcg,
> +   .a6xx = &(struct a6xx_info) {
> +   .hwcg = a630_hwcg,
> +   },
> }, {
> .chip_ids = ADRENO_CHIP_IDS(0x06040001),
> .family = ADRENO_6XX_GEN2,
> @@ -586,7 +599,9 @@ const struct adreno_info a6xx_gpus[] = {
> .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
> .init = a6xx_gpu_init,
> .zapfw = "a640_zap.mdt",
> -   .hwcg = a640_hwcg,
> +   .a6xx = &(struct a6xx_info) {
> +   .hwcg = a640_hwcg,
> +   },
> .speedbins = ADRENO_SPEEDBINS(
> { 0, 0 },
> { 1, 1 },
> @@ -605,7 +620,9 @@ const struct adreno_info a6xx_gpus[] = {
> ADRENO_QUIRK_HAS_HW_APRIV,
> .init = a6xx_gpu_init,
> .zapfw = "a650_zap.mdt",
> -   .hwcg = a650_hwcg,
> +   .a6xx = &(struct a6xx_info) {
> +   .hwcg = a650_hwcg,
> +   },
> .address_space_size = SZ_16G,
> .speedbins = ADRENO_SPEEDBINS(
> { 0, 0 },
> @@ -627,7 +644,9 @@ const struct adreno_info a6xx_gpus[] = {
> ADRENO_QUIRK_HAS_HW_APRIV,
> .init = a6xx_gpu_init,
> .zapfw = "a660_zap.mdt",
> -   .hwcg = a660_hwcg,
> +

[PATCH 4/5] drm/msm/adreno: Move hwcg table into a6xx specific info

2023-12-05 Thread Rob Clark 
From: Rob Clark 

Introduce a6xx_info where we can stash gen specific stuff without
polluting the toplevel adreno_info struct.

Signed-off-by: Rob Clark 
---
 drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 55 +--
 drivers/gpu/drm/msm/adreno/a6xx_gpu.c |  4 +-
 drivers/gpu/drm/msm/adreno/a6xx_gpu.h |  9 
 drivers/gpu/drm/msm/adreno/adreno_gpu.h   |  6 ++-
 4 files changed, 58 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c 
b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
index a35d4c112a61..3fb9e249567a 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
@@ -7,6 +7,7 @@
  */
 
 #include "adreno_gpu.h"
+#include "a6xx_gpu.h"
 #include "a6xx.xml.h"
 #include "a6xx_gmu.xml.h"
 
@@ -465,7 +466,9 @@ const struct adreno_info a6xx_gpus[] = {
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
.init = a6xx_gpu_init,
.zapfw = "a610_zap.mdt",
-   .hwcg = a612_hwcg,
+   .a6xx = &(struct a6xx_info) {
+   .hwcg = a612_hwcg,
+   },
/*
 * There are (at least) three SoCs implementing A610: SM6125
 * (trinket), SM6115 (bengal) and SM6225 (khaje). Trinket does
@@ -492,6 +495,8 @@ const struct adreno_info a6xx_gpus[] = {
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
.quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
.init = a6xx_gpu_init,
+   .a6xx = &(struct a6xx_info) {
+   },
.speedbins = ADRENO_SPEEDBINS(
{ 0,   0 },
{ 169, 1 },
@@ -510,7 +515,9 @@ const struct adreno_info a6xx_gpus[] = {
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
.init = a6xx_gpu_init,
.zapfw = "a615_zap.mdt",
-   .hwcg = a615_hwcg,
+   .a6xx = &(struct a6xx_info) {
+   .hwcg = a615_hwcg,
+   },
.speedbins = ADRENO_SPEEDBINS(
{ 0,   0 },
{ 138, 1 },
@@ -529,7 +536,9 @@ const struct adreno_info a6xx_gpus[] = {
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
.init = a6xx_gpu_init,
.zapfw = "a615_zap.mdt",
-   .hwcg = a615_hwcg,
+   .a6xx = &(struct a6xx_info) {
+   .hwcg = a615_hwcg,
+   },
.speedbins = ADRENO_SPEEDBINS(
{ 0,   0 },
{ 190, 1 },
@@ -548,7 +557,9 @@ const struct adreno_info a6xx_gpus[] = {
.quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
.init = a6xx_gpu_init,
.zapfw = "a615_zap.mdt",
-   .hwcg = a615_hwcg,
+   .a6xx = &(struct a6xx_info) {
+   .hwcg = a615_hwcg,
+   },
.speedbins = ADRENO_SPEEDBINS(
{ 0,   0 },
{ 120, 4 },
@@ -572,7 +583,9 @@ const struct adreno_info a6xx_gpus[] = {
.quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
.init = a6xx_gpu_init,
.zapfw = "a630_zap.mdt",
-   .hwcg = a630_hwcg,
+   .a6xx = &(struct a6xx_info) {
+   .hwcg = a630_hwcg,
+   },
}, {
.chip_ids = ADRENO_CHIP_IDS(0x06040001),
.family = ADRENO_6XX_GEN2,
@@ -586,7 +599,9 @@ const struct adreno_info a6xx_gpus[] = {
.quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
.init = a6xx_gpu_init,
.zapfw = "a640_zap.mdt",
-   .hwcg = a640_hwcg,
+   .a6xx = &(struct a6xx_info) {
+   .hwcg = a640_hwcg,
+   },
.speedbins = ADRENO_SPEEDBINS(
{ 0, 0 },
{ 1, 1 },
@@ -605,7 +620,9 @@ const struct adreno_info a6xx_gpus[] = {
ADRENO_QUIRK_HAS_HW_APRIV,
.init = a6xx_gpu_init,
.zapfw = "a650_zap.mdt",
-   .hwcg = a650_hwcg,
+   .a6xx = &(struct a6xx_info) {
+   .hwcg = a650_hwcg,
+   },
.address_space_size = SZ_16G,
.speedbins = ADRENO_SPEEDBINS(
{ 0, 0 },
@@ -627,7 +644,9 @@ const struct adreno_info a6xx_gpus[] = {
ADRENO_QUIRK_HAS_HW_APRIV,
.init = a6xx_gpu_init,
.zapfw = "a660_zap.mdt",
-   .hwcg = a660_hwcg,
+   .a6xx = &(struct a6xx_info) {
+   .hwcg = a660_hwcg,
+   },
.address_space_size = SZ_16G,
}, {
.chip_ids = ADRENO_CHIP_IDS(0x06030500),
@@ -642,7 +661,9 @@ const struct adreno_info a6xx_gpus[] =