From: Yongqiang Niu
This patch add support for mediatek SOC MT8183
Signed-off-by: Yongqiang Niu
---
drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 18 +
drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 7 ++
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 131 ++-
drivers/gpu/drm/mediatek/mtk_drm_ddp.h | 1 +
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 44 +++
5 files changed, 197 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
index 3b2ce77..5bda3dd 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
@@ -372,11 +372,29 @@ static int mtk_disp_ovl_remove(struct platform_device
*pdev)
.fmt_rgb565_is_0 = true,
};
+static const struct mtk_disp_ovl_data mt8183_ovl_driver_data = {
+ .addr = DISP_REG_OVL_ADDR_MT8173,
+ .gmc_bits = 10,
+ .layer_nr = 4,
+ .fmt_rgb565_is_0 = true,
+};
+
+static const struct mtk_disp_ovl_data mt8183_ovl_2l_driver_data = {
+ .addr = DISP_REG_OVL_ADDR_MT8173,
+ .gmc_bits = 10,
+ .layer_nr = 2,
+ .fmt_rgb565_is_0 = true,
+};
+
static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = {
{ .compatible = "mediatek,mt2701-disp-ovl",
.data = _ovl_driver_data},
{ .compatible = "mediatek,mt8173-disp-ovl",
.data = _ovl_driver_data},
+ { .compatible = "mediatek,mt8183-disp-ovl",
+ .data = _ovl_driver_data},
+ { .compatible = "mediatek,mt8183-disp-ovl-2l",
+ .data = _ovl_2l_driver_data},
{},
};
MODULE_DEVICE_TABLE(of, mtk_disp_ovl_driver_dt_match);
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
index 3f9b4d4..5fffe91 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
@@ -350,11 +350,18 @@ static int mtk_disp_rdma_remove(struct platform_device
*pdev)
.fifo_size1 = SZ_8K,
};
+static const struct mtk_disp_rdma_data mt8183_rdma_driver_data = {
+ .fifo_size = 5 * SZ_1K,
+ .fifo_size1 = SZ_2K,
+};
+
static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
{ .compatible = "mediatek,mt2701-disp-rdma",
.data = _rdma_driver_data},
{ .compatible = "mediatek,mt8173-disp-rdma",
.data = _rdma_driver_data},
+ { .compatible = "mediatek,mt8183-disp-rdma",
+ .data = _rdma_driver_data},
{},
};
MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match);
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index 4be3c11..165843d 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
@@ -11,6 +11,7 @@
* GNU General Public License for more details.
*/
+#include
#include
#include
#include
@@ -41,8 +42,36 @@
#define DISP_REG_CONFIG_DSI_SEL0x050
#define DISP_REG_CONFIG_DPI_SEL0x064
+#define MT8183_DISP_OVL0_MOUT_EN 0xF00
+#define OVL0_MOUT_EN_DISP_PATH0BIT(0)
+#define OVL0_MOUT_EN_OVL0_2L BIT(4)
+#define MT8183_DISP_OVL0_2L_MOUT_EN0xF04
+#define OVL0_2L_MOUT_EN_DISP_PATH0 BIT(0)
+#define MT8183_DISP_OVL1_2L_MOUT_EN0xF08
+#define OVL1_2L_MOUT_EN_RDMA1 BIT(4)
+#define MT8183_DISP_DITHER0_MOUT_EN0xF0C
+#define DITHER0_MOUT_IN_DSI0 BIT(0)
+#define MT8183_DISP_PATH0_SEL_IN 0xF24
+#define DISP_PATH0_SEL_IN_OVL0 0x0
+#define DISP_PATH0_SEL_IN_OVL0_2L 0x1
+#define MT8183_DISP_DSI0_SEL_IN0xF2C
+#define DSI0_SEL_IN_DITHER 0x0
+#define DSI0_SEL_IN_RDMA0 0x1
+#define MT8183_DSI0_SEL_IN_RDMA1 0x3
+#define MT8183_DISP_DPI0_SEL_IN0xF30
+#define MT8183_DPI0_SEL_IN_RDMA0 0x1
+#define MT8183_DPI0_SEL_IN_RDMA1 0x2
+#define MT8183_DISP_RDMA0_SOUT_SEL_IN 0xF50
+#define MT8183_RDMA0_SOUT_DSI0 0x0
+#define MT8183_RDMA0_SOUT_COLOR0 0x1
+#define MT8183_DISP_RDMA1_SOUT_SEL_IN 0xF54
+#define MT8183_RDMA1_SOUT_DPI0 0x0
+#define MT8183_RDMA1_SOUT_DSI0 0x1
+
#define MT2701_DISP_MUTEX0_MOD0 0x2C
#define MT2701_DISP_MUTEX0_SOF0 0x30
+#define MT8183_DISP_MUTEX0_MOD0 0x30
+#define MT8183_DISP_MUTEX0_SOF 0x2C
#define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n))
#define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n))
@@ -53,6 +82,18 @@
#define INT_MUTEX BIT(1)
+#define MT8183_MUTEX_MOD_DISP_RDMA00
+#define MT8183_MUTEX_MOD_DISP_RDMA11
+#define MT8183_MUTEX_MOD_DISP_OVL0 9
+#define MT8183_MUTEX_MOD_DISP_OVL0_2L 10
+#define MT8183_MUTEX_MOD_DISP_OVL1_2L
