https://bugs.freedesktop.org/show_bug.cgi?id=97305
--- Comment #13 from Matias N. Goldberg ---
I've added a "Proof of the bug".
There IS a bug. I don't know if it's software or in the hardware. The attached
sample does the following:
1. Create a 1MB buffer.
2. Fill the first 4kb with the
https://bugs.freedesktop.org/show_bug.cgi?id=97305
--- Comment #12 from Matias N. Goldberg ---
Created attachment 125723
--> https://bugs.freedesktop.org/attachment.cgi?id=125723=edit
Proof of the bug
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https://bugs.freedesktop.org/show_bug.cgi?id=97305
--- Comment #11 from Ilia Mirkin ---
(In reply to Marek Olšák from comment #10)
> (In reply to Ilia Mirkin from comment #9)
> > (In reply to Marek Olšák from comment #5)
> > > Pre-GCN cards require an alignment of 256 bytes for uniform
https://bugs.freedesktop.org/show_bug.cgi?id=97305
--- Comment #10 from Marek Olšák ---
(In reply to Ilia Mirkin from comment #9)
> (In reply to Marek Olšák from comment #5)
> > Pre-GCN cards require an alignment of 256 bytes for uniform buffers. GCN
> > cards only require 4 byte alignment
https://bugs.freedesktop.org/show_bug.cgi?id=97305
--- Comment #9 from Ilia Mirkin ---
(In reply to Marek Olšák from comment #5)
> Pre-GCN cards require an alignment of 256 bytes for uniform buffers. GCN
> cards only require 4 byte alignment there.
>
> All other buffer binding points require
https://bugs.freedesktop.org/show_bug.cgi?id=97305
--- Comment #8 from Marek Olšák ---
> Nonetheless given that AMD always sets it to 256 ...
Not true. The Mesa driver is also developed by us. Nicolai and me work for AMD.
There is also the Vulkan driver which returns "1 byte" for the texture
https://bugs.freedesktop.org/show_bug.cgi?id=97305
--- Comment #7 from Matias N. Goldberg ---
Our code is complex so if you keep insisting 4 byte alignment is correct, I
won't deny the possibility it could be a bug in our codebase. I would have to
create a simple as possible case to double check
https://bugs.freedesktop.org/show_bug.cgi?id=97305
--- Comment #6 from Matias N. Goldberg ---
I'm back.
I only tested texture and uniform buffers, not SSBOs.
Results:
* Setting UBOs to 4 byte alignments didn't seem to matter in any way.
Performance didn't seem to be affected either.
https://bugs.freedesktop.org/show_bug.cgi?id=97305
Marek Olšák changed:
What|Removed |Added
Resolution|--- |NOTABUG
Status|NEW
https://bugs.freedesktop.org/show_bug.cgi?id=97305
--- Comment #4 from Matias N. Goldberg ---
Sure I will try 16 but not 256
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https://bugs.freedesktop.org/show_bug.cgi?id=97305
--- Comment #3 from Matias N. Goldberg ---
>> BEGIN PATCH
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c
b/src/gallium/drivers/radeonsi/si_pipe.c
index 88f4f20..6a2d5bc 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++
https://bugs.freedesktop.org/show_bug.cgi?id=97305
--- Comment #2 from Nicolai Hähnle ---
I agree with Ilia. There should be no requirement for an alignment greater than
the "texel" size, that really wouldn't make sense given how the hardware works.
Can you please try with 16-but-not-256
https://bugs.freedesktop.org/show_bug.cgi?id=97305
--- Comment #1 from Ilia Mirkin ---
(In reply to Matias N. Goldberg from comment #0)
> But the following did not:
> glTexBufferRange( GL_TEXTURE_BUFFER, GL_RGBA32F, boName,
> offsetAlignedTo4ButNotTo256, sizeBytes );
> uniform samplerBuffer
https://bugs.freedesktop.org/show_bug.cgi?id=97305
Bug ID: 97305
Summary: Wrong values returned by
GL_UNIFORM_BUFFER_OFFSET_ALIGNMENT &
GL_TEXTURE_BUFFER_OFFSET_ALIGNMENT randomly breaks
stuff
Product:
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