Re: [Freedreno] [PATCH v2 3/6] drm/msm/dpu: split interrupt address arrays

2023-05-26 Thread Abhinav Kumar 




On 5/26/2023 1:43 AM, Dmitry Baryshkov wrote:

On Fri, 26 May 2023 at 01:42, Abhinav Kumar  wrote:

On 5/25/2023 3:30 PM, Dmitry Baryshkov wrote:

On Fri, 26 May 2023 at 00:40, Jeykumar Sankaran
 wrote:

On 5/22/2023 2:45 PM, Dmitry Baryshkov wrote:

There is no point in having a single enum (and a single array) for both
DPU < 7.0 and DPU >= 7.0 interrupt registers. Instead define a single
enum and two IRQ address arrays.

Signed-off-by: Dmitry Baryshkov 
---
.../msm/disp/dpu1/catalog/dpu_7_0_sm8350.h|  1 +
.../msm/disp/dpu1/catalog/dpu_7_2_sc7280.h|  1 +
.../msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h  |  1 +
.../msm/disp/dpu1/catalog/dpu_8_1_sm8450.h|  1 +
.../msm/disp/dpu1/catalog/dpu_9_0_sm8550.h|  1 +
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h|  2 +
.../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 82 +--
.../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 28 ---
8 files changed, 79 insertions(+), 38 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h 
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
index 3c1b2c13398d..320cfa4be633 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
@@ -15,6 +15,7 @@ static const struct dpu_caps sm8350_dpu_caps = {
.has_dim_layer = true,
.has_idle_pc = true,
.has_3d_merge = true,
+ .has_7xxx_intr = true,
.max_linewidth = 4096,
.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h 
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
index 5d894cbb0a62..9306c7a115e9 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
@@ -13,6 +13,7 @@ static const struct dpu_caps sc7280_dpu_caps = {
.qseed_type = DPU_SSPP_SCALER_QSEED4,
.has_dim_layer = true,
.has_idle_pc = true,
+ .has_7xxx_intr = true,
.max_linewidth = 2400,
.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h 
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
index c3f1ae000a21..fc1e17c495f0 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
@@ -15,6 +15,7 @@ static const struct dpu_caps sc8280xp_dpu_caps = {
.has_dim_layer = true,
.has_idle_pc = true,
.has_3d_merge = true,
+ .has_7xxx_intr = true,
.max_linewidth = 5120,
.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h 
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
index 86c2e68ebd2c..eb72411c16db 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
@@ -14,6 +14,7 @@ static const struct dpu_caps sm8450_dpu_caps = {
.has_src_split = true,
.has_dim_layer = true,
.has_idle_pc = true,
+ .has_7xxx_intr = true,
.has_3d_merge = true,
.max_linewidth = 5120,
.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h 
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
index 85dc34458b88..8209ca317bdc 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
@@ -15,6 +15,7 @@ static const struct dpu_caps sm8550_dpu_caps = {
.has_dim_layer = true,
.has_idle_pc = true,
.has_3d_merge = true,
+ .has_7xxx_intr = true,
.max_linewidth = 5120,
.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 677048cc3b7d..72530ebb0ae6 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -351,6 +351,7 @@ struct dpu_rotation_cfg {
 * @has_dim_layer  dim layer feature status
 * @has_idle_pcindicate if idle power collapse feature is supported
 * @has_3d_merge   indicate if 3D merge is supported
+ * @has_7xxx_intr  indicate that INTF/IRQs use addressing for DPU 7.0 and 
greater


I see the requirement to distinguish feature support based on the DPU
version in more than one series. Is it a good idea to bring in the DPU
version info in chipset catalog? This will relieve us from maintaining
such version flags for individual HW sub-blocks.


This would not play well with the rest of the driver. The driver
usually does not compute features by DPU revision. Instead it lists
feature flags.



So I am increasingly seeing examples such as data_compress, widebus
where it looks like version based enablement in the code will be

Re: [Freedreno] [PATCH v2 3/6] drm/msm/dpu: split interrupt address arrays

2023-05-26 Thread Dmitry Baryshkov 
On Fri, 26 May 2023 at 01:42, Abhinav Kumar  wrote:
> On 5/25/2023 3:30 PM, Dmitry Baryshkov wrote:
> > On Fri, 26 May 2023 at 00:40, Jeykumar Sankaran
> >  wrote:
> >> On 5/22/2023 2:45 PM, Dmitry Baryshkov wrote:
> >>> There is no point in having a single enum (and a single array) for both
> >>> DPU < 7.0 and DPU >= 7.0 interrupt registers. Instead define a single
> >>> enum and two IRQ address arrays.
> >>>
> >>> Signed-off-by: Dmitry Baryshkov 
> >>> ---
> >>>.../msm/disp/dpu1/catalog/dpu_7_0_sm8350.h|  1 +
> >>>.../msm/disp/dpu1/catalog/dpu_7_2_sc7280.h|  1 +
> >>>.../msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h  |  1 +
> >>>.../msm/disp/dpu1/catalog/dpu_8_1_sm8450.h|  1 +
> >>>.../msm/disp/dpu1/catalog/dpu_9_0_sm8550.h|  1 +
> >>>.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h|  2 +
> >>>.../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 82 +--
> >>>.../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 28 ---
> >>>8 files changed, 79 insertions(+), 38 deletions(-)
> >>>
> >>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h 
> >>> b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> >>> index 3c1b2c13398d..320cfa4be633 100644
> >>> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> >>> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> >>> @@ -15,6 +15,7 @@ static const struct dpu_caps sm8350_dpu_caps = {
> >>>.has_dim_layer = true,
> >>>.has_idle_pc = true,
> >>>.has_3d_merge = true,
> >>> + .has_7xxx_intr = true,
> >>>.max_linewidth = 4096,
> >>>.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
> >>>};
> >>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h 
> >>> b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> >>> index 5d894cbb0a62..9306c7a115e9 100644
> >>> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> >>> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> >>> @@ -13,6 +13,7 @@ static const struct dpu_caps sc7280_dpu_caps = {
> >>>.qseed_type = DPU_SSPP_SCALER_QSEED4,
> >>>.has_dim_layer = true,
> >>>.has_idle_pc = true,
> >>> + .has_7xxx_intr = true,
> >>>.max_linewidth = 2400,
> >>>.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
> >>>};
> >>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h 
> >>> b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> >>> index c3f1ae000a21..fc1e17c495f0 100644
> >>> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> >>> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> >>> @@ -15,6 +15,7 @@ static const struct dpu_caps sc8280xp_dpu_caps = {
> >>>.has_dim_layer = true,
> >>>.has_idle_pc = true,
> >>>.has_3d_merge = true,
> >>> + .has_7xxx_intr = true,
> >>>.max_linewidth = 5120,
> >>>.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
> >>>};
> >>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h 
> >>> b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> >>> index 86c2e68ebd2c..eb72411c16db 100644
> >>> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> >>> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> >>> @@ -14,6 +14,7 @@ static const struct dpu_caps sm8450_dpu_caps = {
> >>>.has_src_split = true,
> >>>.has_dim_layer = true,
> >>>.has_idle_pc = true,
> >>> + .has_7xxx_intr = true,
> >>>.has_3d_merge = true,
> >>>.max_linewidth = 5120,
> >>>.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
> >>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h 
> >>> b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> >>> index 85dc34458b88..8209ca317bdc 100644
> >>> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> >>> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> >>> @@ -15,6 +15,7 @@ static const struct dpu_caps sm8550_dpu_caps = {
> >>>.has_dim_layer = true,
> >>>.has_idle_pc = true,
> >>>.has_3d_merge = true,
> >>> + .has_7xxx_intr = true,
> >>>.max_linewidth = 5120,
> >>>.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
> >>>};
> >>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h 
> >>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> >>> index 677048cc3b7d..72530ebb0ae6 100644
> >>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> >>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> >>> @@ -351,6 +351,7 @@ struct dpu_rotation_cfg {
> >>> * @has_dim_layer  dim layer feature status
> >>> * @has_idle_pcindicate if idle power collapse feature is 
> >>> supported
> >>> * @has_3d_merge   indicate if 3D merge is supported
> >>> + * @has_7xxx_intr  indicate that INTF/IRQs use addressing for DPU 
> >>> 7.0 and greater
> >>
> >> I see the requirement to distinguish feature support based on the

Re: [Freedreno] [PATCH v2 3/6] drm/msm/dpu: split interrupt address arrays

2023-05-26 Thread Jeykumar Sankaran 




On 5/22/2023 2:45 PM, Dmitry Baryshkov wrote:

There is no point in having a single enum (and a single array) for both
DPU < 7.0 and DPU >= 7.0 interrupt registers. Instead define a single
enum and two IRQ address arrays.

Signed-off-by: Dmitry Baryshkov 
---
  .../msm/disp/dpu1/catalog/dpu_7_0_sm8350.h|  1 +
  .../msm/disp/dpu1/catalog/dpu_7_2_sc7280.h|  1 +
  .../msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h  |  1 +
  .../msm/disp/dpu1/catalog/dpu_8_1_sm8450.h|  1 +
  .../msm/disp/dpu1/catalog/dpu_9_0_sm8550.h|  1 +
  .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h|  2 +
  .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 82 +--
  .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 28 ---
  8 files changed, 79 insertions(+), 38 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h 
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
index 3c1b2c13398d..320cfa4be633 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
@@ -15,6 +15,7 @@ static const struct dpu_caps sm8350_dpu_caps = {
.has_dim_layer = true,
.has_idle_pc = true,
.has_3d_merge = true,
+   .has_7xxx_intr = true,
.max_linewidth = 4096,
.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
  };
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h 
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
index 5d894cbb0a62..9306c7a115e9 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
@@ -13,6 +13,7 @@ static const struct dpu_caps sc7280_dpu_caps = {
.qseed_type = DPU_SSPP_SCALER_QSEED4,
.has_dim_layer = true,
.has_idle_pc = true,
+   .has_7xxx_intr = true,
.max_linewidth = 2400,
.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
  };
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h 
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
index c3f1ae000a21..fc1e17c495f0 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
@@ -15,6 +15,7 @@ static const struct dpu_caps sc8280xp_dpu_caps = {
.has_dim_layer = true,
.has_idle_pc = true,
.has_3d_merge = true,
+   .has_7xxx_intr = true,
.max_linewidth = 5120,
.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
  };
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h 
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
index 86c2e68ebd2c..eb72411c16db 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
@@ -14,6 +14,7 @@ static const struct dpu_caps sm8450_dpu_caps = {
.has_src_split = true,
.has_dim_layer = true,
.has_idle_pc = true,
+   .has_7xxx_intr = true,
.has_3d_merge = true,
.max_linewidth = 5120,
.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h 
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
index 85dc34458b88..8209ca317bdc 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
@@ -15,6 +15,7 @@ static const struct dpu_caps sm8550_dpu_caps = {
.has_dim_layer = true,
.has_idle_pc = true,
.has_3d_merge = true,
+   .has_7xxx_intr = true,
.max_linewidth = 5120,
.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
  };
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 677048cc3b7d..72530ebb0ae6 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -351,6 +351,7 @@ struct dpu_rotation_cfg {
   * @has_dim_layer  dim layer feature status
   * @has_idle_pcindicate if idle power collapse feature is supported
   * @has_3d_merge   indicate if 3D merge is supported
+ * @has_7xxx_intr  indicate that INTF/IRQs use addressing for DPU 7.0 and 
greater


I see the requirement to distinguish feature support based on the DPU 
version in more than one series. Is it a good idea to bring in the DPU 
version info in chipset catalog? This will relieve us from maintaining 
such version flags for individual HW sub-blocks.


Thanks and Regards,
Jeykumar S.


   * @max_linewidth  max linewidth for sspp
   * @pixel_ram_size size of latency hiding and de-tiling buffer in bytes
   * @max_hdeci_exp  max horizontal decimation supported (max is 2^value)
@@ -364,6 +365,7 @@ struct dpu_caps {
bool has_dim_layer;
bool has_idle_pc;
bool has_3d_merge;
+   bool has_7xxx_intr;
/* SSPP limits */
u32 max_linewidth;
u32 pixel_ram_size;
diff --git

Re: [Freedreno] [PATCH v2 3/6] drm/msm/dpu: split interrupt address arrays

2023-05-25 Thread Abhinav Kumar 




On 5/25/2023 3:30 PM, Dmitry Baryshkov wrote:

On Fri, 26 May 2023 at 00:40, Jeykumar Sankaran
 wrote:




On 5/22/2023 2:45 PM, Dmitry Baryshkov wrote:

There is no point in having a single enum (and a single array) for both
DPU < 7.0 and DPU >= 7.0 interrupt registers. Instead define a single
enum and two IRQ address arrays.

Signed-off-by: Dmitry Baryshkov 
---
   .../msm/disp/dpu1/catalog/dpu_7_0_sm8350.h|  1 +
   .../msm/disp/dpu1/catalog/dpu_7_2_sc7280.h|  1 +
   .../msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h  |  1 +
   .../msm/disp/dpu1/catalog/dpu_8_1_sm8450.h|  1 +
   .../msm/disp/dpu1/catalog/dpu_9_0_sm8550.h|  1 +
   .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h|  2 +
   .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 82 +--
   .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 28 ---
   8 files changed, 79 insertions(+), 38 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h 
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
index 3c1b2c13398d..320cfa4be633 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
@@ -15,6 +15,7 @@ static const struct dpu_caps sm8350_dpu_caps = {
   .has_dim_layer = true,
   .has_idle_pc = true,
   .has_3d_merge = true,
+ .has_7xxx_intr = true,
   .max_linewidth = 4096,
   .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
   };
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h 
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
index 5d894cbb0a62..9306c7a115e9 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
@@ -13,6 +13,7 @@ static const struct dpu_caps sc7280_dpu_caps = {
   .qseed_type = DPU_SSPP_SCALER_QSEED4,
   .has_dim_layer = true,
   .has_idle_pc = true,
+ .has_7xxx_intr = true,
   .max_linewidth = 2400,
   .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
   };
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h 
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
index c3f1ae000a21..fc1e17c495f0 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
@@ -15,6 +15,7 @@ static const struct dpu_caps sc8280xp_dpu_caps = {
   .has_dim_layer = true,
   .has_idle_pc = true,
   .has_3d_merge = true,
+ .has_7xxx_intr = true,
   .max_linewidth = 5120,
   .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
   };
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h 
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
index 86c2e68ebd2c..eb72411c16db 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
@@ -14,6 +14,7 @@ static const struct dpu_caps sm8450_dpu_caps = {
   .has_src_split = true,
   .has_dim_layer = true,
   .has_idle_pc = true,
+ .has_7xxx_intr = true,
   .has_3d_merge = true,
   .max_linewidth = 5120,
   .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h 
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
index 85dc34458b88..8209ca317bdc 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
@@ -15,6 +15,7 @@ static const struct dpu_caps sm8550_dpu_caps = {
   .has_dim_layer = true,
   .has_idle_pc = true,
   .has_3d_merge = true,
+ .has_7xxx_intr = true,
   .max_linewidth = 5120,
   .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
   };
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 677048cc3b7d..72530ebb0ae6 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -351,6 +351,7 @@ struct dpu_rotation_cfg {
* @has_dim_layer  dim layer feature status
* @has_idle_pcindicate if idle power collapse feature is supported
* @has_3d_merge   indicate if 3D merge is supported
+ * @has_7xxx_intr  indicate that INTF/IRQs use addressing for DPU 7.0 and 
greater


I see the requirement to distinguish feature support based on the DPU
version in more than one series. Is it a good idea to bring in the DPU
version info in chipset catalog? This will relieve us from maintaining
such version flags for individual HW sub-blocks.


This would not play well with the rest of the driver. The driver
usually does not compute features by DPU revision. Instead it lists
feature flags.



So I am increasingly seeing examples such as data_compress, widebus 
where it looks like version based enablement in the code will be just 
more efficient. For example.


if (DPU_MAJOR_VER > xxx && DPU_MAJOR_VER < yyy)
enable data_compress;

will be much easier to

Re: [Freedreno] [PATCH v2 3/6] drm/msm/dpu: split interrupt address arrays

2023-05-25 Thread Dmitry Baryshkov 
On Fri, 26 May 2023 at 00:40, Jeykumar Sankaran
 wrote:
>
>
>
> On 5/22/2023 2:45 PM, Dmitry Baryshkov wrote:
> > There is no point in having a single enum (and a single array) for both
> > DPU < 7.0 and DPU >= 7.0 interrupt registers. Instead define a single
> > enum and two IRQ address arrays.
> >
> > Signed-off-by: Dmitry Baryshkov 
> > ---
> >   .../msm/disp/dpu1/catalog/dpu_7_0_sm8350.h|  1 +
> >   .../msm/disp/dpu1/catalog/dpu_7_2_sc7280.h|  1 +
> >   .../msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h  |  1 +
> >   .../msm/disp/dpu1/catalog/dpu_8_1_sm8450.h|  1 +
> >   .../msm/disp/dpu1/catalog/dpu_9_0_sm8550.h|  1 +
> >   .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h|  2 +
> >   .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 82 +--
> >   .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 28 ---
> >   8 files changed, 79 insertions(+), 38 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h 
> > b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> > index 3c1b2c13398d..320cfa4be633 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> > @@ -15,6 +15,7 @@ static const struct dpu_caps sm8350_dpu_caps = {
> >   .has_dim_layer = true,
> >   .has_idle_pc = true,
> >   .has_3d_merge = true,
> > + .has_7xxx_intr = true,
> >   .max_linewidth = 4096,
> >   .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
> >   };
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h 
> > b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> > index 5d894cbb0a62..9306c7a115e9 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> > @@ -13,6 +13,7 @@ static const struct dpu_caps sc7280_dpu_caps = {
> >   .qseed_type = DPU_SSPP_SCALER_QSEED4,
> >   .has_dim_layer = true,
> >   .has_idle_pc = true,
> > + .has_7xxx_intr = true,
> >   .max_linewidth = 2400,
> >   .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
> >   };
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h 
> > b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> > index c3f1ae000a21..fc1e17c495f0 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> > @@ -15,6 +15,7 @@ static const struct dpu_caps sc8280xp_dpu_caps = {
> >   .has_dim_layer = true,
> >   .has_idle_pc = true,
> >   .has_3d_merge = true,
> > + .has_7xxx_intr = true,
> >   .max_linewidth = 5120,
> >   .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
> >   };
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h 
> > b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> > index 86c2e68ebd2c..eb72411c16db 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> > @@ -14,6 +14,7 @@ static const struct dpu_caps sm8450_dpu_caps = {
> >   .has_src_split = true,
> >   .has_dim_layer = true,
> >   .has_idle_pc = true,
> > + .has_7xxx_intr = true,
> >   .has_3d_merge = true,
> >   .max_linewidth = 5120,
> >   .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h 
> > b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> > index 85dc34458b88..8209ca317bdc 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> > @@ -15,6 +15,7 @@ static const struct dpu_caps sm8550_dpu_caps = {
> >   .has_dim_layer = true,
> >   .has_idle_pc = true,
> >   .has_3d_merge = true,
> > + .has_7xxx_intr = true,
> >   .max_linewidth = 5120,
> >   .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
> >   };
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h 
> > b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> > index 677048cc3b7d..72530ebb0ae6 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> > @@ -351,6 +351,7 @@ struct dpu_rotation_cfg {
> >* @has_dim_layer  dim layer feature status
> >* @has_idle_pcindicate if idle power collapse feature is 
> > supported
> >* @has_3d_merge   indicate if 3D merge is supported
> > + * @has_7xxx_intr  indicate that INTF/IRQs use addressing for DPU 7.0 
> > and greater
>
> I see the requirement to distinguish feature support based on the DPU
> version in more than one series. Is it a good idea to bring in the DPU
> version info in chipset catalog? This will relieve us from maintaining
> such version flags for individual HW sub-blocks.

This would not play well with the rest of the driver. The driver
usually does not compute features by DPU revision. Instead it lists