[PATCH] drm/msm: Update generated headers (PLL registers)
This change includes the generated file of the following:
rnndb: Add 28nm PLL register description
Each interface (DSI/eDP/HDMI) has to control its own PLL.
This change only add the register description for each one of them.
Let's not make the register description common as some registers
may not be implemented the same way for each interface PHY.
v2:
- Add description for more bit fields
- Rebase on change "rnndb: dsi: Add DSI_LANE_CTRL info"
Signed-off-by: Stephane Viau
Signed-off-by: Hai Li
---
drivers/gpu/drm/msm/dsi/dsi.xml.h | 149 +++-
drivers/gpu/drm/msm/edp/edp.xml.h | 104 +
drivers/gpu/drm/msm/hdmi/hdmi.xml.h | 102 +---
3 files changed, 330 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi.xml.h
b/drivers/gpu/drm/msm/dsi/dsi.xml.h
index 06c1441..4e4a700 100644
--- a/drivers/gpu/drm/msm/dsi/dsi.xml.h
+++ b/drivers/gpu/drm/msm/dsi/dsi.xml.h
@@ -8,7 +8,7 @@ http://github.com/freedreno/envytools/
git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are:
-- /usr2/hali/local/envytools/envytools/rnndb/dsi/dsi.xml ( 18802
bytes, from 2015-05-06 21:35:51)
+- /usr2/hali/local/envytools/envytools/rnndb/dsi/dsi.xml ( 22094
bytes, from 2015-05-06 21:40:40)
- /usr2/hali/local/envytools/envytools/rnndb/freedreno_copyright.xml ( 1453
bytes, from 2015-01-28 21:43:22)
Copyright (C) 2013-2015 by the following authors:
@@ -838,5 +838,152 @@ static inline uint32_t
DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)
#define REG_DSI_28nm_PHY_REGULATOR_CAL_PWR_CFG 0x0018
+#define REG_DSI_28nm_PHY_PLL_REFCLK_CFG
0x
+#define DSI_28nm_PHY_PLL_REFCLK_CFG_DBLR 0x0001
+
+#define REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG 0x0004
+
+#define REG_DSI_28nm_PHY_PLL_CHGPUMP_CFG 0x0008
+
+#define REG_DSI_28nm_PHY_PLL_VCOLPF_CFG
0x000c
+
+#define REG_DSI_28nm_PHY_PLL_VREG_CFG 0x0010
+#define DSI_28nm_PHY_PLL_VREG_CFG_POSTDIV1_BYPASS_B0x0002
+
+#define REG_DSI_28nm_PHY_PLL_PWRGEN_CFG
0x0014
+
+#define REG_DSI_28nm_PHY_PLL_DMUX_CFG 0x0018
+
+#define REG_DSI_28nm_PHY_PLL_AMUX_CFG 0x001c
+
+#define REG_DSI_28nm_PHY_PLL_GLB_CFG 0x0020
+#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B 0x0001
+#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B 0x0002
+#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B0x0004
+#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE0x0008
+
+#define REG_DSI_28nm_PHY_PLL_POSTDIV2_CFG 0x0024
+
+#define REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG 0x0028
+
+#define REG_DSI_28nm_PHY_PLL_LPFR_CFG 0x002c
+
+#define REG_DSI_28nm_PHY_PLL_LPFC1_CFG 0x0030
+
+#define REG_DSI_28nm_PHY_PLL_LPFC2_CFG 0x0034
+
+#define REG_DSI_28nm_PHY_PLL_SDM_CFG0 0x0038
+#define DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__MASK
0x003f
+#define DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__SHIFT 0
+static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV(uint32_t val)
+{
+ return ((val) << DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__SHIFT) &
DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__MASK;
+}
+#define DSI_28nm_PHY_PLL_SDM_CFG0_BYP 0x0040
+
+#define REG_DSI_28nm_PHY_PLL_SDM_CFG1 0x003c
+#define DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__MASK 0x003f
+#define DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__SHIFT 0
+static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET(uint32_t val)
+{
+ return ((val) << DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__SHIFT) &
DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__MASK;
+}
+#define DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__MASK 0x0040
+#define DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__SHIFT 6
+static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN(uint32_t val)
+{
+ return ((val) << DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__SHIFT) &
DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__MASK;
+}
+
+#define REG_DSI_28nm_PHY_PLL_SDM_CFG2 0x0040
+#define DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__MASK 0x00ff
+#define DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__SHIFT 0
+static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0(uint32_t val)
+{
+ return ((val) << DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__SHIFT) &
DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__MASK;
+}
+
+#define
[PATCH] drm/msm: Update generated headers (PLL registers)
This change includes the generated file of the following: rnndb: Add 28nm PLL register description Each interface (DSI/eDP/HDMI) has to control its own PLL. This change only add the register description for each one of them. Let's not make the register description common as some registers may not be implemented the same way for each interface PHY. Signed-off-by: Stephane Viau --- drivers/gpu/drm/msm/dsi/dsi.xml.h | 118 +++- drivers/gpu/drm/msm/edp/edp.xml.h | 104 +++ drivers/gpu/drm/msm/hdmi/hdmi.xml.h | 99 ++ 3 files changed, 295 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/drm/msm/dsi/dsi.xml.h b/drivers/gpu/drm/msm/dsi/dsi.xml.h index 1dcfae2..aa63952 100644 --- a/drivers/gpu/drm/msm/dsi/dsi.xml.h +++ b/drivers/gpu/drm/msm/dsi/dsi.xml.h @@ -8,8 +8,8 @@ http://github.com/freedreno/envytools/ git clone https://github.com/freedreno/envytools.git The rules-ng-ng source files this header was generated from are: -- /usr2/hali/local/envytools/envytools/rnndb/dsi/dsi.xml ( 18681 bytes, from 2015-03-04 23:08:31) -- /usr2/hali/local/envytools/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-01-28 21:43:22) +- /local/mnt2/workspace2/sviau/envytools/rnndb/dsi/dsi.xml ( 21462 bytes, from 2015-04-30 16:36:31) +- /local/mnt2/workspace2/sviau/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-04-30 16:26:30) Copyright (C) 2013-2015 by the following authors: - Rob Clark (robclark) @@ -835,5 +835,119 @@ static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val) #define REG_DSI_28nm_PHY_REGULATOR_CAL_PWR_CFG 0x0018 +#define REG_DSI_28nm_PHY_PLL_REFCLK_CFG 0x + +#define REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG 0x0004 + +#define REG_DSI_28nm_PHY_PLL_CHGPUMP_CFG 0x0008 + +#define REG_DSI_28nm_PHY_PLL_VCOLPF_CFG 0x000c + +#define REG_DSI_28nm_PHY_PLL_VREG_CFG 0x0010 + +#define REG_DSI_28nm_PHY_PLL_PWRGEN_CFG 0x0014 + +#define REG_DSI_28nm_PHY_PLL_DMUX_CFG 0x0018 + +#define REG_DSI_28nm_PHY_PLL_AMUX_CFG 0x001c + +#define REG_DSI_28nm_PHY_PLL_GLB_CFG 0x0020 +#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B 0x0001 +#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B 0x0002 +#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B0x0004 +#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE0x0008 + +#define REG_DSI_28nm_PHY_PLL_POSTDIV2_CFG 0x0024 + +#define REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG 0x0028 + +#define REG_DSI_28nm_PHY_PLL_LPFR_CFG 0x002c + +#define REG_DSI_28nm_PHY_PLL_LPFC1_CFG 0x0030 + +#define REG_DSI_28nm_PHY_PLL_LPFC2_CFG 0x0034 + +#define REG_DSI_28nm_PHY_PLL_SDM_CFG0 0x0038 + +#define REG_DSI_28nm_PHY_PLL_SDM_CFG1 0x003c + +#define REG_DSI_28nm_PHY_PLL_SDM_CFG2 0x0040 + +#define REG_DSI_28nm_PHY_PLL_SDM_CFG3 0x0044 + +#define REG_DSI_28nm_PHY_PLL_SDM_CFG4 0x0048 + +#define REG_DSI_28nm_PHY_PLL_SSC_CFG0 0x004c + +#define REG_DSI_28nm_PHY_PLL_SSC_CFG1 0x0050 + +#define REG_DSI_28nm_PHY_PLL_SSC_CFG2 0x0054 + +#define REG_DSI_28nm_PHY_PLL_SSC_CFG3 0x0058 + +#define REG_DSI_28nm_PHY_PLL_LKDET_CFG0 0x005c + +#define REG_DSI_28nm_PHY_PLL_LKDET_CFG1 0x0060 + +#define REG_DSI_28nm_PHY_PLL_LKDET_CFG2 0x0064 + +#define REG_DSI_28nm_PHY_PLL_TEST_CFG 0x0068 +#define DSI_28nm_PHY_PLL_TEST_CFG_PLL_SW_RESET 0x0001 + +#define REG_DSI_28nm_PHY_PLL_CAL_CFG0 0x006c + +#define REG_DSI_28nm_PHY_PLL_CAL_CFG1 0x0070 + +#define REG_DSI_28nm_PHY_PLL_CAL_CFG2 0x0074 + +#define REG_DSI_28nm_PHY_PLL_CAL_CFG3 0x0078 + +#define REG_DSI_28nm_PHY_PLL_CAL_CFG4 0x007c + +#define REG_DSI_28nm_PHY_PLL_CAL_CFG5 0x0080 + +#define REG_DSI_28nm_PHY_PLL_CAL_CFG6 0x0084 + +#define REG_DSI_28nm_PHY_PLL_CAL_CFG7 0x0088 + +#define REG_DSI_28nm_PHY_PLL_CAL_CFG8 0x008c + +#define
