[v2] [PATCH 00/11] drm/msm: A5XX preemption

Here is v2 of the preemption series - Changes: * Refactored API in DRM_IOCTL_MSM_GEM_INFO (Thanks Emil Velikov) * Removed preemption worker and fixed atomics (Thanks Stephen Boyd) * Various fixes and improvements based on testing Thanks! Jordan Jordan Crouse (11): drm/msm: Make sure to

Re: [Intel-gfx] [PATCH 00/11] drm/msm: A5XX preemption

On Mon, Feb 6, 2017 at 1:23 PM, Daniel Stone wrote: > Hi, > > On 6 February 2017 at 17:59, Daniel Vetter wrote: >> On Mon, Feb 06, 2017 at 10:39:28AM -0700, Jordan Crouse wrote: >>> This initial series implements 4 ringbuffers to give sufficient coverage

Re: [PATCH 00/11] drm/msm: A5XX preemption

On Mon, Feb 6, 2017 at 12:59 PM, Daniel Vetter wrote: > On Mon, Feb 06, 2017 at 10:39:28AM -0700, Jordan Crouse wrote: >> This series of patches implements multiple ringbuffers and preemption for >> Adreno >> A5XX targets. Preemption allows a command to be interrupted at

Re: [PATCH 00/11] drm/msm: A5XX preemption

Hi, On 6 February 2017 at 17:59, Daniel Vetter wrote: > On Mon, Feb 06, 2017 at 10:39:28AM -0700, Jordan Crouse wrote: >> This initial series implements 4 ringbuffers to give sufficient coverage for >> the >> range of priority levels requested by the GLES and compute

Re: [PATCH 00/11] drm/msm: A5XX preemption

On Mon, Feb 06, 2017 at 10:39:28AM -0700, Jordan Crouse wrote: > This series of patches implements multiple ringbuffers and preemption for > Adreno > A5XX targets. Preemption allows a command to be interrupted at specific > preemption points and execution switched to a different ringbuffer. > >

[PATCH 00/11] drm/msm: A5XX preemption

This series of patches implements multiple ringbuffers and preemption for Adreno A5XX targets. Preemption allows a command to be interrupted at specific preemption points and execution switched to a different ringbuffer. The software alogrithm uses preemption to enforce quality of service for