On 01/20/2017 01:47 AM, Stephen Boyd wrote:
On 01/07, Archit Taneja wrote:
+
+static struct clk *pll_14nm_postdiv_register(struct dsi_pll_14nm *pll_14nm,
+const char *name,
+const char *parent_name,
+
On 01/07, Archit Taneja wrote:
> +
> +static struct clk *pll_14nm_postdiv_register(struct dsi_pll_14nm *pll_14nm,
> + const char *name,
> + const char *parent_name,
> +
Extend the DSI PHY/PLL drivers to support the DSI 14nm PHY/PLL
found on 8x96.
These are picked up from the downstream driver. The PHY part is similar
to the other DSI PHYs. The PLL driver requires some trickery so that
one DSI PLL can drive both the DSIs (i.e, dual DSI mode).
In the case of dual
