[PATCH 2/3] drm/i915/mtl: Modify CAGF functions for MTL

[Ashutosh Dixit]

From: Badal Nilawar <badal.nila...@intel.com>

Update CAGF functions for MTL to get actual resolved frequency of 3D and
SAMedia.

v2: Update MTL_MIRROR_TARGET_WP1 position/formatting (MattR)
    Move MTL branches in cagf functions to top (MattR)
    Fix commit message (Andi)

Bspec: 66300

Signed-off-by: Ashutosh Dixit <ashutosh.di...@intel.com>
Signed-off-by: Badal Nilawar <badal.nila...@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_gt_regs.h | 4 ++++
 drivers/gpu/drm/i915/gt/intel_rps.c     | 8 ++++++--
 2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h 
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 7f79bbf978284..66867747f643e 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -8,6 +8,10 @@
 
 #include "i915_reg_defs.h"
 
+/* MTL workpoint reg to get core C state and actual freq of 3D, SAMedia */
+#define MTL_MIRROR_TARGET_WP1                  _MMIO(0xc60)
+#define   MTL_CAGF_MASK                                REG_GENMASK(8, 0)
+
 /* RPM unit config (Gen8+) */
 #define RPM_CONFIG0                            _MMIO(0xd00)
 #define   GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT    3
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c 
b/drivers/gpu/drm/i915/gt/intel_rps.c
index fc23c562d9b2a..59ca7e80e4c6f 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -2073,7 +2073,9 @@ u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat)
        struct drm_i915_private *i915 = rps_to_i915(rps);
        u32 cagf;
 
-       if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
+       if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
+               cagf = rpstat & MTL_CAGF_MASK;
+       else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
                cagf = (rpstat >> 8) & 0xff;
        else if (GRAPHICS_VER(i915) >= 9)
                cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
@@ -2094,7 +2096,9 @@ static u32 read_cagf(struct intel_rps *rps)
        struct intel_uncore *uncore = rps_to_uncore(rps);
        u32 freq;
 
-       if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
+       if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) {
+               freq = intel_uncore_read(rps_to_gt(rps)->uncore, 
MTL_MIRROR_TARGET_WP1);
+       } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
                vlv_punit_get(i915);
                freq = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS);
                vlv_punit_put(i915);
-- 
2.38.0