Hi,
On 15-01-19 15:55, Ville Syrjälä wrote:
On Sat, Dec 01, 2018 at 12:31:46PM +0100, Hans de Goede wrote:
The display engine has 2 dithering enable bits which both need to be set
for dithering to happen, 1 in the PIPECONF register which is taken care of
by i9xx_set_pipeconf() and a second bit
On Sat, Dec 01, 2018 at 12:31:46PM +0100, Hans de Goede wrote:
> The display engine has 2 dithering enable bits which both need to be set
> for dithering to happen, 1 in the PIPECONF register which is taken care of
> by i9xx_set_pipeconf() and a second bit at the encoder level.
>
> The dsi code
The display engine has 2 dithering enable bits which both need to be set
for dithering to happen, 1 in the PIPECONF register which is taken care of
by i9xx_set_pipeconf() and a second bit at the encoder level.
The dsi code was not setting the encoder level dithering enable bit causing
dithering
