subject:"\[PATCH v1 21\/21\] arm64\: dts\: mt8192\: add display node"

Re: [PATCH v1 21/21] arm64: dts: mt8192: add display node

2020-08-20 Thread Rob Herring

On Thu, Aug 20, 2020 at 12:06 AM Yongqiang Niu
 wrote:
>
> add display node
>
> Signed-off-by: Yongqiang Niu 
> ---
>  arch/arm64/boot/dts/mediatek/mt8192.dtsi | 126 
> +++
>  1 file changed, 126 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi 
> b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 931e1ca..d2a814d 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -17,6 +17,13 @@
> #address-cells = <2>;
> #size-cells = <2>;
>
> +aliases {
> +   ovl0 = &ovl0;
> +   ovl_2l0 = &ovl_2l0;
> +   ovl_2l2 = &ovl_2l2;
> +   rdma0 = &rdma0;
> +   rdma4 = &rdma4;

No, please don't add a bunch of custom aliases that you probably don't need.

> +   };
> clk26m: oscillator@0 {
> compatible = "fixed-clock";
> #clock-cells = <0>;
> @@ -449,6 +456,125 @@
> #clock-cells = <1>;
> };
>
> +mutex: mutex@14001000 {
> +   compatible = "mediatek,mt8192-disp-mutex";
> +   reg = <0 0x14001000 0 0x1000>;
> +   interrupts = ;
> +   clocks = <&mmsys CLK_MM_DISP_CONFIG>,
> +<&mmsys CLK_MM_26MHZ>,
> +<&mmsys CLK_MM_DISP_MUTEX0>;
> +   };
> +   ovl0: ovl@14005000 {
> +   compatible = "mediatek,mt8192-disp-ovl";
> +   reg = <0 0x14005000 0 0x1000>;
> +   interrupts = ;
> +   clocks = <&mmsys CLK_MM_DISP_OVL0>;
> +   //iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>,
> +   //   <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>;
> +   power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
> +   //mediatek,gce-client-reg = <&gce SUBSYS_1400 
> 0x5000 0x1000>;
> +   };
> +
> +   ovl_2l0: ovl@14006000 {
> +   compatible = "mediatek,mt8192-disp-ovl-2l";
> +   reg = <0 0x14006000 0 0x1000>;
> +   interrupts = ;
> +   power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
> +   clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
> +   //iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>,
> +   //   <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>;
> +   //mediatek,gce-client-reg = <&gce SUBSYS_1400 
> 0x6000 0x1000>;
> +   };
> +
> +   rdma0: rdma@14007000 {
> +   compatible = "mediatek,mt8192-disp-rdma";
> +   reg = <0 0x14007000 0 0x1000>;
> +   interrupts = ;
> +   clocks = <&mmsys CLK_MM_DISP_RDMA0>;
> +   //iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>;
> +   mediatek,rdma_fifo_size = <5>;
> +   power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
> +   //mediatek,gce-client-reg = <&gce SUBSYS_1400 
> 0x7000 0x1000>;
> +   };
> +
> +   color0: color@14009000 {
> +   compatible = "mediatek,mt8192-disp-color",
> +"mediatek,mt8173-disp-color";
> +   reg = <0 0x14009000 0 0x1000>;
> +   interrupts = ;
> +   power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
> +   clocks = <&mmsys CLK_MM_DISP_COLOR0>;
> +   //mediatek,gce-client-reg = <&gce SUBSYS_1400 
> 0x9000 0x1000>;
> +   };
> +
> +   ccorr0: ccorr@1400a000 {
> +   compatible = "mediatek,mt8192-disp-ccorr";
> +   reg = <0 0x1400a000 0 0x1000>;
> +   interrupts = ;
> +   power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
> +   clocks = <&mmsys CLK_MM_DISP_CCORR0>;
> +   //mediatek,gce-client-reg = <&gce SUBSYS_1400 
> 0xa000 0x1000>;
> +   };
> +
> +   aal0: aal@1400b000 {
> +   compatible = "mediatek,mt8192-disp-aal";
> +   reg = <0 0x1400b000 0 0x1000>;
> +   interrupts = ;
> +   power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
> +   clocks = <&mmsys CLK_MM_DISP_AAL0>;
> +   //mediatek,gce-client-reg = <&gce SUBSYS_1400 
> 0xb000 0x1000>;
> +   };
> +
> +   gamma0: gamma@1400c000 {
> +   compatible = "mediatek,mt8192-disp-gamma";
> +   reg = <0 0x1400c000 0 0x1000>;
> +   interrupts = ;
> +

[PATCH v1 21/21] arm64: dts: mt8192: add display node

2020-08-20 Thread Yongqiang Niu

add display node

Signed-off-by: Yongqiang Niu 
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 126 +++
 1 file changed, 126 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi 
b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 931e1ca..d2a814d 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -17,6 +17,13 @@
#address-cells = <2>;
#size-cells = <2>;
 
+aliases {
+   ovl0 = &ovl0;
+   ovl_2l0 = &ovl_2l0;
+   ovl_2l2 = &ovl_2l2;
+   rdma0 = &rdma0;
+   rdma4 = &rdma4;
+   };
clk26m: oscillator@0 {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -449,6 +456,125 @@
#clock-cells = <1>;
};
 
+mutex: mutex@14001000 {
+   compatible = "mediatek,mt8192-disp-mutex";
+   reg = <0 0x14001000 0 0x1000>;
+   interrupts = ;
+   clocks = <&mmsys CLK_MM_DISP_CONFIG>,
+<&mmsys CLK_MM_26MHZ>,
+<&mmsys CLK_MM_DISP_MUTEX0>;
+   };
+   ovl0: ovl@14005000 {
+   compatible = "mediatek,mt8192-disp-ovl";
+   reg = <0 0x14005000 0 0x1000>;
+   interrupts = ;
+   clocks = <&mmsys CLK_MM_DISP_OVL0>;
+   //iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>,
+   //   <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>;
+   power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
+   //mediatek,gce-client-reg = <&gce SUBSYS_1400 
0x5000 0x1000>;
+   };
+
+   ovl_2l0: ovl@14006000 {
+   compatible = "mediatek,mt8192-disp-ovl-2l";
+   reg = <0 0x14006000 0 0x1000>;
+   interrupts = ;
+   power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
+   clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
+   //iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>,
+   //   <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>;
+   //mediatek,gce-client-reg = <&gce SUBSYS_1400 
0x6000 0x1000>;
+   };
+
+   rdma0: rdma@14007000 {
+   compatible = "mediatek,mt8192-disp-rdma";
+   reg = <0 0x14007000 0 0x1000>;
+   interrupts = ;
+   clocks = <&mmsys CLK_MM_DISP_RDMA0>;
+   //iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>;
+   mediatek,rdma_fifo_size = <5>;
+   power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
+   //mediatek,gce-client-reg = <&gce SUBSYS_1400 
0x7000 0x1000>;
+   };
+
+   color0: color@14009000 {
+   compatible = "mediatek,mt8192-disp-color",
+"mediatek,mt8173-disp-color";
+   reg = <0 0x14009000 0 0x1000>;
+   interrupts = ;
+   power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
+   clocks = <&mmsys CLK_MM_DISP_COLOR0>;
+   //mediatek,gce-client-reg = <&gce SUBSYS_1400 
0x9000 0x1000>;
+   };
+
+   ccorr0: ccorr@1400a000 {
+   compatible = "mediatek,mt8192-disp-ccorr";
+   reg = <0 0x1400a000 0 0x1000>;
+   interrupts = ;
+   power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
+   clocks = <&mmsys CLK_MM_DISP_CCORR0>;
+   //mediatek,gce-client-reg = <&gce SUBSYS_1400 
0xa000 0x1000>;
+   };
+
+   aal0: aal@1400b000 {
+   compatible = "mediatek,mt8192-disp-aal";
+   reg = <0 0x1400b000 0 0x1000>;
+   interrupts = ;
+   power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
+   clocks = <&mmsys CLK_MM_DISP_AAL0>;
+   //mediatek,gce-client-reg = <&gce SUBSYS_1400 
0xb000 0x1000>;
+   };
+
+   gamma0: gamma@1400c000 {
+   compatible = "mediatek,mt8192-disp-gamma";
+   reg = <0 0x1400c000 0 0x1000>;
+   interrupts = ;
+   power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
+   clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
+   //mediatek,gce-client-reg = <&gce SUBSYS_1400 
0xc000 0x1000>;
+   };
+
+   postmask0: postmask@1400d000 {
+   compatible = "mediatek,mt8192-disp-postmask";
+

Re: [PATCH v1 21/21] arm64: dts: mt8192: add display node

[PATCH v1 21/21] arm64: dts: mt8192: add display node

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