Re: [PATCH v3] drm/msm/dpu: improve DSC allocation

2023-12-11 Thread Dmitry Baryshkov
On Tue, 12 Dec 2023 at 02:03, Kuogee Hsieh wrote: > > > On 12/11/2023 1:30 PM, Dmitry Baryshkov wrote: > > On Mon, 11 Dec 2023 at 20:38, Kuogee Hsieh wrote: > >> A DCE (Display Compression Engine) contains two DSC hard slice > >> encoders. Each DCE start with even DSC encoder index followed by >

Re: [PATCH v3] drm/msm/dpu: improve DSC allocation

2023-12-11 Thread Kuogee Hsieh
On 12/11/2023 1:30 PM, Dmitry Baryshkov wrote: On Mon, 11 Dec 2023 at 20:38, Kuogee Hsieh wrote: A DCE (Display Compression Engine) contains two DSC hard slice encoders. Each DCE start with even DSC encoder index followed by "starts". But it will not be correct. The DCE doesn't start with

Re: [PATCH v3] drm/msm/dpu: improve DSC allocation

2023-12-11 Thread Dmitry Baryshkov
On Mon, 11 Dec 2023 at 20:38, Kuogee Hsieh wrote: > > A DCE (Display Compression Engine) contains two DSC hard slice > encoders. Each DCE start with even DSC encoder index followed by "starts". But it will not be correct. The DCE doesn't start with the DSC encoder. DCE consists of two DSC

[PATCH v3] drm/msm/dpu: improve DSC allocation

2023-12-11 Thread Kuogee Hsieh
A DCE (Display Compression Engine) contains two DSC hard slice encoders. Each DCE start with even DSC encoder index followed by an odd DSC encoder index. Each encoder can work independently. But Only two DSC encoders from same DCE can be paired to work together to support merge mode. In addition,