Add audio front end support of MT8365 SoC.
Update the file header.

Signed-off-by: Alexandre Mergnat <amerg...@baylibre.com>
---
 arch/arm64/boot/dts/mediatek/mt8365.dtsi | 46 +++++++++++++++++++++++++++++---
 1 file changed, 43 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi 
b/arch/arm64/boot/dts/mediatek/mt8365.dtsi
index 24581f7410aa..0bb6f6388bb8 100644
--- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi
@@ -1,10 +1,12 @@
 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
 /*
  * (C) 2018 MediaTek Inc.
- * Copyright (C) 2022 BayLibre SAS
- * Fabien Parent <fpar...@baylibre.com>
- * Bernhard Rosenkränzer <b...@baylibre.com>
+ * Copyright (C) 2024 BayLibre SAS
+ * Authors: Fabien Parent <fpar...@baylibre.com>
+ *         Bernhard Rosenkränzer <b...@baylibre.com>
+ *         Alexandre Mergnat <amerg...@baylibre.com>
  */
+
 #include <dt-bindings/clock/mediatek,mt8365-clk.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
@@ -813,6 +815,44 @@ apu: syscon@19020000 {
                        reg = <0 0x19020000 0 0x1000>;
                        #clock-cells = <1>;
                };
+
+               afe: audio-controller@11220000 {
+                       compatible = "mediatek,mt8365-afe-pcm";
+                       reg = <0 0x11220000 0 0x1000>;
+                       #sound-dai-cells = <0>;
+                       clocks = <&clk26m>,
+                                <&topckgen CLK_TOP_AUDIO_SEL>,
+                                <&topckgen CLK_TOP_AUD_I2S0_M>,
+                                <&topckgen CLK_TOP_AUD_I2S1_M>,
+                                <&topckgen CLK_TOP_AUD_I2S2_M>,
+                                <&topckgen CLK_TOP_AUD_I2S3_M>,
+                                <&topckgen CLK_TOP_AUD_ENGEN1_SEL>,
+                                <&topckgen CLK_TOP_AUD_ENGEN2_SEL>,
+                                <&topckgen CLK_TOP_AUD_1_SEL>,
+                                <&topckgen CLK_TOP_AUD_2_SEL>,
+                                <&topckgen CLK_TOP_APLL_I2S0_SEL>,
+                                <&topckgen CLK_TOP_APLL_I2S1_SEL>,
+                                <&topckgen CLK_TOP_APLL_I2S2_SEL>,
+                                <&topckgen CLK_TOP_APLL_I2S3_SEL>;
+                       clock-names = "top_clk26m_clk",
+                                     "top_audio_sel",
+                                     "audio_i2s0_m",
+                                     "audio_i2s1_m",
+                                     "audio_i2s2_m",
+                                     "audio_i2s3_m",
+                                     "engen1",
+                                     "engen2",
+                                     "aud1",
+                                     "aud2",
+                                     "i2s0_m_sel",
+                                     "i2s1_m_sel",
+                                     "i2s2_m_sel",
+                                     "i2s3_m_sel";
+                       interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>;
+                       power-domains = <&spm MT8365_POWER_DOMAIN_AUDIO>;
+                       mediatek,topckgen = <&topckgen>;
+                       status = "disabled";
+               };
        };
 
        timer {

-- 
2.25.1

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