On Sat, Sep 27, 2014 at 4:12 PM, Boris BREZILLON
wrote:
>> > +static int atmel_hlcdc_rgb_mode_valid(struct drm_connector *connector,
>> > + struct drm_display_mode *mode)
>> > +{
>> > + return MODE_OK;
>> > +}
>>
>> your _mode_valid() should perhaps
Hi Rob,
On Fri, 26 Sep 2014 17:10:49 -0400
Rob Clark wrote:
> On Mon, Sep 8, 2014 at 4:43 AM, Boris BREZILLON
> wrote:
> > The Atmel HLCDC (HLCD Controller) IP available on some Atmel SoCs (i.e.
> > at91sam9n12, at91sam9x5 family or sama5d3 family) provides a display
> > controller device.
> >
On Mon, Sep 8, 2014 at 4:43 AM, Boris BREZILLON
wrote:
> The Atmel HLCDC (HLCD Controller) IP available on some Atmel SoCs (i.e.
> at91sam9n12, at91sam9x5 family or sama5d3 family) provides a display
> controller device.
>
> This display controller supports at least one primary plane and might
>
Hi Thierry,
On 23/09/2014 10:42, Thierry Reding :
> On Tue, Sep 23, 2014 at 09:24:36AM +0200, Boris BREZILLON wrote:
>> Hi Thierry,
>>
>> On Tue, 23 Sep 2014 08:32:33 +0200
>> Thierry Reding wrote:
>>
>>> On Mon, Sep 22, 2014 at 09:18:11PM +0200, Boris BREZILLON wrote:
On Mon, 8 Sep 2014
On Tue, Sep 23, 2014 at 09:24:36AM +0200, Boris BREZILLON wrote:
> Hi Thierry,
>
> On Tue, 23 Sep 2014 08:32:33 +0200
> Thierry Reding wrote:
>
> > On Mon, Sep 22, 2014 at 09:18:11PM +0200, Boris BREZILLON wrote:
> > > On Mon, 8 Sep 2014 10:43:36 +0200 Boris BREZILLON > > free-electrons.com>
Hi Thierry,
On Tue, 23 Sep 2014 08:32:33 +0200
Thierry Reding wrote:
> On Mon, Sep 22, 2014 at 09:18:11PM +0200, Boris BREZILLON wrote:
> > On Mon, 8 Sep 2014 10:43:36 +0200 Boris BREZILLON > free-electrons.com> wrote:
> [...]
> > > diff --git a/drivers/gpu/drm/atmel-hlcdc/Kconfig
> > >
On Mon, Sep 22, 2014 at 09:18:11PM +0200, Boris BREZILLON wrote:
> On Mon, 8 Sep 2014 10:43:36 +0200 Boris BREZILLON free-electrons.com> wrote:
[...]
> > diff --git a/drivers/gpu/drm/atmel-hlcdc/Kconfig
> > b/drivers/gpu/drm/atmel-hlcdc/Kconfig
> > new file mode 100644
> > index
On Mon, 8 Sep 2014 10:43:36 +0200
Boris BREZILLON wrote:
> The Atmel HLCDC (HLCD Controller) IP available on some Atmel SoCs (i.e.
> at91sam9n12, at91sam9x5 family or sama5d3 family) provides a display
> controller device.
>
> This display controller supports at least one primary plane and
Hi David,
On Fri, 19 Sep 2014 15:10:02 +0200
David Herrmann wrote:
> Hi
>
> On Mon, Sep 8, 2014 at 10:43 AM, Boris BREZILLON
> wrote:
> [snip]
> > +static int atmel_hlcdc_dc_drm_probe(struct platform_device *pdev)
> > +{
> > + int ret;
> > +
> > + ret = dma_set_coherent_mask(>dev,
Hi
On Mon, Sep 8, 2014 at 10:43 AM, Boris BREZILLON
wrote:
[snip]
> +static int atmel_hlcdc_dc_drm_probe(struct platform_device *pdev)
> +{
> + int ret;
> +
> + ret = dma_set_coherent_mask(>dev, DMA_BIT_MASK(32));
> + if (ret)
> + return ret;
> +
> + ret =
The Atmel HLCDC (HLCD Controller) IP available on some Atmel SoCs (i.e.
at91sam9n12, at91sam9x5 family or sama5d3 family) provides a display
controller device.
This display controller supports at least one primary plane and might
provide several overlays and an hardware cursor depending on the IP
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