Hi Laurent,
On Wed, 2018-02-21 at 15:17:25 -0800, Laurent Pinchart wrote:
> Hi Hyun,
>
> Thank you for the patch.
>
> On Wednesday, 7 February 2018 03:36:36 EET Hyun Kwon wrote:
> > Xilinx has various platforms for display, where users can create
> > using multiple IPs in the programmable FPGA f
Hi Laurent,
On Thu, 2018-02-22 at 05:40:50 -0800, Laurent Pinchart wrote:
> Hi Hyun,
>
> On Thursday, 22 February 2018 04:50:42 EET Hyun Kwon wrote:
> > On Wed, 2018-02-21 at 15:17:25 -0800, Laurent Pinchart wrote:
> > > On Wednesday, 7 February 2018 03:36:36 EET Hyun Kwon wrote:
> > >> Xilinx ha
Hi Hyun,
On Thursday, 22 February 2018 04:50:42 EET Hyun Kwon wrote:
> On Wed, 2018-02-21 at 15:17:25 -0800, Laurent Pinchart wrote:
> > On Wednesday, 7 February 2018 03:36:36 EET Hyun Kwon wrote:
> >> Xilinx has various platforms for display, where users can create
> >> using multiple IPs in the
Hi Laurent,
On Wed, 2018-02-21 at 15:22:31 -0800, Laurent Pinchart wrote:
> Hi Hyun,
>
> On Tuesday, 20 February 2018 19:11:42 EET hyun.k...@xilinx.com wrote:
> > On Monday, February 19, 2018 1:43 AM Daniel Vetter wrote:
> > > On Tue, Feb 06, 2018 at 05:36:36PM -0800, Hyun Kwon wrote:
> > >> Xili
Hi Laurent,
Thanks for the review.
On Wed, 2018-02-21 at 15:17:25 -0800, Laurent Pinchart wrote:
> Hi Hyun,
>
> Thank you for the patch.
>
> On Wednesday, 7 February 2018 03:36:36 EET Hyun Kwon wrote:
> > Xilinx has various platforms for display, where users can create
> > using multiple IPs in
Hi Hyun,
On Tuesday, 20 February 2018 19:11:42 EET hyun.k...@xilinx.com wrote:
> On Monday, February 19, 2018 1:43 AM Daniel Vetter wrote:
> > On Tue, Feb 06, 2018 at 05:36:36PM -0800, Hyun Kwon wrote:
> >> Xilinx has various platforms for display, where users can create
> >> using multiple IPs in
Hi Hyun,
Thank you for the patch.
On Wednesday, 7 February 2018 03:36:36 EET Hyun Kwon wrote:
> Xilinx has various platforms for display, where users can create
> using multiple IPs in the programmable FPGA fabric, or where
> some hardened piepline is available on the chip. Furthermore,
s/piepli
; Michal Simek ; Laurent Pinchart
>
> Subject: Re: [PATCH v5 1/5] drm: xlnx: Xilinx DRM KMS module
>
> On Tue, Feb 06, 2018 at 05:36:36PM -0800, Hyun Kwon wrote:
> > Xilinx has various platforms for display, where users can create
> > using multiple IPs in the programmable
On Tue, Feb 06, 2018 at 05:36:36PM -0800, Hyun Kwon wrote:
> Xilinx has various platforms for display, where users can create
> using multiple IPs in the programmable FPGA fabric, or where
> some hardened piepline is available on the chip. Furthermore,
> hardened pipeline can also interact with sof
Xilinx has various platforms for display, where users can create
using multiple IPs in the programmable FPGA fabric, or where
some hardened piepline is available on the chip. Furthermore,
hardened pipeline can also interact with soft logics in FPGA.
The Xilinx DRM KMS module is to integrate multip
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