subject:"\[PATCH v5 2\/6\] soc\: mediatek\: add mtk\-mmsys support for mt8195 vdosys0"

Re: [PATCH v5 2/6] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0

2021-08-02 Thread Jason-JH Lin

Hi Enric,

On Fri, 2021-07-30 at 13:41 +0200, Enric Balletbo i Serra wrote:
> Hi Jason,
> 
> Thank you for your patch.
> 
> On 29/7/21 19:07, jason-jh.lin wrote:
> > Add mt8195 vdosys0 clock driver name and routing table to
> > the driver data of mtk-mmsys.
> > 
> 
> This patch is the one that is really introducing mt8195 mmsys
> support. It is a
> bit confusing sent the binding on another patchset. Please include
> [1] in this
> patchset so it's clear.
> 
> [1]
> 
https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/patch/20210722092624.14401-2-jason-jh@mediatek.com/__;!!CTRNKA9wMg0ARbw!3MaHl_gSJTB1nJ3RMsmAf7oLpKF8I3nDGIgkcVBlZ_LjV8Z0g88U5giQCAXRidxVujDS$
>  
Ok, I'll add this.
> 
> > Signed-off-by: jason-jh.lin 
> > ---
> > This patch is base on [1]
> > 
> > [1]add mt8195 SoC DRM binding
> > - 
> > https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/list/?series=519597__;!!CTRNKA9wMg0ARbw!3MaHl_gSJTB1nJ3RMsmAf7oLpKF8I3nDGIgkcVBlZ_LjV8Z0g88U5giQCAXRiX1vDsmL$
> >  
> > ---
> >  drivers/soc/mediatek/mt8195-mmsys.h| 96
> > ++
> >  drivers/soc/mediatek/mtk-mmsys.c   | 11 +++
> >  include/linux/soc/mediatek/mtk-mmsys.h |  9 +++
> >  3 files changed, 116 insertions(+)
> >  create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h
> > 
> > diff --git a/drivers/soc/mediatek/mt8195-mmsys.h
> > b/drivers/soc/mediatek/mt8195-mmsys.h
> > new file mode 100644
> > index ..9339a786ec5d
> > --- /dev/null
> > +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> > @@ -0,0 +1,96 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
> > +
> > +#ifndef __SOC_MEDIATEK_MT8195_MMSYS_H
> > +#define __SOC_MEDIATEK_MT8195_MMSYS_H
> > +
> > +#define MT8195_VDO0_OVL_MOUT_EN
> > 0xf14
> > +#define MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0
> > BIT(0)
> > +#define MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0
> > BIT(1)
> > +#define MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1 BIT(2)
> > +#define MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1
> > BIT(4)
> > +#define MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1
> > BIT(5)
> > +#define MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0 BIT(6)
> > +
> > +#define MT8195_VDO0_SEL_IN 0xf34
> > +#define MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT (0 <<
> > 0)
> > +#define MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1  (1 <<
> > 0)
> > +#define MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0 (2 <<
> > 0)
> > +#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0   
> > (0 << 4)
> > +#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE  (1 <<
> > 4)
> > +#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1   
> > (0 << 5)
> > +#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE  (1 <<
> > 5)
> > +#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE (0 <<
> > 8)
> > +#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT 
> > (1 << 8)
> > +#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT 
> > (0 << 9)
> > +#define MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT  (0 <<
> > 12)
> > +#define MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE  
> > (1 << 12)
> > +#define MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0  (2 <<
> > 12)
> > +#define MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT  
> > (0 << 16)
> > +#define MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0   
> > (1 << 16)
> > +#define MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT  
> > (0 << 17)
> > +#define MT8195_SEL_IN_DSI1_FROM_VPP_MERGE  (1 <<
> > 17)
> > +#define MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1
> > (0 << 20)
> > +#define MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE
> > (1 << 20)
> > +#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN  
> > (0 << 21)
> > +#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1  
> > (1 << 21)
> > +#define MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0
> > (0 << 22)
> > +#define MT8195_SEL_IN_DISP_WDMA0_FROM_VPP_MERGE
> > (1 << 22)
> > +
> > +#define MT8195_VDO0_SEL_OUT
> > 0xf38
> > +#define MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN   (0 <<
> > 0)
> > +#define MT8195_SOUT_DISP_DITHER0_TO_DSI0   (1 <<
> > 0)
> > +#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN   (0 <<
> > 1)
> > +#define MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE  
> > (1 << 1)
> > +#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT  (2 <<
> > 1)
> > +#define MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE 
> > (0 << 4)
> > +#define MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0  
> > (1 << 4)
> > +#define MT8195_SOUT_VPP_MERGE_TO_DSI1

Re: [PATCH v5 2/6] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0

2021-07-30 Thread Enric Balletbo i Serra

Hi Jason,

Thank you for your patch.

On 29/7/21 19:07, jason-jh.lin wrote:
> Add mt8195 vdosys0 clock driver name and routing table to
> the driver data of mtk-mmsys.
> 

This patch is the one that is really introducing mt8195 mmsys support. It is a
bit confusing sent the binding on another patchset. Please include [1] in this
patchset so it's clear.

[1]
https://patchwork.kernel.org/project/linux-mediatek/patch/20210722092624.14401-2-jason-jh@mediatek.com/

> Signed-off-by: jason-jh.lin 
> ---
> This patch is base on [1]
> 
> [1]add mt8195 SoC DRM binding
> - https://patchwork.kernel.org/project/linux-mediatek/list/?series=519597
> ---
>  drivers/soc/mediatek/mt8195-mmsys.h| 96 ++
>  drivers/soc/mediatek/mtk-mmsys.c   | 11 +++
>  include/linux/soc/mediatek/mtk-mmsys.h |  9 +++
>  3 files changed, 116 insertions(+)
>  create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h
> 
> diff --git a/drivers/soc/mediatek/mt8195-mmsys.h 
> b/drivers/soc/mediatek/mt8195-mmsys.h
> new file mode 100644
> index ..9339a786ec5d
> --- /dev/null
> +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> @@ -0,0 +1,96 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +
> +#ifndef __SOC_MEDIATEK_MT8195_MMSYS_H
> +#define __SOC_MEDIATEK_MT8195_MMSYS_H
> +
> +#define MT8195_VDO0_OVL_MOUT_EN  0xf14
> +#define MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0  BIT(0)
> +#define MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0  BIT(1)
> +#define MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1   BIT(2)
> +#define MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1  BIT(4)
> +#define MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1  BIT(5)
> +#define MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0   BIT(6)
> +
> +#define MT8195_VDO0_SEL_IN   0xf34
> +#define MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT   (0 << 0)
> +#define MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1(1 << 0)
> +#define MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0   (2 << 0)
> +#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0 (0 << 4)
> +#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE(1 << 4)
> +#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1 (0 << 5)
> +#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE(1 << 5)
> +#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE   (0 << 8)
> +#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT   (1 << 8)
> +#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT   (0 << 9)
> +#define MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT(0 << 12)
> +#define MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE(1 << 
> 12)
> +#define MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0(2 << 12)
> +#define MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT(0 << 
> 16)
> +#define MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0 (1 << 16)
> +#define MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT(0 << 
> 17)
> +#define MT8195_SEL_IN_DSI1_FROM_VPP_MERGE(1 << 17)
> +#define MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1  (0 << 
> 20)
> +#define MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE  (1 << 
> 20)
> +#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN(0 << 
> 21)
> +#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1(1 << 
> 21)
> +#define MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0  (0 << 
> 22)
> +#define MT8195_SEL_IN_DISP_WDMA0_FROM_VPP_MERGE  (1 << 
> 22)
> +
> +#define MT8195_VDO0_SEL_OUT  0xf38
> +#define MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN (0 << 0)
> +#define MT8195_SOUT_DISP_DITHER0_TO_DSI0 (1 << 0)
> +#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN (0 << 1)
> +#define MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE(1 << 1)
> +#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT(2 << 1)
> +#define MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE   (0 << 4)
> +#define MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0(1 << 4)
> +#define MT8195_SOUT_VPP_MERGE_TO_DSI1(0 << 8)
> +#define MT8195_SOUT_VPP_MERGE_TO_DP_INTF0(1 << 8)
> +#define MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0   (2 << 8)
> +#define MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1  (3 << 8)
> +#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN(4 << 8)
> +#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN(0 << 
> 11)
> +#define MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA0  (1 << 11)
> +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0(0 << 12)
> +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0   (1 << 12)
> +#define

[PATCH v5 2/6] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0

2021-07-29 Thread jason-jh . lin

Add mt8195 vdosys0 clock driver name and routing table to
the driver data of mtk-mmsys.

Signed-off-by: jason-jh.lin 
---
This patch is base on [1]

[1]add mt8195 SoC DRM binding
- https://patchwork.kernel.org/project/linux-mediatek/list/?series=519597
---
 drivers/soc/mediatek/mt8195-mmsys.h| 96 ++
 drivers/soc/mediatek/mtk-mmsys.c   | 11 +++
 include/linux/soc/mediatek/mtk-mmsys.h |  9 +++
 3 files changed, 116 insertions(+)
 create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h

diff --git a/drivers/soc/mediatek/mt8195-mmsys.h 
b/drivers/soc/mediatek/mt8195-mmsys.h
new file mode 100644
index ..9339a786ec5d
--- /dev/null
+++ b/drivers/soc/mediatek/mt8195-mmsys.h
@@ -0,0 +1,96 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_MEDIATEK_MT8195_MMSYS_H
+#define __SOC_MEDIATEK_MT8195_MMSYS_H
+
+#define MT8195_VDO0_OVL_MOUT_EN0xf14
+#define MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0BIT(0)
+#define MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0BIT(1)
+#define MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1 BIT(2)
+#define MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1BIT(4)
+#define MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1BIT(5)
+#define MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0 BIT(6)
+
+#define MT8195_VDO0_SEL_IN 0xf34
+#define MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT (0 << 0)
+#define MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1  (1 << 0)
+#define MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0 (2 << 0)
+#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0   (0 << 4)
+#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE  (1 << 4)
+#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1   (0 << 5)
+#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE  (1 << 5)
+#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE (0 << 8)
+#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT (1 << 8)
+#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT (0 << 9)
+#define MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT  (0 << 12)
+#define MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE  (1 << 12)
+#define MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0  (2 << 12)
+#define MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT  (0 << 16)
+#define MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0   (1 << 16)
+#define MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT  (0 << 17)
+#define MT8195_SEL_IN_DSI1_FROM_VPP_MERGE  (1 << 17)
+#define MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1(0 << 
20)
+#define MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE(1 << 
20)
+#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN  (0 << 21)
+#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1  (1 << 21)
+#define MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0(0 << 
22)
+#define MT8195_SEL_IN_DISP_WDMA0_FROM_VPP_MERGE(1 << 
22)
+
+#define MT8195_VDO0_SEL_OUT0xf38
+#define MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN   (0 << 0)
+#define MT8195_SOUT_DISP_DITHER0_TO_DSI0   (1 << 0)
+#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN   (0 << 1)
+#define MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE  (1 << 1)
+#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT  (2 << 1)
+#define MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE (0 << 4)
+#define MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0  (1 << 4)
+#define MT8195_SOUT_VPP_MERGE_TO_DSI1  (0 << 8)
+#define MT8195_SOUT_VPP_MERGE_TO_DP_INTF0  (1 << 8)
+#define MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0 (2 << 8)
+#define MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1(3 << 8)
+#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN  (4 << 8)
+#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN  (0 << 11)
+#define MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA0(1 << 11)
+#define MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0  (0 << 12)
+#define MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0 (1 << 12)
+#define MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE (2 << 12)
+#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1  (0 << 16)
+#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0  (1 << 16)
+#define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 (2 << 16)
+#define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE (3 << 16)
+
+static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
+   {
+   DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
+   MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0
+

Re: [PATCH v5 2/6] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0

Re: [PATCH v5 2/6] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0

[PATCH v5 2/6] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0

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