On Mon, 6 Oct 2014 16:26:10 +0200
Thierry Reding wrote:
> On Mon, Oct 06, 2014 at 03:53:58PM +0200, Boris Brezillon wrote:
> > On Mon, 6 Oct 2014 14:35:06 +0200
> > Thierry Reding wrote:
> >
> > > On Mon, Oct 06, 2014 at 02:14:40PM +0200, Boris Brezillon wrote:
> > > > On Mon, 6 Oct 2014
On Mon, Oct 06, 2014 at 03:53:58PM +0200, Boris Brezillon wrote:
> On Mon, 6 Oct 2014 14:35:06 +0200
> Thierry Reding wrote:
>
> > On Mon, Oct 06, 2014 at 02:14:40PM +0200, Boris Brezillon wrote:
> > > On Mon, 6 Oct 2014 12:54:34 +0200
> > > Thierry Reding wrote:
> > >
> > > > On Wed, Oct 01,
On Mon, 6 Oct 2014 14:35:06 +0200
Thierry Reding wrote:
> On Mon, Oct 06, 2014 at 02:14:40PM +0200, Boris Brezillon wrote:
> > On Mon, 6 Oct 2014 12:54:34 +0200
> > Thierry Reding wrote:
> >
> > > On Wed, Oct 01, 2014 at 04:53:03PM +0200, Boris Brezillon wrote:
> > > > From: Boris BREZILLON
>
On Mon, Oct 06, 2014 at 02:14:40PM +0200, Boris Brezillon wrote:
> On Mon, 6 Oct 2014 12:54:34 +0200
> Thierry Reding wrote:
>
> > On Wed, Oct 01, 2014 at 04:53:03PM +0200, Boris Brezillon wrote:
> > > From: Boris BREZILLON
> > >
> > > The Atmel HLCDC (HLCD Controller) IP available on some
On Mon, 6 Oct 2014 12:54:34 +0200
Thierry Reding wrote:
> On Wed, Oct 01, 2014 at 04:53:03PM +0200, Boris Brezillon wrote:
> > From: Boris BREZILLON
> >
> > The Atmel HLCDC (HLCD Controller) IP available on some Atmel SoCs (i.e.
> > at91sam9n12, at91sam9x5 family or sama5d3 family) provides a
On Wed, Oct 01, 2014 at 04:53:03PM +0200, Boris Brezillon wrote:
> From: Boris BREZILLON
>
> The Atmel HLCDC (HLCD Controller) IP available on some Atmel SoCs (i.e.
> at91sam9n12, at91sam9x5 family or sama5d3 family) provides a display
> controller device.
>
> The HLCDC block provides a single
From: Boris BREZILLON
The Atmel HLCDC (HLCD Controller) IP available on some Atmel SoCs (i.e.
at91sam9n12, at91sam9x5 family or sama5d3 family) provides a display
controller device.
The HLCDC block provides a single RGB output port, and only supports LCD