On Wed, 2019-12-18 at 19:39 +0900, Chanwoo Choi wrote:
> Hi,
>
> 2019년 12월 18일 (수) 오후 7:19, Artur Świgoń 님이 작성:
> >
> > Hi,
> >
> > Thank you for the review.
> >
> > On Mon, 2019-12-16 at 09:44 +0900, Chanwoo Choi wrote:
> > > Hi,
> > >
> > > On 9/19/19 11:22 PM, Artur Świgoń wrote:
> > > >
Hi,
Thank you for the review.
On Mon, 2019-12-16 at 09:44 +0900, Chanwoo Choi wrote:
> Hi,
>
> On 9/19/19 11:22 PM, Artur Świgoń wrote:
> > From: Artur Świgoń
> >
> > This patch adds interconnect functionality to the exynos-bus devfreq
> > driver.
> >
> > The SoC topology is a graph (or,
Hi,
If possible, I'd like to apply these patches to v5.6-rc1.
It is very useful feature to support the QoS for user device using memory bus.
2019년 12월 18일 (수) 오후 7:48, Artur Świgoń 님이 작성:
>
> On Wed, 2019-12-18 at 19:39 +0900, Chanwoo Choi wrote:
> > Hi,
> >
> > 2019년 12월 18일 (수) 오후 7:19, Artur
Hi,
2019년 12월 18일 (수) 오후 7:19, Artur Świgoń 님이 작성:
>
> Hi,
>
> Thank you for the review.
>
> On Mon, 2019-12-16 at 09:44 +0900, Chanwoo Choi wrote:
> > Hi,
> >
> > On 9/19/19 11:22 PM, Artur Świgoń wrote:
> > > From: Artur Świgoń
> > >
> > > This patch adds interconnect functionality to the
Hi,
On 9/19/19 11:22 PM, Artur Świgoń wrote:
> From: Artur Świgoń
>
> This patch adds interconnect functionality to the exynos-bus devfreq
> driver.
>
> The SoC topology is a graph (or, more specifically, a tree) and most of
> its edges are taken from the devfreq parent-child hierarchy (cf.
>
Hi Artur,
On 12/3/19 2:05 AM, Artur Świgoń wrote:
> Hi Chanwoo,
>
> On Wed, 2019-09-25 at 16:03 +0900, Chanwoo Choi wrote:
>> Hi,
>>
>> I need the time to dig the ICC framework
>> to understand them detailed. After that, I'll review this.
>
> Any updates on this topic?
I'm sorry for delaying
Hi Chanwoo,
On Wed, 2019-09-25 at 16:03 +0900, Chanwoo Choi wrote:
> Hi,
>
> I need the time to dig the ICC framework
> to understand them detailed. After that, I'll review this.
Any updates on this topic?
Regardless of the purpose of this RFC, I think patches 01-04
are still beneficial to
Hi,
On Wed, 2019-09-25 at 16:03 +0900, Chanwoo Choi wrote:
> Hi,
>
> I need the time to dig the ICC framework
> to understand them detailed. After that, I'll review this.
>
> Basically, I agree this approach. But, I'm wondering
> the existing binding method between 'bus_leftbus' and 'bus_dmc'.
Hi,
I need the time to dig the ICC framework
to understand them detailed. After that, I'll review this.
Basically, I agree this approach. But, I'm wondering
the existing binding method between 'bus_leftbus' and 'bus_dmc'.
>From before, I thought that devfreq framework need to
enhance the binding
From: Artur Świgoń
This patch adds interconnect functionality to the exynos-bus devfreq
driver.
The SoC topology is a graph (or, more specifically, a tree) and most of
its edges are taken from the devfreq parent-child hierarchy (cf.
Documentation/devicetree/bindings/devfreq/exynos-bus.txt). Due
10 matches
Mail list logo
