Aapo Tahkola wrote:
Alright. Have you been able to reproduce this with any other app?
Perhaps if it hits in menus it might be able to track it down but I wouldnt try
it otherwise.
Also, does it lock always at the same time or is it random?
No only Quake 3. in-game lockups are rare, most
That makes sense, because (from my understanding) this chipset is
basically an ATI northbridge with an attached Radeon x300 GPU. This is
what enables them to do their UMA+Sideport interleaving technology, I
guess; since the Xpress chip *is* the northbridge, it has direct access
to system
I've been thinking about memory management again, and decided to try a
fresh start. This is a distillation of my thoughts based on two
premises:
1) Use of an ARB_vbo derived API and semantics.
2) An initial implementation focus on an AGP-only manager.
In this email I try and outline the API
This follows on from the previous post to discuss an implementation of
the memory manager for managing only AGP memory.
Right now, I'm primarily concerned with unified memory chipsets, like
i915 and via. This memory manager would be suitable for managing the
AGP memory on non-unified chipsets,
Keith Whitwell wrote:
1) I think this is the first solution for memory management that I can
imagine implementing. Also it's one which gives reasonable
performance when data is being evicted from the GART.
This sounds a little trite reading it back.
This a function of two things,
On Sun, 2006-01-08 at 18:17 +, Keith Whitwell wrote:
In the past there has been talk about mapping user memory into the GTT
aperture as a mechanism to avoid copy-based uploading. What I'm
proposing is that this type of mapping becomes the only or at least
primary way of getting data and
Benjamin Herrenschmidt wrote:
On Sun, 2006-01-08 at 18:17 +, Keith Whitwell wrote:
In the past there has been talk about mapping user memory into the GTT
aperture as a mechanism to avoid copy-based uploading. What I'm
proposing is that this type of mapping becomes the only or at least
On Sun, 2006-01-08 at 22:55 +, Keith Whitwell wrote:
Yes, this I think is addressed by the Map/Unmap semantics from ARB_vbo and
the
additional constraints I included in the design, ie that the only time the
buffer contents are meant to be available as user memory is when they are
Indeed. I think that taking the API from ARB_vbo makes these different
implementations entirely possible. The implementation I am interested in right
now is the AGP one, but don't take that to imply that other implementations and
backends are excluded.
I've tried to provide exactly the
Keith Whitwell wrote:
Right now, I'm primarily concerned with unified memory chipsets, like
i915 and via. This memory manager would be suitable for managing the
AGP memory on non-unified chipsets, but a different implementation
would be needed for the on-card video ram, based more on dma and
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