Dave,
On 2/20/07, Dave Airlie <[EMAIL PROTECTED]> wrote:
>
> How is your card configured?
No on-board RAM.. just UMA... 32MB setup by BIOS..
Hmm. Then our setup is a bit different.
> After looking at the debug output from the fglrx 8.32.5 driver, I think
that
> there is a GART table at
>
> How is your card configured?
No on-board RAM.. just UMA... 32MB setup by BIOS..
> After looking at the debug output from the fglrx 8.32.5 driver, I think that
> there is a GART table at the end of the 128M. (From 0x57fe-0x5800)
> The CP is mapped at 0x5800. (In the GART space.)
> work with the EGL demos. This is because I'd like to help out with EGL
> +MESA development.
>
> Now I'm totally stuck, and suppose I hit a few deeply-rooted problems
> that I cannot solve without in-depth knowledge about DRM memory layout.
>
> DRI/Mesa are fresh GIT checkouts, I also had this pr
Am Dienstag, den 20.02.2007, 18:04 +0100 schrieb Jerome Glisse:
> > (...)
> (...) [1]
Thanks for your hints regarding documentation. My overall impression was
that some parts of the wiki are not tidied up, and many docs are
scattered, but of course one can't expect busy developers to invest very
m
Christian Neumair wrote:
> Dear DRI mailing list,
>
> I'm trying to make my Radeon Mobility M300 (probably PCIE) which is
> reported as
>
> 01:00.0 VGA compatible controller: ATI Technologies Inc M22 [Radeon
> Mobility M300]
>
> work with the EGL demos. This is because I'd like to help out with
On 2/20/07, Christian Neumair <[EMAIL PROTECTED]> wrote:
> Dear DRI mailing list,
>
> I'm trying to make my Radeon Mobility M300 (probably PCIE) which is
> reported as
>
> 01:00.0 VGA compatible controller: ATI Technologies Inc M22 [Radeon
> Mobility M300]
>
> work with the EGL demos. This is becau
Dear DRI mailing list,
I'm trying to make my Radeon Mobility M300 (probably PCIE) which is
reported as
01:00.0 VGA compatible controller: ATI Technologies Inc M22 [Radeon
Mobility M300]
work with the EGL demos. This is because I'd like to help out with EGL
+MESA development.
Now I'm totally st
I've added some info the wiki page on what I've found with the 200M so
far,
quick summary:
1. It should have a PCI GART, the regs work, but it doesn't seem to
function... bummer...
2. Attempts to move all things we currently allocate in GART into
framebuffer, seems to work fine for CP accel f
