for non-coherent DMA PowerPC
Bah, I think I found the problem:
+static inline void *drm_vmalloc_dma(unsigned long size)
+{
+#if defined(__powerpc__) defined(CONFIG_NOT_COHERENT_CACHE)
+ return __vmalloc(size, GFP_KERNEL | __GFP_HIGHMEM,
+PAGE_KERNEL
for non-coherent DMA PowerPC
On Mon, 2008-03-03 at 20:51 +0100, Gerhard Pircher wrote:
Remove the GFP_HIGHMEM from the above. It looks like our cache
flushing isn't going to work for highmem, it would need some
kmap's for that.
Yes, it looks like this was the problem. No kernel oops
This patch fixes bits of the DRM so to make the radeon DRI work on
non-cache coherent PCI DMA variants of the PowerPC processors.
It moves the few places that needs change to wrappers to that
other architectures with similar issues can easily add their
own changes to those wrappers, at least
On Mon, 2008-03-03 at 20:51 +0100, Gerhard Pircher wrote:
Remove the GFP_HIGHMEM from the above. It looks like our cache
flushing isn't going to work for highmem, it would need some
kmap's for that.
Yes, it looks like this was the problem. No kernel oops anymore.
The machine locks up
Xorg (v7.1.1, Debian Etch) crashes with this patch (applied to 2.6.25-rc3)
on my AmigaOne with a Radeon 9200 (PCIGART mode enabled). See the attached
log file for the stack trace.
That doesn't look possible, which is weird... looks like we are passing
0 to clean_dcache_range().
Interestingly
Okay, I changed the code to this:
DRM_DEBUG(dev = 0x%x, bus_address = 0x%x, bus_to_virt = 0x%lx, max_pages =
0x%x\n,
(unsigned int)dev-pdev-dev, bus_address,
(unsigned long)virt_to_bus(bus_address), max_pages);
if (gart_info-gart_table_location == DRM_ATI_GART_MAIN) {
Bah, I think I found the problem:
+static inline void *drm_vmalloc_dma(unsigned long size)
+{
+#if defined(__powerpc__) defined(CONFIG_NOT_COHERENT_CACHE)
+ return __vmalloc(size, GFP_KERNEL | __GFP_HIGHMEM,
+PAGE_KERNEL | _PAGE_NO_CACHE);
+#else
+ return
This patch fixes bits of the DRM so to make the radeon DRI work on
non-cache coherent PCI DMA variants of the PowerPC processors.
It moves the few places that needs change to wrappers to that
other architectures with similar issues can easily add their
own changes to those wrappers, at least
