[Patch] drm: Add the basic check for the detailed timing in EDID

From: Zhao Yakui Sometimes we will get the incorrect display modeline when parsing the detailed timing in EDID. For example: >hsync/vsync width is zero >sync is beyond the blank. So add the basic check for the detailed timing in EDID to avoid the incorrect display modeline. Signed-off-b

Re: [Patch] drm: Add the basic check for the detailed timing in EDID

Dear Yakui, Am Samstag, den 10.10.2009, 16:12 +0800 schrieb yakui.z...@intel.com: […] > + /* it is incorrect if hsync/vsync width is zero */ > + if (!hsync_pulse_width || !vsync_pulse_width) { > + DRM_DEBUG_KMS("Incorrect Detailed timing. " > + "W

[Patch] drm: Add the basic check for the detailed timing in EDID

From: Zhao Yakui Sometimes we will get the incorrect display modeline when parsing the detailed timing in EDID. For example: >hsync/vsync width is zero >sync is beyond the blank. So add the basic check for the detailed timing in EDID to avoid the incorrect display modeline. Signed-off-b