Dave Airlie wrote:
>
>
>
OK. We're using this functionality in Poulsbo, so we should probably
sort this out to avoid breaking things.
>>>Okay I'll try and fix it back up tomorrow..
>>>
>>>
>>>
>
>I've attached my first attempt a
> >>>
> >> OK. We're using this functionality in Poulsbo, so we should probably
> >> sort this out to avoid breaking things.
> >>
> >
> > Okay I'll try and fix it back up tomorrow..
> >
I've attached my first attempt at fixing this up but it messes up by the
time the flags hit the t
Dave Airlie wrote:
>>>
>>>
>> OK. We're using this functionality in Poulsbo, so we should probably
>> sort this out to avoid breaking things.
>>
>
> Okay I'll try and fix it back up tomorrow..
>
>
>> Yes, Eric seems to have the same opinion. I'm not quite sure I understand the
>>
> >
> OK. We're using this functionality in Poulsbo, so we should probably
> sort this out to avoid breaking things.
Okay I'll try and fix it back up tomorrow..
> Yes, Eric seems to have the same opinion. I'm not quite sure I understand the
> reasoning behind it.
> Is it the added complexity
Dave Airlie wrote:
>> Dave, I'd like to see the flag DRM_BO_FLAG_CACHED really mean cache-coherent
>> memory, that is cache coherent also while visible to the GPU. There are HW
>> implementations out there (Poulsbo at least) where this option actually seems
>> to work, althought it's considerably s
Dave Airlie wrote:
>> Dave, I'd like to see the flag DRM_BO_FLAG_CACHED really mean cache-coherent
>> memory, that is cache coherent also while visible to the GPU. There are HW
>> implementations out there (Poulsbo at least) where this option actually seems
>> to work, althought it's considerably s
> Dave, I'd like to see the flag DRM_BO_FLAG_CACHED really mean cache-coherent
> memory, that is cache coherent also while visible to the GPU. There are HW
> implementations out there (Poulsbo at least) where this option actually seems
> to work, althought it's considerably slower for things like
Dave Airlie wrote:
>Hi,
>
>So currently the TTM interface allows the user specify a cacheable
>allocation, and on Intel hardware this gets conflated with using the intel
>snooped memory type in the GART. This is bad as the intel snooped memory
>type comes with its own set of special rules and s
