Hi,
I suspace zcache flushing before fast zclears is not needed on r100 (and removing it adds a couple of q3 frames :).
This patch removes it for these chips. It works fine on rv100, but I wonder if it does on r100/rv200 too.
So, testing is welcome !
Stephane
Index: shared/radeon_state.c =================================================================== RCS file: /cvs/dri/drm/shared/radeon_state.c,v retrieving revision 1.43 diff -u -r1.43 radeon_state.c --- shared/radeon_state.c 7 Feb 2005 21:11:59 -0000 1.43 +++ shared/radeon_state.c 9 Feb 2005 19:15:28 -0000 @@ -832,14 +851,20 @@ clearmask = 0x0; } - BEGIN_RING( 8 ); + if (dev_priv->microcode_version==UCODE_R100) { + BEGIN_RING( 6 ); + } else { + BEGIN_RING( 8 ); + } RADEON_WAIT_UNTIL_2D_IDLE(); OUT_RING_REG( RADEON_RB3D_DEPTHCLEARVALUE, tempRB3D_DEPTHCLEARVALUE); /* what offset is this exactly ? */ OUT_RING_REG( RADEON_RB3D_ZMASKOFFSET, 0 ); - /* need ctlstat, otherwise get some strange black flickering */ - OUT_RING_REG( RADEON_RB3D_ZCACHE_CTLSTAT, RADEON_RB3D_ZC_FLUSH_ALL ); + if (dev_priv->microcode_version!=UCODE_R100) { + /* need ctlstat, otherwise get some strange black flickering */ + OUT_RING_REG( RADEON_RB3D_ZCACHE_CTLSTAT, RADEON_RB3D_ZC_FLUSH_ALL ); + } ADVANCE_RING(); for (i = 0; i < nbox; i++) { Index: shared-core/radeon_state.c =================================================================== RCS file: /cvs/dri/drm/shared-core/radeon_state.c,v retrieving revision 1.48 diff -u -r1.48 radeon_state.c --- shared-core/radeon_state.c 8 Feb 2005 04:17:14 -0000 1.48 +++ shared-core/radeon_state.c 9 Feb 2005 19:15:31 -0000 @@ -818,14 +844,20 @@ clearmask = 0x0; } - BEGIN_RING( 8 ); + if (dev_priv->microcode_version==UCODE_R100) { + BEGIN_RING( 6 ); + } else { + BEGIN_RING( 8 ); + } RADEON_WAIT_UNTIL_2D_IDLE(); OUT_RING_REG( RADEON_RB3D_DEPTHCLEARVALUE, tempRB3D_DEPTHCLEARVALUE); /* what offset is this exactly ? */ OUT_RING_REG( RADEON_RB3D_ZMASKOFFSET, 0 ); - /* need ctlstat, otherwise get some strange black flickering */ - OUT_RING_REG( RADEON_RB3D_ZCACHE_CTLSTAT, RADEON_RB3D_ZC_FLUSH_ALL ); + if (dev_priv->microcode_version!=UCODE_R100) { + /* need ctlstat, otherwise get some strange black flickering */ + OUT_RING_REG( RADEON_RB3D_ZCACHE_CTLSTAT, RADEON_RB3D_ZC_FLUSH_ALL ); + } ADVANCE_RING(); for (i = 0; i < nbox; i++) {