Jesse Barnes wrote:
Ok, so I've got everything built and the sample server starts (after applying the attached patch):
[EMAIL PROTECTED] miniglx]# ./sample_server [miniglx] probed chipset 0x4e4b got MMIOAddress 0x2000000010900000 offset 268435456 [drm] added 65536 byte SAREA at 0xa000000204fa0000 [drm] mapped SAREA 0xa000000204fa0000 to 0x2000000011200000, size 65536 [drm] framebuffer handle = 0xc0000041c8000000 [drm] register handle = 0xc0000041c0100000 [pci] 8192 kB allocated with handle 0x0551c000 [pci] ring handle = 0xa00000020551c000 [pci] ring read ptr handle = 0xa000000205620000 [pci] vertex/indirect buffers handle = 0xa000000205624000 [pci] GART texture map handle = 0xa000000205824000 Using 8 MB AGP aperture Using 1 MB for the ring buffer Using 2 MB for vertex/indirect buffers Using 1 MB for AGP textures Will use back buffer at offset 0x600000 Will use depth buffer at offset 0xb00000 Will use 245760 kb for textures at offset 0x1000000 [drm] Added 32 65536 byte vertex/indirect buffers [drm] dma control initialized, using IRQ 67 [drm] Initialized kernel gart heap manager, 5111808 page flipping disabled [miniglx] Setting mode: visible 1280x1024 virtual 1280x1024x32 [miniglx] Readback mode: visible 1280x1024 virtual 1280x1024x32 RADEONEngineRestore [1]+ Stopped ./sample_server [EMAIL PROTECTED] miniglx]# bg
then I start up the sample test app:
[EMAIL PROTECTED] miniglx]# ./miniglxtest [miniglx] probed chipset 0x4e4b CreateNotify Authorize - magic 1 Unknown device ID 4E4B, please report. Assuming plain R300. Using 8 maximum texture units.. sizeof(drm_r300_cmd_header_t)=4 sizeof(drm_radeon_cmd_buffer_t)=32 Allocating 284420 bytes command buffer (max state is 11140 bytes) *********************************WARN_ONCE********************************* File r300_state.c function r300Enable line 516 Don't know how to enable polygon offset point/line. Help me ! *************************************************************************** DestroyNotify Segmentation fault
Any ideas? Is this because I'm using the radeon server/ directory (at least it looks like the r300 dir's server/ dir has items symlinked back to radeon/)?
Ok, I (finally) found it.
You need the attached one-liner to set the mode. The rest is just something I have in my tree to make it gcc2-friendly.
Stephane
Index: miniglx.c =================================================================== RCS file: /cvs/mesa/Mesa/src/glx/mini/miniglx.c,v retrieving revision 1.17 diff -u -r1.17 miniglx.c --- miniglx.c 5 Jan 2005 22:40:34 -0000 1.17 +++ miniglx.c 5 Mar 2005 03:27:48 -0000 @@ -1103,6 +1103,7 @@ drmVersionPtr version; drm_handle_t hFB; int junk; + drm_magic_t magic; err_msg = "XF86DRIOpenConnection"; err_extra = NULL; @@ -1117,8 +1118,6 @@ if (fd < 0) goto done; - drm_magic_t magic; - err_msg = "drmGetMagic"; err_extra = NULL; @@ -1989,6 +1988,7 @@ else sharePriv = NULL; + ctx->driContext.mode = vis->visual->mode; ctx->driContext.private = dpy->driScreen.createNewContext(dpy, vis->visual->mode, GLX_WINDOW_BIT, sharePriv, &ctx->driContext);